trace: reimplement the DTRACE function so it doesn't use a vector

At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing.  This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
This commit is contained in:
Nathan Binkert 2011-04-15 10:44:32 -07:00
parent f946d7bcdb
commit eddac53ff6
221 changed files with 740 additions and 340 deletions

View file

@ -198,21 +198,23 @@ Export('UnitTest')
########################################################################
#
# Trace Flags
# Debug Flags
#
trace_flags = {}
def TraceFlag(name, desc=None):
if name in trace_flags:
debug_flags = {}
def DebugFlag(name, desc=None):
if name in debug_flags:
raise AttributeError, "Flag %s already specified" % name
trace_flags[name] = (name, (), desc)
debug_flags[name] = (name, (), desc)
TraceFlag = DebugFlag
def CompoundFlag(name, flags, desc=None):
if name in trace_flags:
if name in debug_flags:
raise AttributeError, "Flag %s already specified" % name
compound = tuple(flags)
trace_flags[name] = (name, compound, desc)
debug_flags[name] = (name, compound, desc)
Export('DebugFlag')
Export('TraceFlag')
Export('CompoundFlag')
@ -622,81 +624,16 @@ for swig in SwigSource.all:
MakeAction(makeEmbeddedSwigInit, Transform("EMBED SW")))
Source(init_file)
def getFlags(source_flags):
flagsMap = {}
flagsList = []
for s in source_flags:
val = eval(s.get_contents())
name, compound, desc = val
flagsList.append(val)
flagsMap[name] = bool(compound)
for name, compound, desc in flagsList:
for flag in compound:
if flag not in flagsMap:
raise AttributeError, "Trace flag %s not found" % flag
if flagsMap[flag]:
raise AttributeError, \
"Compound flag can't point to another compound flag"
#
# Handle debug flags
#
def makeDebugFlagCC(target, source, env):
assert(len(target) == 1 and len(source) == 1)
flagsList.sort()
return flagsList
val = eval(source[0].get_contents())
name, compound, desc = val
compound = list(sorted(compound))
# Generate traceflags.py
def traceFlagsPy(target, source, env):
assert(len(target) == 1)
code = code_formatter()
allFlags = getFlags(source)
code('basic = [')
code.indent()
for flag, compound, desc in allFlags:
if not compound:
code("'$flag',")
code(']')
code.dedent()
code()
code('compound = [')
code.indent()
code("'All',")
for flag, compound, desc in allFlags:
if compound:
code("'$flag',")
code("]")
code.dedent()
code()
code("all = frozenset(basic + compound)")
code()
code('compoundMap = {')
code.indent()
all = tuple([flag for flag,compound,desc in allFlags if not compound])
code("'All' : $all,")
for flag, compound, desc in allFlags:
if compound:
code("'$flag' : $compound,")
code('}')
code.dedent()
code()
code('descriptions = {')
code.indent()
code("'All' : 'All flags',")
for flag, compound, desc in allFlags:
code("'$flag' : '$desc',")
code("}")
code.dedent()
code.write(str(target[0]))
def traceFlagsCC(target, source, env):
assert(len(target) == 1)
allFlags = getFlags(source)
code = code_formatter()
# file header
@ -705,75 +642,39 @@ def traceFlagsCC(target, source, env):
* DO NOT EDIT THIS FILE! Automatically generated
*/
#include "base/traceflags.hh"
using namespace Trace;
const char *Trace::flagStrings[] =
{''')
code.indent()
# The string array is used by SimpleEnumParam to map the strings
# provided by the user to enum values.
for flag, compound, desc in allFlags:
if not compound:
code('"$flag",')
code('"All",')
for flag, compound, desc in allFlags:
if compound:
code('"$flag",')
code.dedent()
code('''\
};
const int Trace::numFlagStrings = ${{len(allFlags) + 1}};
#include "base/debug.hh"
''')
# Now define the individual compound flag arrays. There is an array
# for each compound flag listing the component base flags.
all = tuple([flag for flag,compound,desc in allFlags if not compound])
code('static const Flags AllMap[] = {')
code.indent()
for flag, compound, desc in allFlags:
if not compound:
code('$flag,')
code.dedent()
code('};')
for flag in compound:
code('#include "debug/$flag.hh"')
code()
code('namespace Debug {')
code()
for flag, compound, desc in allFlags:
if not compound:
continue
code('static const Flags ${flag}Map[] = {')
if not compound:
code('SimpleFlag $name("$name", "$desc");')
else:
code('CompoundFlag $name("$name", "$desc",')
code.indent()
for flag in compound:
code('$flag,')
code('(Flags)-1')
last = len(compound) - 1
for i,flag in enumerate(compound):
if i != last:
code('$flag,')
else:
code('$flag);')
code.dedent()
code('};')
code()
# Finally the compoundFlags[] array maps the compound flags
# to their individual arrays/
code('const Flags *Trace::compoundFlags[] = {')
code.indent()
code('AllMap,')
for flag, compound, desc in allFlags:
if compound:
code('${flag}Map,')
# file trailer
code.dedent()
code('};')
code()
code('} // namespace Debug')
code.write(str(target[0]))
def traceFlagsHH(target, source, env):
assert(len(target) == 1)
def makeDebugFlagHH(target, source, env):
assert(len(target) == 1 and len(source) == 1)
val = eval(source[0].get_contents())
name, compound, desc = val
allFlags = getFlags(source)
code = code_formatter()
# file header boilerplate
@ -781,76 +682,43 @@ def traceFlagsHH(target, source, env):
/*
* DO NOT EDIT THIS FILE!
*
* Automatically generated from traceflags.py
* Automatically generated by SCons
*/
#ifndef __BASE_TRACE_FLAGS_HH__
#define __BASE_TRACE_FLAGS_HH__
#ifndef __DEBUG_${name}_HH__
#define __DEBUG_${name}_HH__
namespace Trace {
namespace Debug {
''')
enum Flags {''')
if compound:
code('class CompoundFlag;')
code('class SimpleFlag;')
# Generate the enum. Base flags come first, then compound flags.
idx = 0
code.indent()
for flag, compound, desc in allFlags:
if not compound:
code('$flag = $idx,')
idx += 1
if compound:
code('extern CompoundFlag $name;')
for flag in compound:
code('extern SimpleFlag $flag;')
else:
code('extern SimpleFlag $name;')
numBaseFlags = idx
code('NumFlags = $idx,')
code.dedent()
code()
# put a comment in here to separate base from compound flags
code('''
// The remaining enum values are *not* valid indices for Trace::flags.
// They are "compound" flags, which correspond to sets of base
// flags, and are used by changeFlag.''')
}
code.indent()
code('All = $idx,')
idx += 1
for flag, compound, desc in allFlags:
if compound:
code('$flag = $idx,')
idx += 1
numCompoundFlags = idx - numBaseFlags
code('NumCompoundFlags = $numCompoundFlags')
code.dedent()
# trailer boilerplate
code('''\
}; // enum Flags
// Array of strings for SimpleEnumParam
extern const char *flagStrings[];
extern const int numFlagStrings;
// Array of arraay pointers: for each compound flag, gives the list of
// base flags to set. Inidividual flag arrays are terminated by -1.
extern const Flags *compoundFlags[];
} // namespace Trace
#endif // __BASE_TRACE_FLAGS_HH__
#endif // __DEBUG_${name}_HH__
''')
code.write(str(target[0]))
flags = map(Value, trace_flags.values())
env.Command('base/traceflags.py', flags,
MakeAction(traceFlagsPy, Transform("TRACING", 0)))
PySource('m5', 'base/traceflags.py')
for name,flag in sorted(debug_flags.iteritems()):
n, compound, desc = flag
assert n == name
env.Command('base/traceflags.hh', flags,
MakeAction(traceFlagsHH, Transform("TRACING", 0)))
env.Command('base/traceflags.cc', flags,
MakeAction(traceFlagsCC, Transform("TRACING", 0)))
Source('base/traceflags.cc')
env.Command('debug/%s.hh' % name, Value(flag),
MakeAction(makeDebugFlagHH, Transform("TRACING", 0)))
env.Command('debug/%s.cc' % name, Value(flag),
MakeAction(makeDebugFlagCC, Transform("TRACING", 0)))
Source('debug/%s.cc' % name)
# Embed python files. All .py files that have been indicated by a
# PySource() call in a SConscript need to be embedded into the M5

View file

@ -37,6 +37,8 @@
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Flow.hh"
#include "debug/Interrupt.hh"
#include "params/AlphaInterrupts.hh"
#include "sim/sim_object.hh"

View file

@ -38,6 +38,7 @@
#include "arch/alpha/osfpal.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Context.hh"
#include "kern/tru64/tru64_syscalls.hh"
#include "sim/system.hh"

View file

@ -34,6 +34,7 @@
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
#include "sim/syscall_emul.hh"

View file

@ -48,6 +48,7 @@
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"

View file

@ -35,6 +35,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"

View file

@ -136,6 +136,8 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/system.hh"

View file

@ -33,6 +33,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;

View file

@ -37,6 +37,7 @@
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "debug/Loader.hh"
#include "mem/physical.hh"
#include "mem/vport.hh"
#include "params/AlphaSystem.hh"

View file

@ -40,6 +40,7 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
using namespace std;

View file

@ -37,6 +37,7 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "mem/vport.hh"
using namespace std;

View file

@ -46,6 +46,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
namespace ArmISA
{

View file

@ -39,6 +39,8 @@
*/
#include "arch/arm/isa.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"

View file

@ -46,6 +46,7 @@
#include "arch/arm/registers.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
#include "debug/Checkpoint.hh"
class ThreadContext;
class Checkpoint;

View file

@ -87,6 +87,7 @@ output exec {{
#endif
#include "base/cp_annotate.hh"
#include "debug/Arm.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"

View file

@ -44,6 +44,7 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecRegDelta.hh"
#include "params/ArmNativeTrace.hh"
#include "sim/byteswap.hh"

View file

@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Predecoder.hh"
namespace ArmISA
{

View file

@ -48,6 +48,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/byteswap.hh"

View file

@ -151,6 +151,8 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"

View file

@ -33,6 +33,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;
namespace ArmISA

View file

@ -53,6 +53,9 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Checkpoint.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "mem/page_table.hh"
#include "params/ArmTLB.hh"
#include "sim/process.hh"

View file

@ -48,6 +48,7 @@
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Predecoder.hh"
namespace ArmISA
{

View file

@ -36,6 +36,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#if !FULL_SYSTEM
#include "mem/page_table.hh"

View file

@ -35,6 +35,7 @@
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
namespace MipsISA
{

View file

@ -82,6 +82,7 @@ output exec {{
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/MipsPRA.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"

View file

@ -35,6 +35,7 @@
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "kern/linux/linux.hh"
#include "sim/eventq.hh"
#include "sim/process.hh"

View file

@ -40,6 +40,7 @@
#include "arch/registers.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/LLSC.hh"
#include "mem/request.hh"
namespace MipsISA

View file

@ -36,6 +36,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#include "sim/process_impl.hh"

View file

@ -33,6 +33,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;

View file

@ -43,6 +43,8 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/MipsTLB.hh"
#include "sim/process.hh"

View file

@ -37,6 +37,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"

View file

@ -37,6 +37,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;
class StackTrace;

View file

@ -46,6 +46,8 @@
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Power.hh"
#include "debug/TLB.hh"
#include "mem/page_table.hh"
#include "params/PowerTLB.hh"
#include "sim/process.hh"

View file

@ -36,6 +36,7 @@
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "params/SparcInterrupts.hh"
#include "sim/sim_object.hh"

View file

@ -35,6 +35,8 @@
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MiscRegs.hh"
#include "debug/Timer.hh"
namespace SparcISA
{

View file

@ -74,6 +74,7 @@ output exec {{
#include "base/bigint.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/sim_exit.hh"

View file

@ -39,6 +39,7 @@
#include "base/loader/object_file.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"

View file

@ -130,6 +130,7 @@
#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBRead.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/port.hh"

View file

@ -35,6 +35,7 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;
namespace SparcISA

View file

@ -38,6 +38,8 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/IPR.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/system.hh"

View file

@ -33,6 +33,8 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Quiesce.hh"
#include "debug/Timer.hh"
#include "sim/system.hh"
using namespace SparcISA;

View file

@ -36,6 +36,7 @@
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "mem/vport.hh"
using namespace std;

View file

@ -45,12 +45,14 @@
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
#include "arch/x86/isa_traits.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
#else
#include "arch/x86/tlb.hh"
#include "debug/Faults.hh"
#endif
namespace X86ISA

View file

@ -42,6 +42,7 @@
#include "arch/x86/insts/microregop.hh"
#include "arch/x86/regs/misc.hh"
#include "base/condcodes.hh"
#include "debug/X86.hh"
namespace X86ISA
{

View file

@ -42,6 +42,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/X86.hh"
namespace X86ISA
{

View file

@ -41,6 +41,7 @@
#include "arch/x86/interrupts.hh"
#include "arch/x86/intmessage.hh"
#include "cpu/base.hh"
#include "debug/LocalApic.hh"
#include "dev/x86/i82094aa.hh"
#include "dev/x86/pc.hh"
#include "dev/x86/south_bridge.hh"

View file

@ -118,6 +118,7 @@ output exec {{
#include "base/condcodes.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/X86.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"

View file

@ -33,6 +33,7 @@
#include "arch/x86/isa_traits.hh"
#include "arch/x86/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecRegDelta.hh"
#include "params/X86NativeTrace.hh"
#include "sim/byteswap.hh"

View file

@ -44,6 +44,7 @@
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/PageTableWalker.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/system.hh"

View file

@ -43,6 +43,7 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "debug/Predecoder.hh"
namespace X86ISA
{

View file

@ -48,6 +48,7 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Predecoder.hh"
class ThreadContext;

View file

@ -51,6 +51,7 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/process_impl.hh"

View file

@ -33,6 +33,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/Stack.hh"
class ThreadContext;
namespace X86ISA

View file

@ -50,6 +50,7 @@
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"

View file

@ -45,6 +45,7 @@
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "debug/VtoPhys.hh"
#include "sim/fault_fwd.hh"
using namespace std;

View file

@ -31,12 +31,24 @@
#include <sys/types.h>
#include <unistd.h>
#include <algorithm>
#include <csignal>
#include <map>
#include <vector>
#include "base/cprintf.hh"
#include "base/debug.hh"
#include "base/misc.hh"
using namespace std;
namespace Debug {
//
// This function will cause the process to signal itself with a
// SIGTRAP which is ignored if not in gdb, but will cause the debugger
// to break if in gdb.
//
void
breakpoint()
{
@ -47,4 +59,127 @@ breakpoint()
#endif
}
//
// Flags for debugging purposes. Primarily for trace.hh
//
typedef std::map<string, Flag *> FlagsMap;
int allFlagsVersion = 0;
FlagsMap &
allFlags()
{
static FlagsMap flags;
return flags;
}
Flag *
findFlag(const std::string &name)
{
FlagsMap::iterator i = allFlags().find(name);
if (i == allFlags().end())
return NULL;
return i->second;
}
Flag::Flag(const char *name, const char *desc)
: _name(name), _desc(desc)
{
pair<FlagsMap::iterator, bool> result =
allFlags().insert(make_pair(name, this));
if (!result.second)
panic("Flag %s already defined!", name);
++allFlagsVersion;
}
Flag::~Flag()
{
// should find and remove flag.
}
void
CompoundFlag::enable()
{
SimpleFlag::enable();
for_each(flags.begin(), flags.end(), mem_fun(&Flag::enable));
}
void
CompoundFlag::disable()
{
SimpleFlag::disable();
for_each(flags.begin(), flags.end(), mem_fun(&Flag::disable));
}
struct AllFlags : public Flag
{
AllFlags()
: Flag("All", "All Flags")
{}
void
enable()
{
FlagsMap::iterator i = allFlags().begin();
FlagsMap::iterator end = allFlags().end();
for (; i != end; ++i)
if (i->second != this)
i->second->enable();
}
void
disable()
{
FlagsMap::iterator i = allFlags().begin();
FlagsMap::iterator end = allFlags().end();
for (; i != end; ++i)
if (i->second != this)
i->second->enable();
}
};
AllFlags theAllFlags;
Flag *const All = &theAllFlags;
bool
changeFlag(const char *s, bool value)
{
Flag *f = findFlag(s);
if (!f)
return false;
if (value)
f->enable();
else
f->disable();
return true;
}
} // namespace Debug
// add a set of functions that can easily be invoked from gdb
void
setDebugFlag(const char *string)
{
Debug::changeFlag(string, true);
}
void
clearDebugFlag(const char *string)
{
Debug::changeFlag(string, false);
}
void
dumpDebugFlags()
{
using namespace Debug;
FlagsMap::iterator i = allFlags().begin();
FlagsMap::iterator end = allFlags().end();
for (; i != end; ++i) {
SimpleFlag *f = dynamic_cast<SimpleFlag *>(i->second);
if (f && f->status())
cprintf("%s\n", f->name());
}
}

View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2010 The Hewlett-Packard Development Company
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -31,10 +32,84 @@
#ifndef __BASE_DEBUG_HH__
#define __BASE_DEBUG_HH__
#include <string>
#include <vector>
namespace Debug {
void breakpoint();
class Flag
{
protected:
const char *_name;
const char *_desc;
public:
Flag(const char *name, const char *desc);
virtual ~Flag();
std::string name() const { return _name; }
std::string desc() const { return _desc; }
virtual void enable() = 0;
virtual void disable() = 0;
};
class SimpleFlag : public Flag
{
protected:
bool _status;
public:
SimpleFlag(const char *name, const char *desc)
: Flag(name, desc)
{ }
bool status() const { return _status; }
operator bool() const { return _status; }
bool operator!() const { return !_status; }
void enable() { _status = true; }
void disable() { _status = false; }
};
class CompoundFlag : public SimpleFlag
{
protected:
std::vector<Flag *> flags;
public:
CompoundFlag(const char *name, const char *desc,
Flag &f00 = *(Flag *)0, Flag &f01 = *(Flag *)0,
Flag &f02 = *(Flag *)0, Flag &f03 = *(Flag *)0,
Flag &f04 = *(Flag *)0, Flag &f05 = *(Flag *)0,
Flag &f06 = *(Flag *)0, Flag &f07 = *(Flag *)0,
Flag &f08 = *(Flag *)0, Flag &f09 = *(Flag *)0,
Flag &f10 = *(Flag *)0, Flag &f11 = *(Flag *)0,
Flag &f12 = *(Flag *)0, Flag &f13 = *(Flag *)0,
Flag &f14 = *(Flag *)0, Flag &f15 = *(Flag *)0,
Flag &f16 = *(Flag *)0, Flag &f17 = *(Flag *)0,
Flag &f18 = *(Flag *)0, Flag &f19 = *(Flag *)0)
: SimpleFlag(name, desc)
{
addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03); addFlag(f04);
addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08); addFlag(f09);
addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13); addFlag(f14);
addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18); addFlag(f19);
}
void
addFlag(Flag &f)
{
if (&f != NULL)
flags.push_back(&f);
}
void enable();
void disable();
};
} // namespace Debug
#endif // __BASE_DEBUG_HH__

View file

@ -34,6 +34,7 @@
#include "base/loader/exec_aout.h"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "debug/Loader.hh"
using namespace std;

View file

@ -35,6 +35,7 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Loader.hh"
// Only alpha will be able to load ecoff files for now.
// base/types.hh and ecoff_machdep.h must be before the other .h files

View file

@ -37,6 +37,7 @@
#include "base/bitfield.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/Loader.hh"
#include "sim/byteswap.hh"
#include "gelf.h"

View file

@ -31,6 +31,7 @@
#include "base/loader/raw_object.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "debug/Loader.hh"
ObjectFile *
RawObject::tryFile(const std::string &fname, int fd, size_t len, uint8_t *data)

View file

@ -32,6 +32,7 @@
#include "base/mysql.hh"
#include "base/trace.hh"
#include "debug/SQL.hh"
using namespace std;

View file

@ -136,11 +136,13 @@
#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBAll.hh"
#include "mem/port.hh"
#include "mem/translating_port.hh"
#include "sim/system.hh"
using namespace std;
using namespace Debug;
using namespace TheISA;
#ifndef NDEBUG

View file

@ -32,9 +32,7 @@
#include <cctype>
#include <fstream>
#include <iostream>
#include <list>
#include <string>
#include <vector>
#include "base/misc.hh"
#include "base/output.hh"
@ -45,8 +43,8 @@
using namespace std;
namespace Trace {
const string DefaultName("global");
FlagVec flags(NumFlags, false);
bool enabled = false;
//
@ -149,63 +147,4 @@ dump(Tick when, const std::string &name, const void *d, int len)
}
}
bool
changeFlag(const char *s, bool value)
{
using namespace Trace;
std::string str(s);
for (int i = 0; i < numFlagStrings; ++i) {
if (str != flagStrings[i])
continue;
if (i < NumFlags) {
flags[i] = value;
} else {
i -= NumFlags;
const Flags *flagVec = compoundFlags[i];
for (int j = 0; flagVec[j] != -1; ++j) {
if (flagVec[j] < NumFlags)
flags[flagVec[j]] = value;
}
}
return true;
}
// the flag was not found.
return false;
}
void
dumpStatus()
{
using namespace Trace;
for (int i = 0; i < numFlagStrings; ++i) {
if (flags[i])
cprintf("%s\n", flagStrings[i]);
}
}
} // namespace Trace
// add a set of functions that can easily be invoked from gdb
void
setTraceFlag(const char *string)
{
Trace::changeFlag(string, true);
}
void
clearTraceFlag(const char *string)
{
Trace::changeFlag(string, false);
}
void
dumpTraceStatus()
{
Trace::dumpStatus();
}

View file

@ -33,23 +33,22 @@
#define __BASE_TRACE_HH__
#include <string>
#include <vector>
#include "base/cprintf.hh"
#include "base/debug.hh"
#include "base/match.hh"
#include "base/traceflags.hh"
#include "base/types.hh"
#include "sim/core.hh"
namespace Trace {
using Debug::SimpleFlag;
using Debug::CompoundFlag;
std::ostream &output();
void setOutput(const std::string &filename);
extern bool enabled;
typedef std::vector<bool> FlagVec;
extern FlagVec flags;
inline bool IsOn(int t) { return flags[t]; }
bool changeFlag(const char *str, bool value);
void dumpStatus();
@ -85,25 +84,28 @@ inline const std::string &name() { return Trace::DefaultName; }
#if TRACING_ON
#define DTRACE(x) (Trace::IsOn(Trace::x) && Trace::enabled)
#define DTRACE(x) ((Debug::x) && Trace::enabled)
#define DDUMP(x, data, count) do { \
using namespace Debug; \
if (DTRACE(x)) \
Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTF(x, ...) do { \
using namespace Debug; \
if (DTRACE(x)) \
Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
#define DPRINTFS(x,s, ...) do { \
#define DPRINTFS(x, s, ...) do { \
using namespace Debug; \
if (DTRACE(x)) \
Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
} while (0)
#define DPRINTFR(x, ...) do { \
using namespace Debug; \
if (DTRACE(x)) \
Trace::dprintf((Tick)-1, std::string(), __VA_ARGS__); \
} while (0)

View file

@ -55,6 +55,7 @@
#include "base/misc.hh"
#include "base/socket.hh"
#include "base/trace.hh"
#include "debug/VNC.hh"
#include "sim/byteswap.hh"
using namespace std;

View file

@ -173,6 +173,10 @@ TraceFlag('IntrControl')
TraceFlag('PCEvent')
TraceFlag('Quiesce')
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
'ExecResult', 'ExecSpeculative', 'ExecSymbol', 'ExecThread',
'ExecTicks', 'ExecMicro', 'ExecMacro' ])
CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread',
'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecFaulting' ])
CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',

View file

@ -32,6 +32,7 @@
#include "cpu/activity.hh"
#include "cpu/timebuf.hh"
#include "debug/Activity.hh"
using namespace std;

View file

@ -45,6 +45,7 @@
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "debug/SyscallVerbose.hh"
#include "params/BaseCPU.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"

View file

@ -50,6 +50,8 @@
#include "config/the_isa.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "debug/DynInst.hh"
#include "debug/IQ.hh"
#include "mem/request.hh"
#include "sim/faults.hh"

View file

@ -41,6 +41,7 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecAll.hh"
#include "enums/OpClass.hh"
using namespace std;
@ -59,22 +60,21 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
{
ostream &outs = Trace::output();
if (IsOn(ExecTicks))
if (Debug::ExecTicks)
dumpTicks(outs);
outs << thread->getCpuPtr()->name() << " ";
if (IsOn(ExecSpeculative))
if (Debug::ExecSpeculative)
outs << (misspeculating ? "-" : "+") << " ";
if (IsOn(ExecThread))
if (Debug::ExecThread)
outs << "T" << thread->threadId() << " : ";
std::string sym_str;
Addr sym_addr;
Addr cur_pc = pc.instAddr();
if (debugSymbolTable
&& IsOn(ExecSymbol)
if (debugSymbolTable && Debug::ExecSymbol
#if FULL_SYSTEM
&& !inUserMode(thread)
#endif
@ -104,25 +104,25 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
if (ran) {
outs << " : ";
if (IsOn(ExecOpClass)) {
if (Debug::ExecOpClass) {
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
if (IsOn(ExecResult) && predicate == false) {
if (Debug::ExecResult && predicate == false) {
outs << "Predicated False";
}
if (IsOn(ExecResult) && data_status != DataInvalid) {
if (Debug::ExecResult && data_status != DataInvalid) {
ccprintf(outs, " D=%#018x", data.as_int);
}
if (IsOn(ExecEffAddr) && addr_valid)
if (Debug::ExecEffAddr && addr_valid)
outs << " A=0x" << hex << addr;
if (IsOn(ExecFetchSeq) && fetch_seq_valid)
if (Debug::ExecFetchSeq && fetch_seq_valid)
outs << " FetchSeq=" << dec << fetch_seq;
if (IsOn(ExecCPSeq) && cp_seq_valid)
if (Debug::ExecCPSeq && cp_seq_valid)
outs << " CPSeq=" << dec << cp_seq;
}
@ -143,14 +143,14 @@ Trace::ExeTracerRecord::dump()
* finishes. Macroops then behave like regular instructions and don't
* complete/print when they fault.
*/
if (IsOn(ExecMacro) && staticInst->isMicroop() &&
((IsOn(ExecMicro) &&
macroStaticInst && staticInst->isFirstMicroop()) ||
(!IsOn(ExecMicro) &&
if (Debug::ExecMacro && staticInst->isMicroop() &&
((Debug::ExecMicro &&
macroStaticInst && staticInst->isFirstMicroop()) ||
(!Debug::ExecMicro &&
macroStaticInst && staticInst->isLastMicroop()))) {
traceInst(macroStaticInst, false);
}
if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
if (Debug::ExecMicro || !staticInst->isMicroop()) {
traceInst(staticInst, true);
}
}

View file

@ -36,6 +36,8 @@
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
#include "debug/ExecSpeculative.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
@ -72,13 +74,13 @@ class ExeTracer : public InstTracer
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
if (!IsOn(ExecEnable))
if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
if (!IsOn(ExecSpeculative) && tc->misspeculating())
if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new ExeTracerRecord(when, tc,

View file

@ -47,6 +47,10 @@
#include "cpu/exetrace.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "debug/Activity.hh"
#include "debug/InOrderCPU.hh"
#include "debug/RefCount.hh"
#include "debug/SkedCache.hh"
#include "mem/translating_port.hh"
#include "params/InOrderCPU.hh"
#include "sim/process.hh"

View file

@ -34,6 +34,7 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/first_stage.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/InOrderStage.hh"
#include "params/InOrderTrace.hh"
using namespace std;

View file

@ -41,6 +41,7 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "debug/InOrderDynInst.hh"
#include "mem/request.hh"
using namespace std;

View file

@ -57,6 +57,7 @@
#include "cpu/op_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/InOrderDynInst.hh"
#include "mem/packet.hh"
#include "sim/system.hh"

View file

@ -37,6 +37,7 @@
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
#include "params/InOrderTrace.hh"
using namespace std;
@ -64,7 +65,7 @@ InOrderTraceRecord *
InOrderTrace::getInstRecord(unsigned num_stages, bool stage_tracing,
ThreadContext *tc)
{
if (!IsOn(ExecEnable))
if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)

View file

@ -34,6 +34,11 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/Activity.hh"
#include "debug/InOrderStage.hh"
#include "debug/InOrderStall.hh"
#include "debug/Resource.hh"
#include "debug/ThreadModel.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -35,6 +35,7 @@
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/reg_dep_map.hh"
#include "debug/RegDepMap.hh"
using namespace std;
using namespace TheISA;

View file

@ -35,6 +35,10 @@
#include "base/str.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource.hh"
#include "debug/RefCount.hh"
#include "debug/ResReqCount.hh"
#include "debug/Resource.hh"
using namespace std;
Resource::Resource(string res_name, int res_id, int res_width,

View file

@ -34,6 +34,7 @@
#include "cpu/inorder/resources/resource_list.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -35,6 +35,7 @@
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_sked.hh"
#include "debug/SkedCache.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -30,6 +30,7 @@
*/
#include "cpu/inorder/resources/agen_unit.hh"
#include "debug/InOrderAGEN.hh"
AGENUnit::AGENUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu,

View file

@ -33,9 +33,10 @@
#include "arch/utility.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/inorder/resources/bpred_unit.hh"
#include "debug/InOrderBPred.hh"
#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -31,6 +31,8 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/branch_predictor.hh"
#include "debug/InOrderBPred.hh"
#include "debug/InOrderStage.hh"
using namespace std;
using namespace TheISA;

View file

@ -41,6 +41,14 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/Activity.hh"
#include "debug/AddrDep.hh"
#include "debug/InOrderCachePort.hh"
#include "debug/InOrderStall.hh"
#include "debug/InOrderTLB.hh"
#include "debug/LLSC.hh"
#include "debug/RefCount.hh"
#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;

View file

@ -31,6 +31,9 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/decode_unit.hh"
#include "debug/InOrderDecode.hh"
#include "debug/InOrderStall.hh"
#include "debug/Resource.hh"
using namespace TheISA;
using namespace ThePipeline;

View file

@ -35,6 +35,8 @@
#include "cpu/inorder/resources/execution_unit.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/InOrderExecute.hh"
#include "debug/InOrderStall.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -32,6 +32,8 @@
#include "config/the_isa.hh"
#include "cpu/inorder/resources/fetch_seq_unit.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/InOrderFetchSeq.hh"
#include "debug/InOrderStall.hh"
using namespace std;
using namespace TheISA;

View file

@ -42,6 +42,11 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource_pool.hh"
#include "debug/Activity.hh"
#include "debug/InOrderCachePort.hh"
#include "debug/InOrderStall.hh"
#include "debug/RefCount.hh"
#include "debug/ThreadModel.hh"
#include "mem/request.hh"
using namespace std;

View file

@ -30,6 +30,7 @@
*/
#include "cpu/inorder/resources/graduation_unit.hh"
#include "debug/InOrderGraduation.hh"
using namespace ThePipeline;

View file

@ -37,6 +37,8 @@
#include "cpu/inorder/resources/inst_buffer.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "debug/InOrderInstBuffer.hh"
#include "debug/Resource.hh"
using namespace std;
using namespace TheISA;

View file

@ -36,6 +36,8 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh"
#include "cpu/op_class.hh"
#include "debug/InOrderMDU.hh"
#include "debug/Resource.hh"
using namespace std;
using namespace ThePipeline;

View file

@ -37,6 +37,8 @@
#include "cpu/inorder/resources/use_def.hh"
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "debug/InOrderStall.hh"
#include "debug/InOrderUseDef.hh"
using namespace std;
using namespace TheISA;

View file

@ -33,6 +33,7 @@
#include "config/the_isa.hh"
#include "cpu/inorder/thread_context.hh"
#include "cpu/exetrace.hh"
#include "debug/InOrderCPU.hh"
using namespace TheISA;

View file

@ -35,6 +35,8 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/ExecEnable.hh"
#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
@ -68,13 +70,13 @@ class IntelTrace : public InstTracer
const StaticInstPtr staticInst, TheISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
if (!IsOn(ExecEnable))
if (!Debug::ExecEnable)
return NULL;
if (!Trace::enabled)
return NULL;
if (!IsOn(ExecSpeculative) && tc->misspeculating())
if (!Debug::ExecSpeculative && tc->misspeculating())
return NULL;
return new IntelTraceRecord(when, tc,

View file

@ -36,6 +36,7 @@
#include "cpu/base.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "debug/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;

View file

@ -31,6 +31,7 @@
#include "base/socket.hh"
#include "cpu/nativetrace.hh"
#include "cpu/static_inst.hh"
#include "debug/GDBMisc.hh"
#include "params/NativeTrace.hh"
using namespace std;

View file

@ -34,9 +34,9 @@
#include "arch/types.hh"
#include "arch/utility.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "config/the_isa.hh"
#include "cpu/o3/bpred_unit.hh"
#include "debug/Fetch.hh"
#include "params/DerivO3CPU.hh"
template<class Impl>

View file

@ -54,6 +54,10 @@
#include "cpu/o3/thread_state.hh"
#include "cpu/exetrace.hh"
#include "cpu/timebuf.hh"
#include "debug/Activity.hh"
#include "debug/Commit.hh"
#include "debug/CommitRate.hh"
#include "debug/ExecFaulting.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"

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