ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.
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5 changed files with 35 additions and 0 deletions
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@ -137,6 +137,7 @@ elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode,
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options.machine_type, bm[0],
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bare_metal=options.bare_metal)
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setWorkCountOptions(test_sys, options)
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else:
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fatal("incapable of building non-alpha or non-sparc full system!")
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@ -72,6 +72,8 @@ def format M5ops() {{
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case 0x53: return new M5addsymbol(machInst);
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#endif
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case 0x54: return new M5panic(machInst);
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case 0x5a: return new M5workbegin(machInst);
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case 0x5b: return new M5workend(machInst);
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}
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}
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'''
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@ -313,4 +313,30 @@ let {{
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decoder_output += BasicConstructor.subst(m5panicIop)
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exec_output += PredOpExecute.subst(m5panicIop)
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m5workbeginCode = '''PseudoInst::workbegin(
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xc->tcBase(),
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join32to64(R1, R0),
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join32to64(R3, R2)
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);'''
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m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
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{ "code": m5workbeginCode,
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(m5workbeginIop)
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decoder_output += BasicConstructor.subst(m5workbeginIop)
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exec_output += PredOpExecute.subst(m5workbeginIop)
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m5workendCode = '''PseudoInst::workend(
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xc->tcBase(),
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join32to64(R1, R0),
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join32to64(R3, R2)
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);'''
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m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
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{ "code": m5workendCode,
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"predicate_test": predicateTest },
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["IsNonSpeculative"])
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header_output += BasicDeclare.subst(m5workendIop)
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decoder_output += BasicConstructor.subst(m5workendIop)
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exec_output += PredOpExecute.subst(m5workendIop)
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}};
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@ -53,6 +53,8 @@ void m5_debugbreak(void);
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void m5_switchcpu(void);
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void m5_addsymbol(uint64_t addr, char *symbol);
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void m5_panic(void);
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void m5_work_begin(uint64_t workid, uint64_t threadid);
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void m5_work_end(uint64_t workid, uint64_t threadid);
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// These operations are for critical path annotation
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void m5a_bsm(char *sm, const void *id, int flags);
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@ -84,6 +84,8 @@ func:
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#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
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#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
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#define PANIC INST(m5_op, 0, 0, panic_func)
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#define WORK_BEGIN(r1,r2) INST(m5_op, r1, r2, work_begin_func)
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#define WORK_END(r1,r2) INST(m5_op, r1, r2, work_end_func)
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#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
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#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
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@ -123,6 +125,8 @@ SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
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SIMPLE_OP(m5_switchcpu, SWITCHCPU)
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SIMPLE_OP(m5_addsymbol, ADDSYMBOL(0, 1))
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SIMPLE_OP(m5_panic, PANIC)
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SIMPLE_OP(m5_work_begin, WORK_BEGIN(0,1))
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SIMPLE_OP(m5_work_end, WORK_END(0,1))
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SIMPLE_OP(m5a_bsm, AN_BSM)
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SIMPLE_OP(m5a_esm, AN_ESM)
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