gem5/src/arch
Gabe Black a1ad9e652a Stack: Tidy up some comments, a warning, and make stack extension consistent.
Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
2011-09-09 01:01:43 -07:00
..
alpha Stack: Tidy up some comments, a warning, and make stack extension consistent. 2011-09-09 01:01:43 -07:00
arm ARM: Mark some variables uncacheable until boot all CPUs are enabled. 2011-08-19 15:08:08 -05:00
generic ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
mips ISA parser: Define operand types with a ctype directly. 2011-07-05 16:52:15 -07:00
noisa SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
power ISAs: Streamline some spots where Mem is used in the ISA descriptions. 2011-07-05 16:52:57 -07:00
sparc Stack: Tidy up some comments, a warning, and make stack extension consistent. 2011-09-09 01:01:43 -07:00
x86 Stack: Tidy up some comments, a warning, and make stack extension consistent. 2011-09-09 01:01:43 -07:00
isa_parser.py ISA parser: Don't look for operands in strings. 2011-09-08 03:21:14 -07:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00