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ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.

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readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
This commit is contained in:
Gabe Black 2011-07-02 22:35:04 -07:00
parent 2e7426664a
commit 3a1428365a
11 changed files with 41 additions and 41 deletions
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12
src/arch/arm/isa/templates/mem.isa
View file

@ -209,7 +209,7 @@ def template NeonLoadExecute {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
%(memacc_code)s;
}
@ -280,8 +280,8 @@ def template NeonStoreExecute {{
}
if (fault == NoFault) {
fault = xc->writeBytes(dataPtr, %(size)d, EA,
memAccessFlags, NULL);
fault = xc->writeMem(dataPtr, %(size)d, EA,
memAccessFlags, NULL);
}
if (fault == NoFault) {
@ -413,8 +413,8 @@ def template NeonStoreInitiateAcc {{
}
if (fault == NoFault) {
fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
memAccessFlags, NULL);
fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
memAccessFlags, NULL);
}
} else {
xc->setPredicate(false);
@ -467,7 +467,7 @@ def template NeonLoadInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
}
} else {
xc->setPredicate(false);

4
src/arch/generic/memhelpers.hh
View file

@ -42,7 +42,7 @@ Fault
readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
MemT &mem, unsigned flags)
{
return xc->readBytes(addr, (uint8_t *)&mem, sizeof(MemT), flags);
return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
}
/// Extract the data returned from a timing mode read.
@ -81,7 +81,7 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
traceData->setData(mem);
}
mem = TheISA::htog(mem);
return xc->writeBytes((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
}
/// Write to memory in atomic mode.

4
src/arch/x86/memhelpers.hh
View file

@ -44,7 +44,7 @@ Fault
readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
uint64_t &mem, unsigned dataSize, unsigned flags)
{
return xc->readBytes(addr, (uint8_t *)&mem, dataSize, flags);
return xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
}
static inline uint64_t
@ -99,7 +99,7 @@ writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
traceData->setData(mem);
}
mem = TheISA::htog(mem);
return xc->writeBytes((uint8_t *)&mem, dataSize, addr, flags, res);
return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
}
template <class XC>

14
src/cpu/base_dyn_inst.hh
View file

@ -124,10 +124,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
cpu->demapPage(vaddr, asn);
}
Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@ -841,8 +841,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
template<class Impl>
Fault
BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
{
reqMade = true;
Request *req = NULL;
@ -893,8 +893,8 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
template<class Impl>
Fault
BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {
traceData->setAddr(addr);

6
src/cpu/exec_context.hh
View file

@ -106,10 +106,10 @@ class ExecContext {
/** Returns a pointer to the ThreadContext. */
ThreadContext *tcBase();
Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
#if FULL_SYSTEM
/** Somewhat Alpha-specific function that handles returning from

8
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -559,15 +559,15 @@ InOrderDynInst::deallocateContext(int thread_num)
}
Fault
InOrderDynInst::readBytes(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
InOrderDynInst::readMem(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
{
return cpu->read(this, addr, data, size, flags);
}
Fault
InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
InOrderDynInst::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
return cpu->write(this, data, size, addr, flags, res);
}

6
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -613,10 +613,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
//
////////////////////////////////////////////
Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
/** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
* Access Only valid for memory operations.

8
src/cpu/simple/atomic.cc
View file

@ -299,8 +299,8 @@ AtomicSimpleCPU::suspendContext(int thread_num)
Fault
AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
unsigned size, unsigned flags)
AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
unsigned size, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = &data_read_req;
@ -387,8 +387,8 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
Fault
AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;

6
src/cpu/simple/atomic.hh
View file

@ -131,10 +131,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
/**
* Print state of address in memory system via PrintReq (for

8
src/cpu/simple/timing.cc
View file

@ -432,8 +432,8 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
}
Fault
TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
unsigned size, unsigned flags)
{
Fault fault;
const int asid = 0;
@ -500,8 +500,8 @@ TimingSimpleCPU::handleWritePacket()
}
Fault
TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
uint8_t *newData = new uint8_t[size];
memcpy(newData, data, size);

6
src/cpu/simple/timing.hh
View file

@ -256,10 +256,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
Fault writeBytes(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
void fetch();
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);