gem5/src/arch
Ali Saidi b5160ba2c3 ARM: Generate condition code setting code based on which codes are set.
This change further eliminates cases where condition codes were being read
just so they could be written without change because the instruction in
question was supposed to preserve them. This is done by creating the condition
code code based on the input rather than just doing a simple substitution.
2011-05-13 17:27:02 -05:00
..
alpha Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
arm ARM: Generate condition code setting code based on which codes are set. 2011-05-13 17:27:02 -05:00
generic includes: sort all includes 2011-04-15 10:44:06 -07:00
mips Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
noisa SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
power Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
sparc Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
x86 Trace: Allow printing ASIDs and selectively tracing based on user/kernel code. 2011-05-13 17:27:00 -05:00
isa_parser.py ISA parser: Set up op_src_decl and op_dest_decl for pc operands. 2011-03-24 13:55:16 -04:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript Spelling: Fix the a spelling error by changing mmaped to mmapped. 2011-03-01 23:18:47 -08:00