Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
Move some miscregs into the integer register file so they get renamed.
--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
Protect other pieces of code so that sparc compiles SE again
src/arch/sparc/SConscript:
Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
protect legion code so it doesn't try to compile under se
--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it
configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it
--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
into zower.eecs.umich.edu:/eecshome/m5/newmemmid
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
hand merge
--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
src/arch/SConscript:
add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
src/arch/sparc/process.cc:
MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
Sparc version of this file.
--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
src/arch/sparc/SConscript:
Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
update asi names for how they're listed in the supplement
add asis
add more asi functions
src/arch/sparc/isa_traits.hh:
move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add mmu registers to tlb
get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
first cut at sparc tlb
src/arch/sparc/vtophys.hh:
pagatable nedes to be included here
src/mem/request.hh:
add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
fix incorrect definition of LL
--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
src/arch/sparc/isa/base.isa:
Fix a constant.
src/arch/sparc/isa/decoder.isa:
Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
Use the right constant.
--HG--
extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
--HG--
extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
src/arch/alpha/faults.hh:
Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
Only use tlb.hh in FS
--HG--
extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?
src/arch/sparc/faults.cc:
set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
fix endian issues with condition codes
src/arch/sparc/tlb.hh:
add implemented physical addres constants
src/arch/sparc/utility.hh:
add tlb.hh to utilities
src/base/loader/raw_object.cc:
add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
use memcpy instead of bcopy
src/cpu/exetrace.cc:
clean up printing a bit more
src/cpu/m5legion_interface.h:
add tons to the shared interface
src/dev/ethertap.cc:
s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
hack to make sure htole() works...
--HG--
extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/arch/sparc/faults.hh:
Hand merged.
--HG--
extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
SConstruct:
Put the code to make a switching header directory into a function so they are easy to make.
src/arch/SConscript:
Replace switching header code with the new function call.
src/kern/SConscript:
Created a new switching header directory in kern, and moved the declaration of some source files here.
--HG--
rename : src/kern/kernel_stats.cc => src/kern/base_kernel_stats.cc
rename : src/kern/kernel_stats.hh => src/kern/base_kernel_stats.hh
extra : convert_revision : 98f5320a5ade567c3e4f67fef123dfb0c5122545
SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
src/sim/faults.cc:
Fix fault message.
src/kern/tru64/tru64.hh:
Add DPRINTF to see where new thread stacks are allocated.
src/arch/alpha/faults.cc:
Add print statement so we know what the faulting address is in SE mode.
--HG--
extra : convert_revision : 6eb2b513c339496a0d013b7e914953a0a066c12d
src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
src/arch/sparc/isa/base.isa:
src/arch/sparc/isa/formats/micro.isa:
Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions.
src/arch/sparc/utility.hh:
Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used.
--HG--
extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.
--HG--
extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
src/arch/sparc/isa/bitfields.isa:
Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
Encoded the ASI into the ExtMachInst
--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision : c61f4bf05517172edd2c83368fd10bb0f0678029
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
src/cpu/ozone/cpu_impl.hh:
Hand merged
--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac
src/arch/alpha/isa_traits.hh:
This got changed to the wrong version by accident.
src/cpu/base.cc:
Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
Switch out updates from the version of m5 I have. Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
Use proper method to get flags. Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
Support profiling.
src/cpu/ozone/cpu.hh:
Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
Get flags correctly.
src/cpu/ozone/thread_state.hh:
Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
src/arch/sparc/SConscript:
Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface.
src/arch/sparc/asi.hh:
Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions.
src/arch/sparc/asi.cc:
Implementation of some ASI utility functions.
--HG--
extra : convert_revision : 8021007027b13e91cc66908029470da49a8ca11f
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
Added in the filename parameter which is provided for the user space linker.
Fix the ordering and alignment of stack elements.
Made mmap start with the address it has been seen starting with "in the wild"
--HG--
extra : convert_revision : 8734753145f59a6cb433e4f92f43cb28a44b56d4
1. alignaddr wrote it's address to a floating point register rather than a gpr.
2. sethi was sign extending it's immediate value.
--HG--
extra : convert_revision : 9aa30a6485bc4cba916367973b986d439b7c7588
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
src/arch/sparc/process.cc:
All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.
--HG--
extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
Options to turn on output after every instruction. They are commented out.
--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
src/arch/sparc/isa/operands.isa:
Added the GSR register as a control register
--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : be1e5dcb1c5025db8526e628c2060b1790d38227
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.
--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
update scripts acordingly
configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay
--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
src/arch/alpha/regfile.hh:
Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
Move common serialization code into ThreadState.
--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
src/arch/mips/isa/formats/fp.isa:
Adjust for newmem
src/cpu/cpu_models.py:
Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
Add O3DynInst
src/cpu/o3/dyn_inst.hh:
Use to get ISA-specific O3DynInst
--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
src/cpu/simple/base.cc:
add syscall emulation page table fault so we can allocate more stack pages
FaultBase::invoke will do this, we don't need to do it here
src/sim/faults.hh:
I have no idea why this #if was there... gone
src/sim/process.cc:
make stack_min actually be the current minimum
--HG--
extra : convert_revision : 9786b39f2747b94654a5d77c74243cd20503add4
SConstruct:
Remove check for Checker from this SConstruct
src/arch/SConscript:
Specific check if CheckerCPU is being used. Not the cleanest, but works for now.
src/cpu/SConscript:
Code to handle using the CheckerCPU a little better. Allows -c to be used normally.
--HG--
extra : convert_revision : 0a82f16db0f38e5ce114d08368477bd211331fa3
src/arch/alpha/isa/decoder.isa:
Surround Erik's old copy code with #ifdefs. This way the copy functions don't need to be included in the ExecContext (until somebody decides to add them back in).
--HG--
extra : convert_revision : 508ca387757a32bb616e5b4b07af17787a76970e
Fix some author stuff and copyright dates
Take out full system code
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
copyright info
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/control.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/process.cc:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/stacktrace.hh:
copyright 2006
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
copyright 2006
take out full system
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/regfile.hh:
copyright 2006
use FloatRegVal
src/arch/mips/regfile/int_regfile.hh:
copyright 2006
move HI/LO to types.hh
src/arch/mips/types.hh:
copyright 2006
typedef FloatRegVal
--HG--
extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
src/arch/mips/isa/formats/trap.isa:
Take out fix that tried to fix trap
instruction disassembly. It forces bad
compile ..
configs/test/test.py:
add 'cycle' to exit message
--HG--
extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 9b5b1419e8e22bce16ed97fc02c2008ca0181afc
src/arch/alpha/ev5.cc:
Fix memory leak. The faults are refcounted, but that only works if you're actually assigning them to a RefCountingPtr.
--HG--
extra : convert_revision : 9a57963eb5d5d86c16023bfedb0fb5ccdbe7efaa
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 7ac7b9c9288e4940899766cd2dd55ef793d48d4d
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 18a381fa230f2ef6d027359ffd619e3ae75cd446
Also delete no-longer-needed SPARC test.py files (should
have gone with my last chnageset where LiveProcess
became ISA-independent).
src/arch/SConscript:
Mistakenly committed hard-coded python binary name.
Should use same python to run isa_parser that was
used to run scons.
--HG--
extra : convert_revision : a3acd5496f3b930d57bb59ae164b8a4a8065bbf8
into ewok.(none):/home/gblack/m5/newmem
src/arch/sparc/regfile.hh:
Hand Merge
--HG--
extra : convert_revision : c47202689202069892524a7d71962082469996ee
bcak to main LiveProcess, then automatically select
ISA based on object file type. Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().
configs/test/test.py:
Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
Move create() from arch-specific files back to
main LiveProcess, then automatically select ISA
based on object file type.
--HG--
extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
- change include from exec_context.hh -> threadcontext.hh
- g++ 4.0.3 complaint about broken code (which it was).
- bad merge thread_context -> exec_context
src/arch/sparc/isa/includes.isa:
Fix SPARC_SE for exec_context->thread_context switch
src/arch/sparc/regfile.hh:
fix g++ 4.0.3 complaint about broken code (which it was).
src/cpu/thread_context.hh:
fix bad merge
--HG--
extra : convert_revision : f5bab822d5c25177756e9890e143b0ad8d704201
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : b73eeb1f73a5886a008919acd9e1971a79fd6bfb
src/arch/mips/isa/decoder.isa:
div,divu,ext,seb,seh, fp conditonal moves, fp indexed memory...
src/arch/mips/isa/formats/mem.isa:
MemoryNoDisp class .. use sext<> function instead of doing it manually
src/arch/mips/regfile/float_regfile.hh:
use bits function
--HG--
extra : convert_revision : cbbda9499185b91bdb2a6198fe1b961be04f9265
src/arch/mips/isa/formats/mt.isa:
change copyright to 2006
src/cpu/simple/base.cc:
Only DPRINT NNPC if we are not using ALPHA
src/cpu/static_inst.hh:
Take Out MIPS Specific functions ...
--HG--
extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64
Minor fixes to ALPHA_FS and SPARC_SE.
SPARC_SE still does not compile... looks like there
are unresolved issues with ExecContext -> ThreadContext
rename/reorg.
configs/test/fs.py:
Port to new script interface/model.
configs/test/test.py:
Add support for running MIPS test(s) too via
command-line option.
src/arch/alpha/ev5.cc:
Fix include file.
src/arch/sparc/regfile.hh:
Make Bit64 a ULL constant to avoid compiler error.
--HG--
extra : convert_revision : c46c179758271c4f00171faaa579915846bf4624
into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
Hand merge.
--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf
User script now invokes initialization and
simulation loop after building configuration.
These functions are exported from C++ to Python
using SWIG.
SConstruct:
Set up SWIG builder & scanner.
Set up symlinking of source files into build directory
(by not disabling the default behavior).
configs/test/test.py:
Rewrite to use new script-driven interface.
Include a sample option.
src/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
Add SWIG-generated main_wrap.cc to source list.
src/arch/SConscript:
Set up symlinking of source files into build directory
(by not disabling the default behavior).
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/trace/opt_cpu.cc:
src/cpu/trace/trace_cpu.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
src/sim/serialize.cc:
src/sim/syscall_emul.cc:
SimExit() is now exitSimLoop().
src/cpu/base.cc:
SimExitEvent is now SimLoopExitEvent
src/python/SConscript:
Add SWIG build command for main.i.
Use python/m5 in build dir as source for zip archive...
easy now with file duplication enabled.
src/python/m5/__init__.py:
- Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
- Get rid of argument parsing code; just provide default
option descriptors for user script to call optparse with.
- Don't clutter m5 namespace by sucking in all of m5.config
and m5.objects.
- Move instantiate() function here from config.py.
src/python/m5/config.py:
- Move instantiate() function to __init__.py.
- Param.Foo deferred type lookups must use m5.objects
namespace now (not m5).
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/AlphaFullCPU.py:
src/python/m5/objects/AlphaTLB.py:
src/python/m5/objects/BadDevice.py:
src/python/m5/objects/BaseCPU.py:
src/python/m5/objects/BaseCache.py:
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Bus.py:
src/python/m5/objects/CoherenceProtocol.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/IntrControl.py:
src/python/m5/objects/MemObject.py:
src/python/m5/objects/MemTest.py:
src/python/m5/objects/Pci.py:
src/python/m5/objects/PhysicalMemory.py:
src/python/m5/objects/Platform.py:
src/python/m5/objects/Process.py:
src/python/m5/objects/Repl.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/SimConsole.py:
src/python/m5/objects/SimpleDisk.py:
src/python/m5/objects/System.py:
src/python/m5/objects/Tsunami.py:
src/python/m5/objects/Uart.py:
Fix up imports (m5 namespace no longer includes m5.config).
src/sim/eventq.cc:
src/sim/eventq.hh:
Support for Python-called simulate() function:
- Use IsExitEvent flag to signal events that want
to exit the simulation loop gracefully (instead of
calling exit() to terminate the process).
- Modify interface to hand exit event object back to
caller so it can be inspected for cause.
src/sim/host.hh:
Add MaxTick constant.
src/sim/main.cc:
Move copyright notice back to C++ so we can print
it right away, even for interactive sessions.
Use PYTHONPATH environment var to set module path
(instead of clunky code injection method).
Move main control from here into Python:
- Separate initialization code and simulation loop
into separate functions callable from Python.
- Make Python interpreter invocation more pure (more
like directly invoking interpreter).
Add -i and -p flags (only options on binary itself;
other options processed by Python).
Import readline package when using interactive mode.
src/sim/sim_events.cc:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
src/sim/sim_events.hh:
SimExitEvent is now SimLoopExitEvent, and uses
IsSimExit flag to terminate loop (instead of
exiting simulator process).
Get rid of a few unused constructors.
src/sim/sim_exit.hh:
SimExit() is now exitSimLoop().
Get rid of unused functions.
Add comments.
--HG--
extra : convert_revision : 280b0d671516b25545a6f24cefa64a68319ff3d4
use ThreadContext rename
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/includes.isa:
Use ThreadContext
src/sim/syscall_emul.cc:
fcntl64 function using TC
src/sim/syscall_emul.hh:
Add fcntl64func
--HG--
extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
when we get a virtual port delete it (even though delete does nothing in these cases)
src/arch/alpha/linux/system.cc:
src/arch/alpha/stacktrace.cc:
src/base/remote_gdb.cc:
src/cpu/simple_thread.cc:
when we get a virtual port delete it (even though delete does nothing in this case)
src/mem/port.hh:
src/mem/vport.hh:
add write/read functions that have endian conversions in them
--HG--
extra : convert_revision : 163e05cc038c461f95c92f8ce55422033f9ea513
Following with the previous check-in, ExecContext now refers only to the interface provided to the ISA in order to access CPU state. ThreadContext refers to the interface provided to all objects outside the CPU in order to access thread state. SimpleThread provides all thread state and the interface to access it, and is suitable for simple execution models such as the SimpleCPU.
src/SConscript:
Include thread state file.
src/arch/alpha/ev5.cc:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/thread_context.hh:
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/cpu.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
Rename CPUExecContext to SimpleThread.
src/cpu/base_dyn_inst.hh:
Make thread member variables protected..
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/cpu.hh:
Make various members of ThreadState protected.
src/cpu/o3/alpha_cpu_impl.hh:
Push generation of TranslatingPort into the CPU itself.
Make various members of ThreadState protected.
src/cpu/o3/thread_state.hh:
Pull a lot of common code into the base ThreadState class.
src/cpu/ozone/thread_state.hh:
Rename CPUExecContext to SimpleThread, move a lot of common code into base ThreadState class.
src/cpu/thread_state.hh:
Push a lot of common code into base ThreadState class. This goes along with renaming CPUExecContext to SimpleThread, and making it derive from ThreadState.
src/cpu/simple_thread.cc:
Rename CPUExecContext to SimpleThread, make it derive from ThreadState. This helps push a lot of common code/state into a single class that can be used by all CPUs.
src/cpu/simple_thread.hh:
Rename CPUExecContext to SimpleThread, make it derive from ThreadState.
src/kern/system_events.cc:
Rename cpu_exec_context to thread_context.
src/sim/process.hh:
Remove unused forward declaration.
--HG--
rename : src/cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : src/cpu/cpu_exec_context.hh => src/cpu/simple_thread.hh
extra : convert_revision : 2ed617aa80b64016cb9270f75352607cca032733
src/arch/alpha/regfile.hh:
Define clear functions on the individual reg files.
src/cpu/o3/regfile.hh:
Be sure to clear the misc reg file at startup.
--HG--
extra : convert_revision : 41e640887f0cf15d778c59a4dcd544d46899b527
src/SConscript:
src/arch/sparc/SConscript:
commit a couple of things that I forgot to last time.
--HG--
extra : convert_revision : f140912905b9d36eccc27e35ebcaf2c15611b56b
so the events can be migrated on cpu switches.
Create a new wrapper classe called CpuEventWrapper that works like the old wrapper class but calls the function with the xc
parameter
Use new CpuEventWrapper class from tick compare events on sparc
src/arch/sparc/regfile.hh:
Use new CpuEventWrapper class from tick compare events
src/arch/sparc/ua2005.cc:
Move definition to to a fullsystem only file, since it is.
src/cpu/base.cc:
On switch from one cpu to another CpuEvent::replaceExecContext() needs to be called on all (oldxc,newxc) pairs.
--HG--
extra : convert_revision : eecf4540427cc0ddf75e19a3371cf32b56cba0f5
setup all initialization stuff for UA2005
Setup fullsys build options
Start to make fullsystem compile
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
RCS to BitKeeper
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add support for doing virtual to physical translation using the in-memory
page table
src/arch/sparc/vtophys.cc:
a tad bit of error checking
src/arch/sparc/vtophys.hh:
Cleanup of full-system global variables, primarily in simple_cpu.cc,
to allow multi-system simulations. (Multiple systems not yet yested
though.) Also changes to build sim_smt in full-system mode (though
with only SimpleCPU and not the full timing CPU for now).
Still to do: minimize changes in SimpleCPU code between full-system
and application modes... way too many ifdefs there. Much of the
full-system stuff moved into SimpleCPU should be put in a new System
object to allow multiprocessor simulations.
Converted last remaining modules from C to C++ (mostly in /old).
Renamed all .c files to .cc and a few .h files to .hh.
Renamed architecture-specific files in arch/$TARGET from
$TARGET.{cc,hh,def} to machine.{cc,hh,def} to get rid of pointless
intermediate files in object directory. Split exo-specific
definitions out of machine.hh into machine_exo.h.
Specifics:
In machine.def, null resource descriptors must be FUClamd_NA (and not
NA) to pass C++ type checking.
Enhanced error checking/reporting in bas
src/arch/sparc/vtophys.cc:
- Get rid of my String class, the Vector class, the bitvector class, and my
doubly linked list class.
- Convert tokenize, to_number (formerly StringToNumber) and eat_white to
function on stl strings.
- Change most cases of char * and const char * to string, or const string &
- Some formatting and style nits, but not too many.
src/arch/sparc/vtophys.cc:
simplify
src/arch/sparc/vtophys.cc:
Renamed SimpleCPU::(read|write)_(byte|half|word|qword) to just read &
write, overloaded on the type of the 'data' argument. Merged the
full-system and non-full-system implementations of these eight
original functions into two common template functions.
To support this, also renamed (read|write)[1248] on memory_object and
derivatives to just read & write, again overloaded on the type of the
'data' argument. Many of these functions could now be condensed into
a few template functions (though with a level of indirection so that
the interface can remain virtual). I did not do that though.
src/arch/sparc/vtophys.cc:
First pass at compiling with gcc 3.x. Lots of "std::" in header files,
"using namespace std" in source files. (Note policy of not putting "using"
statements in headers or before includes in sources.)
Still not able to compile with gcc 3.2.
Errors:
- Can't create an ifstream from a file descriptor anymore (breaks IniFile).
- "`class MSHR::MSHRegister' is private" errors in mshr.cc and prefetch_cache.cc:
not clear why since it's in the public part of the class declaration.
- cpu.cc:879: can't match a reference and 0 (specifically "no match for `bool ?
SimObjectParam<PipeTrace*>& : int' operator")
- pipetrace.cc: "invalid conversion from `int' to `std::_Ios_Fmtflags'"
Warnings:
- strstream now deprecated... needs some rewriting in sat_counter.hh
and hybrid_pred.hh (need to get all that code out of the headers anyway)
- trace.hh macro problem: cpp now says 'pasting "::" and "Event" does not
give a valid preprocessing token'
- major "implicit typename" issues in base/sized.hh
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Implement some interval statistics for full system mode.
Create a callpal function that is called when a callpal occurs so it's easier
to manipulate the statics.
Rework the vtophys stuff to make it a bit cleaner.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Get rid of almost all old-style object names. This commit is equivalent
to running the following script on the current head:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' \) -exec perl -pi -e '\
s/\bmemory_object\b(?!\.hh)/FunctionalMemory/g;\
s/\bvirtual_memory\b(?!\.hh)/VirtualMemory/g;\
s/\bmain_memory\b(?!\.hh)/MainMemory/g;\
s/\bphysical_memory\b(?!\.hh)/PhysicalMemory/g;\
s/\bspec_memory\b(?!\.hh)/SpeculativeMemory/g;\
s/\bMemObj\b(?!\.hh)/TimingMemObj/g;\
s/\bmemory_translation\b(?!\.hh)/AddressTranslator/g;\
s/\balpha_tlb\b(?!\.hh)/AlphaTlb/g;\
s/\balpha_itb\b(?!\.hh)/AlphaItb/g;\
s/\balpha_dtb\b(?!\.hh)/AlphaDtb/g;\
s/\bmemory_controller\b(?!\.hh)/MemoryController/g;\
s/\bstorebuffer_t\b(?!\.hh)/StoreBuffer/g;\
s/\bstorebuffer_entry_t\b(?!\.hh)/StoreBufferEntry/g;\
s/\bcreate_vector_t\b(?!\.hh)/CreateVector/g;\
s/\bcv_spec_state\b(?!\.hh)/CreateVecSpecState/g;\
s/\bspec_state_list\b(?!\.hh)/SpecStateList/g;\
s/\bdyn_inst_t\b(?!\.hh)/DynInst/g;' {} \;
src/arch/sparc/vtophys.cc:
since cprintf properly deals with 64-bit types, stop using FMT* as much as
possible
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Change byte_t etc. to C99 standard int8_t etc.
Other than old/host.h, all other changes were produced by this script:
#! /bin/sh
find \( -name '*.cc' -o -name '*.hh' -o -name '*.c' -o -name '*.h' -o -name 'machine.def' \) -exec perl -pi -e '\
s/\bbyte_t\b(?!\.hh)/uint8_t/g;\
s/\bsbyte_t\b(?!\.hh)/int8_t/g;\
s/\bhalf_t\b(?!\.hh)/uint16_t/g;\
s/\bshalf_t\b(?!\.hh)/int16_t/g;\
s/\bword_t\b(?!\.hh)/uint32_t/g;\
s/\bsword_t\b(?!\.hh)/int32_t/g;\
s/\bqword_t\b(?!\.hh)/uint64_t/g;\
s/\bsqword_t\b(?!\.hh)/int64_t/g;\
s/\bbool_t\b(?!\.hh)/bool/g;\
s/\bdfloat_t\b(?!\.hh)/double/g;\
s/\bsfloat_t\b(?!\.hh)/float/g;' {} \;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add CVS Id tags
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Massive renaming to (almost) eliminate all md_* and MD_* names
in preparation for total exorcism of machine.def.
Most of the changes in this commit were performed with the
following perl script (perl -pi <script> <files>). A small
amount of manual fixup was needed to (mostly getting rid of
the Addr typedefs in the various memory objects now that
the former md_addr_t has that name).
# rename machine-dependent types and constants (will be moving into ISA traits object)
s/md_addr_t/Addr/g;
s/md_intreg_t/IntReg/g;
s/md_gpr_t/IntRegFile/g;
s/md_fpreg_t/FloatReg/g;
s/md_fpr_t/FloatRegFile/g;
s/md_ctrlreg_t/MiscReg/g;
s/md_ctrl_t/MiscRegFile/g;
s/md_ipr_t/InternalProcReg/g;
s/md_anyreg_t/AnyReg/g;
s/md_inst_t/MachInst/g;
s/regs_t/RegFile/g;
# manually fix declaration in old/regs.h and a few forward decls
s/struct RegFile/RegFile/g;
s/MD_NUM_IREGS/NumIntRegs/g;
s/MD_NUM_FREGS/NumFloatRegs/g;
s/MD_NUM_CREGS/NumMiscRegs/g;
s/MD_IPR_NUM/NumInternalProcRegs/g;
s/MD_TOTAL_REGS/TotalNumRegs/g;
s/MD_REG_ZERO/ZeroReg/g;
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
New ISA description system. No more machine.def!
Instructions are now decoded into StaticInst objects, and all static
instruction properties (including execution behavior) are associated
with those objects. Extended documentation in progress.
Currently supports Alpha only; PISA will not compile.
Use END_OF_MACHINE_DOT_DEF tag to extract previous version.
src/arch/sparc/vtophys.cc:
get rid of MD_IPR_foo and call it IPR_foo
add some comments to describe what the various PALtemp registers do
formatting
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
license
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
a little style
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Add attribution to license.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Make include paths explicit.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
CopyData and CopyString moved from kernel.cc to vtophys.cc
kernel.cc and kernel.hh moved to kern/tru64
src/arch/sparc/vtophys.hh:
Include isa_traits.hh for Addr
src/arch/sparc/vtophys.cc:
formatting fixes
src/arch/sparc/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
src/arch/sparc/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
src/arch/sparc/vtophys.cc:
Fix to remote debugger while in PAL code
src/arch/sparc/vtophys.cc:
Remote an old hack that is now unnecessary
src/arch/sparc/vtophys.cc:
Removed buggy code that tries to fix PAL addresses (may cause problems
while trying to debug in PAL code, but that should do this fix outside
of vtophys)
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Updated Copyright
src/arch/sparc/vtophys.cc:
added back some code andrew removed and couldn't remember why.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
rename CopyData to CopyOut and implement CopyIn to copy data
from the simulator into the simulatee
src/arch/sparc/vtophys.cc:
fixed a bad merge from linux<->tru64
src/arch/sparc/vtophys.cc:
Check max address pal can be at so we don't do the wrong conversion
if gdb asks for an unaligned access.
src/arch/sparc/vtophys.cc:
PGOFSET -> ALPHA_PGOFSET to avoid include file problems
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
in the arch/alpha directory we should use arch/alpha, not
targetarch. sort includes while we're here.
src/arch/sparc/vtophys.cc:
use new constants, functions and structs to clean up the
vtophys code.
src/arch/sparc/vtophys.hh:
Clean up a little bit and make the protypes match new changes.
src/arch/sparc/vtophys.cc:
deal with isa addition
src/arch/sparc/vtophys.cc:
shuffle files around for new directory structure
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Remove RCS Id string
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
Update copyright dates and author list
src/arch/sparc/vtophys.cc:
Added a using directive for AlphaISA
src/arch/sparc/vtophys.hh:
Added the AlphaISA namespace specifier where needed
src/arch/sparc/vtophys.hh:
Made Addr a global type
src/arch/sparc/vtophys.cc:
Change access to the IPR to go through the XC.
src/arch/sparc/vtophys.cc:
Avoid directly accessing objects within the XC.
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
fixed for new memory system
put in namespace AlphaISA
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
Remove authors from copyright.
src/arch/sparc/vtophys.cc:
bk cp alpha/vtophys.cc sparc/vtophys.cc
src/arch/sparc/vtophys.hh:
bk cp alpha/vtophys.hh sparc/vtophys.hh
src/arch/sparc/SConscript:
remove fullsystem files that don't exist
src/arch/sparc/isa_traits.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
src/arch/sparc/regfile.hh:
split off fullsystem and se iprs into two functions to remove lots of #ifs
setup all initialization stuff for UA2005
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
Add system level tick storage to make stick be syncronized across multiple processors
src/arch/sparc/vtophys.hh:
start to create a vtophys for Sparc
src/base/loader/symtab.hh:
Addr is defined in sim/host.hh
--HG--
extra : convert_revision : ae4658e6bc2e2b51d7fb1c711d069ffe99e1377d
Rip out storage in miscreg file that will never store anything
Add storage and defines for Priv and Hyperpriv registers
Change defines to match the spec register numbers
Change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
Change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
Use bitfields for things that are rarely used in decoder
Instead of decoding ASR/PR/HPR and having a specfic instruction, use a generic instruction instead
Still todo:
Protect rdpr, rdhpr, wrpr, wrhpr with checks that fault in insufficient privs
Deal with signaling interrupts on timer expiration
Deal with writes to softint/PIL generating interrupts how those are vectored to the CPU
Other misc:
Instruction decoding needs major help!
src/arch/sparc/isa/decoder.isa:
Remove tons of MISCREG_XXXX defines that weren't used and ControlRegs in that were never used. Ones that were used rarely
changed to bitfields.
src/arch/sparc/isa/formats/integerop.isa:
These seems like a whole lot of overkill in printing, but i'll leave it the way it is for now. Allow Ccr to be set
at once
src/arch/sparc/isa/formats/priv.isa:
PrivTick is handled by miscreg now, don't need a seperate class for it
src/arch/sparc/isa/operands.isa:
prune the number of control regs down to a reasonable amount
src/arch/sparc/isa_traits.hh:
Replace 8 defines with 1 and flick some bits
src/arch/sparc/process.cc:
Better to clean the entire registers that specific bits which leads to indetermanistic behavior.
src/arch/sparc/regfile.hh:
Rip out storage that will never be backed by anything
Add storage for Priv and Hyperpriv registers
change defines to match the spec
change the way misc registers are named to match the spec with offsets to deal with ASR/PR/HPR/FSR.
change contextval to an int since both global registers and windowed registers are indexed by int in UA2005.
--HG--
extra : convert_revision : 64276a3ea884eea70112e721f85a515946ded4c2
It doesn't compile, and if we really want this we should
start over from scratch and see if we can reuse parts from
BaseSimpleCPU (e.g., derive a FastSimpleCPU).
SConstruct:
src/arch/SConscript:
src/cpu/cpu_models.py:
Get rid of FastCPU model.
--HG--
extra : convert_revision : f3f0362f7292bf21e8e0d4d84c475be8a9789a0c
src/arch/sparc/isa/formats/nop.isa:
Fix nop header so we can compile with multiple CPU models.
(Former code re-defined Nop object for each model.)
--HG--
extra : convert_revision : 04e92622edf4dfefd9e149a17f604e17a93707c9
