forgot to commit miscreg file
--HG-- extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
This commit is contained in:
Ali Saidi
parent
8b1bcc3f52
commit
4d57cab49a
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@ -37,10 +37,6 @@
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#if FULL_SYSTEM
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#include "arch/sparc/system.hh"
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#endif
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using namespace SparcISA;
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using namespace std;
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@ -50,15 +46,15 @@ class Checkpoint;
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string SparcISA::getMiscRegName(RegIndex index)
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{
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static::string miscRegName[NumMiscRegs] =
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{"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"stick", "stick_cmpr",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
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"wstate", "gl",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hstick_cmpr",
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"fsr"};
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{"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"stick", "stick_cmpr",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
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"wstate", "gl",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hstick_cmpr",
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"fsr"};
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return miscRegName[index];
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}
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@ -133,149 +129,149 @@ void MiscRegFile::clear()
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MiscReg MiscRegFile::readReg(int miscReg)
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{
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switch (miscReg) {
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case MISCREG_Y:
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return y;
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case MISCREG_CCR:
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return ccr;
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case MISCREG_ASI:
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return asi;
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case MISCREG_FPRS:
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return fprs;
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case MISCREG_TICK:
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return tick;
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case MISCREG_PCR:
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panic("PCR not implemented\n");
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case MISCREG_PIC:
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panic("PIC not implemented\n");
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case MISCREG_GSR:
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return gsr;
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case MISCREG_SOFTINT:
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return softint;
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case MISCREG_TICK_CMPR:
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return tick_cmpr;
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case MISCREG_STICK:
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return stick;
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case MISCREG_STICK_CMPR:
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return stick_cmpr;
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case MISCREG_Y:
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return y;
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case MISCREG_CCR:
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return ccr;
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case MISCREG_ASI:
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return asi;
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case MISCREG_FPRS:
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return fprs;
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case MISCREG_TICK:
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return tick;
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case MISCREG_PCR:
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panic("PCR not implemented\n");
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case MISCREG_PIC:
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panic("PIC not implemented\n");
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case MISCREG_GSR:
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return gsr;
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case MISCREG_SOFTINT:
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return softint;
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case MISCREG_TICK_CMPR:
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return tick_cmpr;
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case MISCREG_STICK:
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return stick;
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case MISCREG_STICK_CMPR:
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return stick_cmpr;
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/** Privilged Registers */
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case MISCREG_TPC:
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return tpc[tl-1];
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case MISCREG_TNPC:
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return tnpc[tl-1];
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case MISCREG_TSTATE:
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return tstate[tl-1];
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case MISCREG_TT:
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return tt[tl-1];
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick registers not implemented\n");
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case MISCREG_TBA:
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return tba;
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case MISCREG_PSTATE:
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return pstate;
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case MISCREG_TL:
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return tl;
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case MISCREG_PIL:
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return pil;
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case MISCREG_CWP:
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return cwp;
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case MISCREG_CANSAVE:
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return cansave;
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case MISCREG_CANRESTORE:
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return canrestore;
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case MISCREG_CLEANWIN:
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return cleanwin;
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case MISCREG_OTHERWIN:
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return otherwin;
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case MISCREG_WSTATE:
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return wstate;
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case MISCREG_GL:
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return gl;
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case MISCREG_TPC:
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return tpc[tl-1];
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case MISCREG_TNPC:
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return tnpc[tl-1];
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case MISCREG_TSTATE:
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return tstate[tl-1];
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case MISCREG_TT:
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return tt[tl-1];
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick registers not implemented\n");
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case MISCREG_TBA:
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return tba;
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case MISCREG_PSTATE:
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return pstate;
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case MISCREG_TL:
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return tl;
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case MISCREG_PIL:
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return pil;
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case MISCREG_CWP:
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return cwp;
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case MISCREG_CANSAVE:
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return cansave;
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case MISCREG_CANRESTORE:
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return canrestore;
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case MISCREG_CLEANWIN:
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return cleanwin;
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case MISCREG_OTHERWIN:
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return otherwin;
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case MISCREG_WSTATE:
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return wstate;
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case MISCREG_GL:
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return gl;
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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return hpstate;
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case MISCREG_HTSTATE:
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return htstate[tl-1];
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case MISCREG_HINTP:
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panic("HINTP not implemented\n");
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case MISCREG_HTBA:
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return htba;
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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case MISCREG_STRAND_STS_REG:
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return strandStatusReg;
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case MISCREG_HSTICK_CMPR:
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return hstick_cmpr;
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case MISCREG_HPSTATE:
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return hpstate;
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case MISCREG_HTSTATE:
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return htstate[tl-1];
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case MISCREG_HINTP:
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panic("HINTP not implemented\n");
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case MISCREG_HTBA:
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return htba;
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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case MISCREG_STRAND_STS_REG:
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return strandStatusReg;
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case MISCREG_HSTICK_CMPR:
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return hstick_cmpr;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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return fsr;
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case MISCREG_FSR:
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return fsr;
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case MISCREG_MMU_P_CONTEXT:
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return priContext;
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case MISCREG_MMU_S_CONTEXT:
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return secContext;
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case MISCREG_MMU_PART_ID:
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return partId;
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case MISCREG_MMU_LSU_CTRL:
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return lsuCtrlReg;
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case MISCREG_MMU_P_CONTEXT:
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return priContext;
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case MISCREG_MMU_S_CONTEXT:
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return secContext;
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case MISCREG_MMU_PART_ID:
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return partId;
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case MISCREG_MMU_LSU_CTRL:
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return lsuCtrlReg;
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case MISCREG_MMU_ITLB_C0_TSB_PS0:
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return iTlbC0TsbPs0;
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case MISCREG_MMU_ITLB_C0_TSB_PS1:
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return iTlbC0TsbPs1;
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case MISCREG_MMU_ITLB_C0_CONFIG:
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return iTlbC0Config;
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case MISCREG_MMU_ITLB_CX_TSB_PS0:
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return iTlbCXTsbPs0;
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case MISCREG_MMU_ITLB_CX_TSB_PS1:
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return iTlbCXTsbPs1;
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case MISCREG_MMU_ITLB_CX_CONFIG:
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return iTlbCXConfig;
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case MISCREG_MMU_ITLB_SFSR:
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return iTlbSfsr;
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case MISCREG_MMU_ITLB_TAG_ACCESS:
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return iTlbTagAccess;
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case MISCREG_MMU_ITLB_C0_TSB_PS0:
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return iTlbC0TsbPs0;
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case MISCREG_MMU_ITLB_C0_TSB_PS1:
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return iTlbC0TsbPs1;
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case MISCREG_MMU_ITLB_C0_CONFIG:
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return iTlbC0Config;
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case MISCREG_MMU_ITLB_CX_TSB_PS0:
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return iTlbCXTsbPs0;
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case MISCREG_MMU_ITLB_CX_TSB_PS1:
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return iTlbCXTsbPs1;
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case MISCREG_MMU_ITLB_CX_CONFIG:
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return iTlbCXConfig;
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case MISCREG_MMU_ITLB_SFSR:
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return iTlbSfsr;
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case MISCREG_MMU_ITLB_TAG_ACCESS:
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return iTlbTagAccess;
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case MISCREG_MMU_DTLB_C0_TSB_PS0:
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return dTlbC0TsbPs0;
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case MISCREG_MMU_DTLB_C0_TSB_PS1:
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return dTlbC0TsbPs1;
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case MISCREG_MMU_DTLB_C0_CONFIG:
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return dTlbC0Config;
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case MISCREG_MMU_DTLB_CX_TSB_PS0:
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return dTlbCXTsbPs0;
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case MISCREG_MMU_DTLB_CX_TSB_PS1:
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return dTlbCXTsbPs1;
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case MISCREG_MMU_DTLB_CX_CONFIG:
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return dTlbCXConfig;
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case MISCREG_MMU_DTLB_SFSR:
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return dTlbSfsr;
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case MISCREG_MMU_DTLB_SFAR:
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return dTlbSfar;
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case MISCREG_MMU_DTLB_TAG_ACCESS:
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return dTlbTagAccess;
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case MISCREG_MMU_DTLB_C0_TSB_PS0:
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return dTlbC0TsbPs0;
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case MISCREG_MMU_DTLB_C0_TSB_PS1:
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return dTlbC0TsbPs1;
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case MISCREG_MMU_DTLB_C0_CONFIG:
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return dTlbC0Config;
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case MISCREG_MMU_DTLB_CX_TSB_PS0:
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return dTlbCXTsbPs0;
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case MISCREG_MMU_DTLB_CX_TSB_PS1:
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return dTlbCXTsbPs1;
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case MISCREG_MMU_DTLB_CX_CONFIG:
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return dTlbCXConfig;
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case MISCREG_MMU_DTLB_SFSR:
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return dTlbSfsr;
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case MISCREG_MMU_DTLB_SFAR:
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return dTlbSfar;
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case MISCREG_MMU_DTLB_TAG_ACCESS:
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return dTlbTagAccess;
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case MISCREG_SCRATCHPAD_R0:
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return scratchPad[0];
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case MISCREG_SCRATCHPAD_R1:
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return scratchPad[1];
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case MISCREG_SCRATCHPAD_R2:
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return scratchPad[2];
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case MISCREG_SCRATCHPAD_R3:
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return scratchPad[3];
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case MISCREG_SCRATCHPAD_R4:
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return scratchPad[4];
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case MISCREG_SCRATCHPAD_R5:
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return scratchPad[5];
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case MISCREG_SCRATCHPAD_R6:
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return scratchPad[6];
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case MISCREG_SCRATCHPAD_R7:
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return scratchPad[7];
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case MISCREG_SCRATCHPAD_R0:
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return scratchPad[0];
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case MISCREG_SCRATCHPAD_R1:
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return scratchPad[1];
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case MISCREG_SCRATCHPAD_R2:
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return scratchPad[2];
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case MISCREG_SCRATCHPAD_R3:
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return scratchPad[3];
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case MISCREG_SCRATCHPAD_R4:
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return scratchPad[4];
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case MISCREG_SCRATCHPAD_R5:
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return scratchPad[5];
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case MISCREG_SCRATCHPAD_R6:
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return scratchPad[6];
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case MISCREG_SCRATCHPAD_R7:
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return scratchPad[7];
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default:
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panic("Miscellaneous register %d not implemented\n", miscReg);
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default:
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panic("Miscellaneous register %d not implemented\n", miscReg);
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}
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}
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@ -283,37 +279,42 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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{
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switch (miscReg) {
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// tick and stick are aliased to each other in niagra
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case MISCREG_STICK:
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case MISCREG_TICK:
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case MISCREG_PRIVTICK:
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// I'm not sure why legion ignores the lowest two bits, but we'll go
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// with it
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// change from curCycle() to instCount() until we're done with legion
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DPRINTFN("Instruction Count when STICK read: %#X\n",
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tc->getCpuPtr()->instCount());
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uint64_t t1 = mbits(tc->getCpuPtr()->instCount() - (tick &
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mask(63)),62,2);
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uint64_t t2 = mbits(tick,63,63) ;
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return t1 | t2;
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case MISCREG_FPRS:
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panic("FPU not implemented\n");
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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case MISCREG_TICK:
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case MISCREG_PRIVTICK:
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// I'm not sure why legion ignores the lowest two bits, but we'll go
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// with it
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// change from curCycle() to instCount() until we're done with legion
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DPRINTFN("Instruction Count when STICK read: %#X\n",
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tc->getCpuPtr()->instCount());
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return mbits(tc->getCpuPtr()->instCount() - (tick &
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mask(63)),62,2) | mbits(tick,63,63) ;
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case MISCREG_FPRS:
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panic("FPU not implemented\n");
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("Performance Instrumentation not impl\n");
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/** Floating Point Status Register */
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case MISCREG_FSR:
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panic("Floating Point not implemented\n");
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//We'll include this only in FS so we don't need the SparcSystem type around
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//in SE.
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/*#if FULL_SYSTEM
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case MISCREG_STICK:
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SparcSystem *sys;
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
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#endif*/
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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case MISCREG_FSR:
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panic("Floating Point not implemented\n");
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case MISCREG_STICK:
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case MISCREG_SOFTINT:
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case MISCREG_SOFTINT_CLR:
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case MISCREG_SOFTINT_SET:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_HTBA:
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case MISCREG_HVER:
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case MISCREG_STRAND_STS_REG:
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case MISCREG_HSTICK_CMPR:
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#if FULL_SYSTEM
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return readFSRegWithEffect(miscReg, tc);
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#else
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panic("Accessing Fullsystem register is SE mode\n");
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#endif
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}
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return readReg(miscReg);
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}
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@ -321,200 +322,200 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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void MiscRegFile::setReg(int miscReg, const MiscReg &val)
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{
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switch (miscReg) {
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case MISCREG_Y:
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y = val;
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break;
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case MISCREG_CCR:
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ccr = val;
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break;
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case MISCREG_ASI:
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asi = val;
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break;
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case MISCREG_FPRS:
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fprs = val;
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break;
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case MISCREG_TICK:
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tick = val;
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break;
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case MISCREG_PCR:
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panic("PCR not implemented\n");
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case MISCREG_PIC:
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panic("PIC not implemented\n");
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case MISCREG_GSR:
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gsr = val;
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break;
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case MISCREG_SOFTINT:
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softint = val;
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break;
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case MISCREG_TICK_CMPR:
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tick_cmpr = val;
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break;
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case MISCREG_STICK:
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stick = val;
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break;
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case MISCREG_STICK_CMPR:
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stick_cmpr = val;
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break;
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case MISCREG_Y:
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y = val;
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break;
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case MISCREG_CCR:
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ccr = val;
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break;
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case MISCREG_ASI:
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asi = val;
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break;
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case MISCREG_FPRS:
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fprs = val;
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break;
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case MISCREG_TICK:
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tick = val;
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
panic("PCR not implemented\n");
|
||||
case MISCREG_PIC:
|
||||
panic("PIC not implemented\n");
|
||||
case MISCREG_GSR:
|
||||
gsr = val;
|
||||
break;
|
||||
case MISCREG_SOFTINT:
|
||||
softint = val;
|
||||
break;
|
||||
case MISCREG_TICK_CMPR:
|
||||
tick_cmpr = val;
|
||||
break;
|
||||
case MISCREG_STICK:
|
||||
stick = val;
|
||||
break;
|
||||
case MISCREG_STICK_CMPR:
|
||||
stick_cmpr = val;
|
||||
break;
|
||||
|
||||
/** Privilged Registers */
|
||||
case MISCREG_TPC:
|
||||
tpc[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TNPC:
|
||||
tnpc[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TSTATE:
|
||||
tstate[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TT:
|
||||
tt[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_PRIVTICK:
|
||||
panic("Priviliged access to tick regesiters not implemented\n");
|
||||
case MISCREG_TBA:
|
||||
// clear lower 7 bits on writes.
|
||||
tba = val & ULL(~0x7FFF);
|
||||
break;
|
||||
case MISCREG_PSTATE:
|
||||
pstate = (val & PSTATE_MASK);
|
||||
break;
|
||||
case MISCREG_TL:
|
||||
tl = val;
|
||||
break;
|
||||
case MISCREG_PIL:
|
||||
pil = val;
|
||||
break;
|
||||
case MISCREG_CWP:
|
||||
cwp = val;
|
||||
break;
|
||||
case MISCREG_CANSAVE:
|
||||
cansave = val;
|
||||
break;
|
||||
case MISCREG_CANRESTORE:
|
||||
canrestore = val;
|
||||
break;
|
||||
case MISCREG_CLEANWIN:
|
||||
cleanwin = val;
|
||||
break;
|
||||
case MISCREG_OTHERWIN:
|
||||
otherwin = val;
|
||||
break;
|
||||
case MISCREG_WSTATE:
|
||||
wstate = val;
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
gl = val;
|
||||
break;
|
||||
case MISCREG_TPC:
|
||||
tpc[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TNPC:
|
||||
tnpc[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TSTATE:
|
||||
tstate[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_TT:
|
||||
tt[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_PRIVTICK:
|
||||
panic("Priviliged access to tick regesiters not implemented\n");
|
||||
case MISCREG_TBA:
|
||||
// clear lower 7 bits on writes.
|
||||
tba = val & ULL(~0x7FFF);
|
||||
break;
|
||||
case MISCREG_PSTATE:
|
||||
pstate = (val & PSTATE_MASK);
|
||||
break;
|
||||
case MISCREG_TL:
|
||||
tl = val;
|
||||
break;
|
||||
case MISCREG_PIL:
|
||||
pil = val;
|
||||
break;
|
||||
case MISCREG_CWP:
|
||||
cwp = val;
|
||||
break;
|
||||
case MISCREG_CANSAVE:
|
||||
cansave = val;
|
||||
break;
|
||||
case MISCREG_CANRESTORE:
|
||||
canrestore = val;
|
||||
break;
|
||||
case MISCREG_CLEANWIN:
|
||||
cleanwin = val;
|
||||
break;
|
||||
case MISCREG_OTHERWIN:
|
||||
otherwin = val;
|
||||
break;
|
||||
case MISCREG_WSTATE:
|
||||
wstate = val;
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
gl = val;
|
||||
break;
|
||||
|
||||
/** Hyper privileged registers */
|
||||
case MISCREG_HPSTATE:
|
||||
hpstate = val;
|
||||
break;
|
||||
case MISCREG_HTSTATE:
|
||||
htstate[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_HINTP:
|
||||
panic("HINTP not implemented\n");
|
||||
case MISCREG_HTBA:
|
||||
htba = val;
|
||||
break;
|
||||
case MISCREG_STRAND_STS_REG:
|
||||
strandStatusReg = val;
|
||||
break;
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
hstick_cmpr = val;
|
||||
break;
|
||||
case MISCREG_HPSTATE:
|
||||
hpstate = val;
|
||||
break;
|
||||
case MISCREG_HTSTATE:
|
||||
htstate[tl-1] = val;
|
||||
break;
|
||||
case MISCREG_HINTP:
|
||||
panic("HINTP not implemented\n");
|
||||
case MISCREG_HTBA:
|
||||
htba = val;
|
||||
break;
|
||||
case MISCREG_STRAND_STS_REG:
|
||||
strandStatusReg = val;
|
||||
break;
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
hstick_cmpr = val;
|
||||
break;
|
||||
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
fsr = val;
|
||||
break;
|
||||
case MISCREG_FSR:
|
||||
fsr = val;
|
||||
break;
|
||||
|
||||
case MISCREG_MMU_P_CONTEXT:
|
||||
priContext = val;
|
||||
break;
|
||||
case MISCREG_MMU_S_CONTEXT:
|
||||
secContext = val;
|
||||
break;
|
||||
case MISCREG_MMU_PART_ID:
|
||||
partId = val;
|
||||
break;
|
||||
case MISCREG_MMU_LSU_CTRL:
|
||||
lsuCtrlReg = val;
|
||||
break;
|
||||
case MISCREG_MMU_P_CONTEXT:
|
||||
priContext = val;
|
||||
break;
|
||||
case MISCREG_MMU_S_CONTEXT:
|
||||
secContext = val;
|
||||
break;
|
||||
case MISCREG_MMU_PART_ID:
|
||||
partId = val;
|
||||
break;
|
||||
case MISCREG_MMU_LSU_CTRL:
|
||||
lsuCtrlReg = val;
|
||||
break;
|
||||
|
||||
case MISCREG_MMU_ITLB_C0_TSB_PS0:
|
||||
iTlbC0TsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_C0_TSB_PS1:
|
||||
iTlbC0TsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_C0_CONFIG:
|
||||
iTlbC0Config = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_TSB_PS0:
|
||||
iTlbCXTsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_TSB_PS1:
|
||||
iTlbCXTsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_CONFIG:
|
||||
iTlbCXConfig = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_SFSR:
|
||||
iTlbSfsr = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_TAG_ACCESS:
|
||||
iTlbTagAccess = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_C0_TSB_PS0:
|
||||
iTlbC0TsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_C0_TSB_PS1:
|
||||
iTlbC0TsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_C0_CONFIG:
|
||||
iTlbC0Config = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_TSB_PS0:
|
||||
iTlbCXTsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_TSB_PS1:
|
||||
iTlbCXTsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_CX_CONFIG:
|
||||
iTlbCXConfig = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_SFSR:
|
||||
iTlbSfsr = val;
|
||||
break;
|
||||
case MISCREG_MMU_ITLB_TAG_ACCESS:
|
||||
iTlbTagAccess = val;
|
||||
break;
|
||||
|
||||
case MISCREG_MMU_DTLB_C0_TSB_PS0:
|
||||
dTlbC0TsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_C0_TSB_PS1:
|
||||
dTlbC0TsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_C0_CONFIG:
|
||||
dTlbC0Config = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_TSB_PS0:
|
||||
dTlbCXTsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_TSB_PS1:
|
||||
dTlbCXTsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_CONFIG:
|
||||
dTlbCXConfig = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_SFSR:
|
||||
dTlbSfsr = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_SFAR:
|
||||
dTlbSfar = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_TAG_ACCESS:
|
||||
dTlbTagAccess = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_C0_TSB_PS0:
|
||||
dTlbC0TsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_C0_TSB_PS1:
|
||||
dTlbC0TsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_C0_CONFIG:
|
||||
dTlbC0Config = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_TSB_PS0:
|
||||
dTlbCXTsbPs0 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_TSB_PS1:
|
||||
dTlbCXTsbPs1 = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_CX_CONFIG:
|
||||
dTlbCXConfig = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_SFSR:
|
||||
dTlbSfsr = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_SFAR:
|
||||
dTlbSfar = val;
|
||||
break;
|
||||
case MISCREG_MMU_DTLB_TAG_ACCESS:
|
||||
dTlbTagAccess = val;
|
||||
break;
|
||||
|
||||
case MISCREG_SCRATCHPAD_R0:
|
||||
scratchPad[0] = val;
|
||||
case MISCREG_SCRATCHPAD_R1:
|
||||
scratchPad[1] = val;
|
||||
case MISCREG_SCRATCHPAD_R2:
|
||||
scratchPad[2] = val;
|
||||
case MISCREG_SCRATCHPAD_R3:
|
||||
scratchPad[3] = val;
|
||||
case MISCREG_SCRATCHPAD_R4:
|
||||
scratchPad[4] = val;
|
||||
case MISCREG_SCRATCHPAD_R5:
|
||||
scratchPad[5] = val;
|
||||
case MISCREG_SCRATCHPAD_R6:
|
||||
scratchPad[6] = val;
|
||||
case MISCREG_SCRATCHPAD_R7:
|
||||
scratchPad[7] = val;
|
||||
case MISCREG_SCRATCHPAD_R0:
|
||||
scratchPad[0] = val;
|
||||
case MISCREG_SCRATCHPAD_R1:
|
||||
scratchPad[1] = val;
|
||||
case MISCREG_SCRATCHPAD_R2:
|
||||
scratchPad[2] = val;
|
||||
case MISCREG_SCRATCHPAD_R3:
|
||||
scratchPad[3] = val;
|
||||
case MISCREG_SCRATCHPAD_R4:
|
||||
scratchPad[4] = val;
|
||||
case MISCREG_SCRATCHPAD_R5:
|
||||
scratchPad[5] = val;
|
||||
case MISCREG_SCRATCHPAD_R6:
|
||||
scratchPad[6] = val;
|
||||
case MISCREG_SCRATCHPAD_R7:
|
||||
scratchPad[7] = val;
|
||||
|
||||
default:
|
||||
panic("Miscellaneous register %d not implemented\n", miscReg);
|
||||
default:
|
||||
panic("Miscellaneous register %d not implemented\n", miscReg);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -522,100 +523,47 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
|||
const MiscReg &val, ThreadContext * tc)
|
||||
{
|
||||
const uint64_t Bit64 = (1ULL << 63);
|
||||
#if FULL_SYSTEM
|
||||
uint64_t time;
|
||||
SparcSystem *sys;
|
||||
#endif
|
||||
switch (miscReg) {
|
||||
case MISCREG_STICK:
|
||||
case MISCREG_TICK:
|
||||
// change from curCycle() to instCount() until we're done with legion
|
||||
tick = tc->getCpuPtr()->instCount() - val & ~Bit64;
|
||||
tick |= val & Bit64;
|
||||
break;
|
||||
case MISCREG_FPRS:
|
||||
//Configure the fpu based on the fprs
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
//Set up performance counting based on pcr value
|
||||
break;
|
||||
case MISCREG_PSTATE:
|
||||
pstate = val & PSTATE_MASK;
|
||||
return;
|
||||
case MISCREG_TL:
|
||||
tl = val;
|
||||
return;
|
||||
case MISCREG_CWP:
|
||||
tc->changeRegFileContext(CONTEXT_CWP, val);
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
|
||||
break;
|
||||
case MISCREG_SOFTINT:
|
||||
//We need to inject interrupts, and or notify the interrupt
|
||||
//object that it needs to use a different interrupt level.
|
||||
//Any newly appropriate interrupts will happen when the cpu gets
|
||||
//around to checking for them. This might not be quite what we
|
||||
//want.
|
||||
break;
|
||||
case MISCREG_SOFTINT_CLR:
|
||||
//Do whatever this is supposed to do...
|
||||
break;
|
||||
case MISCREG_SOFTINT_SET:
|
||||
//Do whatever this is supposed to do...
|
||||
break;
|
||||
case MISCREG_STICK:
|
||||
case MISCREG_TICK:
|
||||
// change from curCycle() to instCount() until we're done with legion
|
||||
tick = tc->getCpuPtr()->instCount() - val & ~Bit64;
|
||||
tick |= val & Bit64;
|
||||
break;
|
||||
case MISCREG_FPRS:
|
||||
//Configure the fpu based on the fprs
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
//Set up performance counting based on pcr value
|
||||
break;
|
||||
case MISCREG_PSTATE:
|
||||
pstate = val & PSTATE_MASK;
|
||||
return;
|
||||
case MISCREG_TL:
|
||||
tl = val;
|
||||
return;
|
||||
case MISCREG_CWP:
|
||||
tc->changeRegFileContext(CONTEXT_CWP, val);
|
||||
break;
|
||||
case MISCREG_GL:
|
||||
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
|
||||
break;
|
||||
case MISCREG_PIL:
|
||||
case MISCREG_SOFTINT:
|
||||
case MISCREG_TICK_CMPR:
|
||||
case MISCREG_STICK_CMPR:
|
||||
case MISCREG_HPSTATE:
|
||||
case MISCREG_HINTP:
|
||||
case MISCREG_HTSTATE:
|
||||
case MISCREG_HTBA:
|
||||
case MISCREG_HVER:
|
||||
case MISCREG_STRAND_STS_REG:
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
#if FULL_SYSTEM
|
||||
case MISCREG_TICK_CMPR:
|
||||
if (tickCompare == NULL)
|
||||
tickCompare = new TickCompareEvent(this, tc);
|
||||
setReg(miscReg, val);
|
||||
if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
|
||||
tickCompare->deschedule();
|
||||
time = (tick_cmpr & mask(63)) - (tick & mask(63));
|
||||
if (!(tick_cmpr & ~mask(63)) && time > 0)
|
||||
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
|
||||
break;
|
||||
#endif
|
||||
case MISCREG_PIL:
|
||||
//We need to inject interrupts, and or notify the interrupt
|
||||
//object that it needs to use a different interrupt level.
|
||||
//Any newly appropriate interrupts will happen when the cpu gets
|
||||
//around to checking for them. This might not be quite what we
|
||||
//want.
|
||||
break;
|
||||
//We'll include this only in FS so we don't need the SparcSystem type around
|
||||
//in SE.
|
||||
#if FULL_SYSTEM
|
||||
// @todo figure out how we're actualy going to do this. In niagra the
|
||||
// registers are aliased to the same thing (see tick above)
|
||||
/*case MISCREG_STICK:
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
|
||||
stick |= val & Bit64;
|
||||
break;*/
|
||||
case MISCREG_STICK_CMPR:
|
||||
if (sTickCompare == NULL)
|
||||
sTickCompare = new STickCompareEvent(this, tc);
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
|
||||
sTickCompare->deschedule();
|
||||
time = (stick_cmpr & mask(63)) - sys->sysTick;
|
||||
if (!(stick_cmpr & ~mask(63)) && time > 0)
|
||||
sTickCompare->schedule(time * Clock::Int::ns);
|
||||
break;
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
if (hSTickCompare == NULL)
|
||||
hSTickCompare = new HSTickCompareEvent(this, tc);
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
|
||||
hSTickCompare->deschedule();
|
||||
int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
|
||||
if (!(hstick_cmpr & ~mask(63)) && time > 0)
|
||||
hSTickCompare->schedule(time * Clock::Int::ns);
|
||||
break;
|
||||
setFSRegWithEffect(miscReg, val, tc);
|
||||
return;
|
||||
#else
|
||||
panic("Accessing Fullsystem register is SE mode\n");
|
||||
#endif
|
||||
}
|
||||
setReg(miscReg, val);
|
||||
|
|
@ -720,24 +668,5 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
|
|||
UNSERIALIZE_SCALAR(dTlbSfsr);
|
||||
UNSERIALIZE_SCALAR(dTlbSfar);
|
||||
UNSERIALIZE_SCALAR(dTlbTagAccess);
|
||||
UNSERIALIZE_ARRAY(scratchPad,8);}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
void
|
||||
MiscRegFile::processTickCompare(ThreadContext *tc)
|
||||
{
|
||||
panic("tick compare not implemented\n");
|
||||
UNSERIALIZE_ARRAY(scratchPad,8);
|
||||
}
|
||||
|
||||
void
|
||||
MiscRegFile::processSTickCompare(ThreadContext *tc)
|
||||
{
|
||||
panic("tick compare not implemented\n");
|
||||
}
|
||||
|
||||
void
|
||||
MiscRegFile::processHSTickCompare(ThreadContext *tc)
|
||||
{
|
||||
panic("tick compare not implemented\n");
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue