Set the ASI register to be something explicitly so that simulation is deterministic.

--HG--
extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
This commit is contained in:
Gabe Black 2006-11-10 04:14:25 -05:00
parent 1d70dda6d7
commit dc6af9fbf7

View file

@ -29,6 +29,7 @@
* Ali Saidi
*/
#include "arch/sparc/asi.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/process.hh"
#include "base/loader/object_file.hh"
@ -105,6 +106,8 @@ SparcLiveProcess::startup()
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
//Set the trap level to 0
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
//Set the ASI register to something fixed
threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
}
m5_auxv_t buildAuxVect(int64_t type, int64_t val)