Set the ASI register to be something explicitly so that simulation is deterministic.
--HG-- extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
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@ -29,6 +29,7 @@
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* Ali Saidi
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*/
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "base/loader/object_file.hh"
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@ -105,6 +106,8 @@ SparcLiveProcess::startup()
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threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
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//Set the trap level to 0
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threadContexts[0]->setMiscReg(MISCREG_TL, 0);
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//Set the ASI register to something fixed
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threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
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}
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m5_auxv_t buildAuxVect(int64_t type, int64_t val)
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