add fcntl64Func

use ThreadContext rename

src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/includes.isa:
    Use ThreadContext
src/sim/syscall_emul.cc:
    fcntl64 function using TC
src/sim/syscall_emul.hh:
    Add fcntl64func

--HG--
extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
This commit is contained in:
Korey Sewell 2006-06-09 17:07:13 -04:00
parent 68e470f78a
commit 4cc31e1aef
5 changed files with 45 additions and 12 deletions

View file

@ -88,7 +88,7 @@ output header {{
{
}
Addr branchTarget(ExecContext *xc) const;
Addr branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@ -103,10 +103,10 @@ output decoder {{
}
Addr
Jump::branchTarget(ExecContext *xc) const
Jump::branchTarget(ThreadContext *tc) const
{
Addr NPC = xc->readPC() + 4;
uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
Addr NPC = tc->readPC() + 4;
uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}

View file

@ -95,7 +95,7 @@ output exec {{
template <class T>
bool
fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
Trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
@ -111,13 +111,13 @@ output exec {{
}
//Set value to QNAN
xc->setFloatRegBits(inst, 0, mips_nan, size);
cpu->setFloatRegBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
//Write FCSR from FloatRegFile
xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
if (traceData) { traceData->setData(mips_nan); }
return true;
@ -127,15 +127,15 @@ output exec {{
}
void
fpResetCauseBits(%(CPU_exec_context)s *xc)
fpResetCauseBits(%(CPU_exec_context)s *cpu)
{
//Read FCSR from FloatRegFile
uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
//Write FCSR from FloatRegFile
xc->cpuXC->setFloatRegBits(FCSR, fcsr);
cpu->tc->setFloatRegBits(FCSR, fcsr);
}
}};

View file

@ -18,7 +18,7 @@ output decoder {{
#include "arch/mips/isa_traits.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh" // for Jump::branchTarget()
#include "cpu/thread_context.hh"
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/utility.hh"

View file

@ -340,6 +340,35 @@ fcntlFunc(SyscallDesc *desc, int num, Process *process,
}
}
SyscallReturn
fcntl64Func(SyscallDesc *desc, int num, Process *process,
ThreadContext *tc)
{
int fd = tc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0)
return -EBADF;
int cmd = tc->getSyscallArg(1);
switch (cmd) {
case 33: //F_GETLK64
warn("fcntl64(%d, F_GETLK64) not supported, error returned\n", fd);
return -EMFILE;
case 34: // F_SETLK64
case 35: // F_SETLKW64
warn("fcntl64(%d, F_SETLK(W)64) not supported, error returned\n", fd);
return -EMFILE;
default:
// not sure if this is totally valid, but we'll pass it through
// to the underlying OS
warn("fcntl64(%d, %d) passed through to host\n", fd, cmd);
return fcntl(process->sim_fd(fd), cmd);
// return 0;
}
}
SyscallReturn
pipePseudoFunc(SyscallDesc *desc, int callnum, Process *process,
ThreadContext *tc)

View file

@ -249,6 +249,10 @@ SyscallReturn fchownFunc(SyscallDesc *desc, int num,
SyscallReturn fcntlFunc(SyscallDesc *desc, int num,
Process *process, ThreadContext *tc);
/// Target fcntl64() handler.
SyscallReturn fcntl64Func(SyscallDesc *desc, int num,
Process *process, ThreadContext *tc);
/// Target setuid() handler.
SyscallReturn setuidFunc(SyscallDesc *desc, int num,
Process *p, ThreadContext *tc);