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Fixes for SPARC_FS

Browse source 
configs/common/FSConfig.py:
    Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
    Create a T1000 platform
src/arch/sparc/miscregfile.cc:
    Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
    Truncate an ExtMachInst to a MachInst before comparing with Legion.

--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
This commit is contained in:
Gabe Black 2006-11-16 12:34:10 -05:00
parent 079dd45417
commit cd5b33b9ff
4 changed files with 15 additions and 51 deletions
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6
configs/common/FSConfig.py
View file

@ -84,8 +84,14 @@ def makeSparcSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
self.bridge = Bridge()
self.t1000 = T1000()
self.t1000.attachIO(self.iobus)
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
self.bridge.side_a = self.iobus.port
self.bridge.side_b = self.membus.port
self.physmem.port = self.membus.port
self.rom.port = self.membus.port
self.intrctrl = IntrControl()

3
src/arch/sparc/miscregfile.cc
View file

@ -94,7 +94,8 @@ void MiscRegFile::reset()
hintp = 0;
htba = 0;
hstick_cmpr = 0;
strandStatusReg = 0;
//This is set this way in Legion for some reason
strandStatusReg = 0x50000;
fsr = 0;
implicitInstAsi = ASI_PRIMARY;
implicitDataAsi = ASI_PRIMARY;

4
src/cpu/exetrace.cc
View file

@ -247,8 +247,10 @@ Trace::InstRecord::dump(ostream &outs)
if (shared_data->flags == OWN_M5) {
if (lgnPc != m5Pc)
diffPC = true;
if (shared_data->instruction != staticInst->machInst)
if (shared_data->instruction !=
(SparcISA::MachInst)staticInst->machInst) {
diffInst = true;
}
for (int i = 0; i < TheISA::NumRegularIntRegs; i++) {
if (thread->readIntReg(i) != shared_data->intregs[i]) {
diffRegs = true;

53
src/python/m5/objects/T1000.py
View file

@ -1,11 +1,9 @@
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
from Platform import Platform
from AlphaConsole import AlphaConsole
from Uart import Uart8250
from Pci import PciConfigAll
from BadDevice import BadDevice
from Platform import Platform
from SimConsole import SimConsole, ConsoleListener
class IsaFake(BasicPioDevice):
type = 'IsaFake'
@ -22,55 +20,12 @@ class T1000(Platform):
fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
fake_ata1 = IsaFake(pio_addr=0x801fc000170)
fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
uart = Uart8250(pio_addr=0x801fc0003f8)
uart = Uart8250(pio_addr=0xfff0c2c000)
console = SimConsole(listener = ConsoleListener())
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
self.fake_iob.pio = bus.port
self.fake_uart1.pio = bus.port
self.fake_uart2.pio = bus.port
self.fake_uart3.pio = bus.port
self.fake_uart4.pio = bus.port
self.fake_ppc.pio = bus.port
self.fake_OROM.pio = bus.port
self.fake_pnp_addr.pio = bus.port
self.fake_pnp_write.pio = bus.port
self.fake_pnp_read0.pio = bus.port
self.fake_pnp_read1.pio = bus.port
self.fake_pnp_read2.pio = bus.port
self.fake_pnp_read3.pio = bus.port
self.fake_pnp_read4.pio = bus.port
self.fake_pnp_read5.pio = bus.port
self.fake_pnp_read6.pio = bus.port
self.fake_pnp_read7.pio = bus.port
self.fake_ata0.pio = bus.port
self.fake_ata1.pio = bus.port
self.fb.pio = bus.port
self.io.pio = bus.port
self.uart.pio = bus.port