Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.
--HG-- extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
This commit is contained in:
Gabe Black
parent
232c3f1b27
commit
4aea5deccb
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@ -346,22 +346,93 @@ decode OP default Unknown::unknown()
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0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
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0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
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}
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// XXX might want a format rdipr thing here
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0x28: decode RS1 {
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0xF: decode I {
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0x00: NoPriv::rdy({{Rd = Y;}});
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//1 should cause an illegal instruction exception
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0x02: NoPriv::rdccr({{Rd = Ccr;}});
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0x03: NoPriv::rdasi({{Rd = Asi;}});
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0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
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0x05: NoPriv::rdpc({{
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if(Pstate<3:>)
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Rd = (xc->readPC())<31:0>;
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else
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Rd = xc->readPC();}});
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0x06: NoPriv::rdfprs({{
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//Wait for all fpops to finish.
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Rd = Fprs;
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}});
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//7-14 should cause an illegal instruction exception
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0x0F: decode I {
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0x0: Nop::stbar({{/*stuff*/}});
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0x1: Nop::membar({{/*stuff*/}});
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}
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default: rdasr({{
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Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
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0x10: Priv::rdpcr({{Rd = Pcr;}});
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0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
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//0x12 should cause an illegal instruction exception
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0x13: NoPriv::rdgsr({{
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if(Fprs<2:> == 0 || Pstate<4:> == 0)
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Rd = Gsr;
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else
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fault = new FpDisabled;
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}});
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//0x14-0x15 should cause an illegal instruction exception
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0x16: Priv::rdsoftint({{Rd = Softint;}});
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0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
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0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
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0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
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//0x1A-0x1F should cause an illegal instruction exception
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}
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0x29: decode RS1 {
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0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
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0x01: HPriv::rdhprhtstate({{
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if(Tl == 0)
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return new IllegalInstruction;
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Rd = Htstate;
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}});
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//0x02 should cause an illegal instruction exception
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0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
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//0x04 should cause an illegal instruction exception
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0x05: HPriv::rdhprhtba({{Rd = Htba;}});
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0x06: HPriv::rdhprhver({{Rd = Hver;}});
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//0x07-0x1E should cause an illegal instruction exception
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0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
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}
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0x2A: decode RS1 {
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0x00: Priv::rdprtpc({{
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if(Tl == 0)
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return new IllegalInstruction;
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Rd = Tpc;
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}});
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0x01: Priv::rdprtnpc({{
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if(Tl == 0)
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return new IllegalInstruction;
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Rd = Tnpc;
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}});
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0x02: Priv::rdprtstate({{
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if(Tl == 0)
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return new IllegalInstruction;
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Rd = Tstate;
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}});
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0x03: Priv::rdprtt({{
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if(Tl == 0)
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return new IllegalInstruction;
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Rd = Tt;
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}});
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0x04: Priv::rdprtick({{Rd = Tick;}});
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0x05: Priv::rdprtba({{Rd = Tba;}});
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0x06: Priv::rdprpstate({{Rd = Pstate;}});
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0x07: Priv::rdprtl({{Rd = Tl;}});
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0x08: Priv::rdprpil({{Rd = Pil;}});
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0x09: Priv::rdprcwp({{Rd = Cwp;}});
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0x0A: Priv::rdprcansave({{Rd = Cansave;}});
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0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
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0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
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0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
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0x0E: Priv::rdprwstate({{Rd = Wstate;}});
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//0x0F should cause an illegal instruction exception
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0x10: Priv::rdprgl({{Rd = Gl;}});
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//0x11-0x1F should cause an illegal instruction exception
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}
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0x29: HPriv::rdhpr({{
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Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
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}});
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0x2A: Priv::rdpr({{
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Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
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}});
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0x2B: BasicOperate::flushw({{
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if(NWindows - 2 - Cansave == 0)
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{
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@ -417,9 +488,35 @@ decode OP default Unknown::unknown()
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0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
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0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
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}
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0x30: wrasr({{
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xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x30: decode RD {
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0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
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//0x01 should cause an illegal instruction exception
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0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
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0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
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//0x04-0x05 should cause an illegal instruction exception
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0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
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//0x07-0x0E should cause an illegal instruction exception
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0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
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0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
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0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
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//0x12 should cause an illegal instruction exception
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0x13: NoPriv::wrgsr({{
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if(Fprs<2:> == 0 || Pstate<4:> == 0)
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return new FpDisabled;
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Gsr = Rs1 ^ Rs2_or_imm13;
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}});
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0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
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0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
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0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
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0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
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0x18: NoPriv::wrstick({{
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if(!Hpstate<2:>)
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return new IllegalInstruction;
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Stick = Rs1 ^ Rs2_or_imm13;
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}});
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0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
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//0x1A-0x1F should cause an illegal instruction exception
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}
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0x31: decode FCN {
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0x0: Priv::saved({{
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assert(Cansave < NWindows - 2);
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@ -440,16 +537,70 @@ decode OP default Unknown::unknown()
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Otherwin = Otherwin - 1;
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}});
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}
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0x32: Priv::wrpr({{
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// XXX Need to protect with format that traps non-priv
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// access
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xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x33: HPriv::wrhpr({{
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// XXX Need to protect with format that traps non-priv/priv
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// access
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xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
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}});
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0x32: decode RD {
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0x00: Priv::wrprtpc({{
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if(Tl == 0)
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return new IllegalInstruction;
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else
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Tpc = Rs1 ^ Rs2_or_imm13;
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}});
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0x01: Priv::wrprtnpc({{
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if(Tl == 0)
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return new IllegalInstruction;
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else
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Tnpc = Rs1 ^ Rs2_or_imm13;
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}});
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0x02: Priv::wrprtstate({{
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if(Tl == 0)
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return new IllegalInstruction;
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else
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Tstate = Rs1 ^ Rs2_or_imm13;
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}});
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0x03: Priv::wrprtt({{
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if(Tl == 0)
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return new IllegalInstruction;
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else
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Tt = Rs1 ^ Rs2_or_imm13;
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}});
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0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
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0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
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0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
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0x07: Priv::wrprtl({{
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if(Pstate<2:> && !Hpstate<2:>)
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Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
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else
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Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
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}});
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0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
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0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
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0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
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0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
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0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
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0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
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0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
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//0x0F should cause an illegal instruction exception
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0x10: Priv::wrprgl({{
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if(Pstate<2:> && !Hpstate<2:>)
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Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
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else
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Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
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}});
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//0x11-0x1F should cause an illegal instruction exception
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}
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0x33: decode RD {
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0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
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0x01: HPriv::wrhprhtstate({{
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if(Tl == 0)
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return new IllegalInstruction;
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Htstate = Rs1 ^ Rs2_or_imm13;
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}});
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//0x02 should cause an illegal instruction exception
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0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
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//0x04 should cause an illegal instruction exception
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0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
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//0x06-0x01D should cause an illegal instruction exception
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0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
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}
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0x34: decode OPF{
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format BasicOperate{
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0x01: fmovs({{
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@ -119,18 +119,34 @@ let {{
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return (header_output, decoder_output, exec_output, decode_block)
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}};
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// Primary format for integer operate instructions:
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def format Priv(code, *opt_flags) {{
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checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
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checkCode = "!(Pstate<2:> || Hpstate<2:>)"
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags + ('IprAccessOp',))
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checkCode, name, Name, opt_flags)
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}};
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def format NoPriv(code, *opt_flags) {{
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#Instructions which use this format don't really check for
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#any particular mode, but the disassembly is performed
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#using the control registers actual name
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checkCode = "false"
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags)
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}};
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def format PrivCheck(code, extraCheckCode, *opt_flags) {{
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checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags)
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}};
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def format HPriv(code, *opt_flags) {{
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checkCode = "!Hpstate<2:2>"
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(header_output, decoder_output,
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exec_output, decode_block) = doPrivFormat(code,
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checkCode, name, Name, opt_flags + ('IprAccessOp',))
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checkCode, name, Name, opt_flags)
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}};
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@ -54,6 +54,7 @@ output decoder {{
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#if defined(linux)
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#include <fenv.h>
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#endif
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#include <algorithm>
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using namespace SparcISA;
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}};
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@ -80,8 +80,6 @@ def operands {{
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
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#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R1': ('IntReg', 'udw', '1', None, 7),
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'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
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@ -91,24 +89,42 @@ def operands {{
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'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
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'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
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'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
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'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
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'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
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'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
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'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
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'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
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'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
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'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
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'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
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'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
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'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
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'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43),
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'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
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'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
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'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
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'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
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'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
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'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
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'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
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'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
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'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62),
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'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
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'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
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'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
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'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
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'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
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'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
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'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
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'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
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'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
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'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
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'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
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'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
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'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
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'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
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'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
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'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
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'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
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'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
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# Mem gets a large number so it's always last
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'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
*/
|
||||
|
||||
#include "arch/sparc/miscregfile.hh"
|
||||
#include "base/bitfield.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/base.hh"
|
||||
|
|
@ -78,8 +79,9 @@ MiscReg MiscRegFile::readReg(int miscReg)
|
|||
case MISCREG_TICK:
|
||||
return tick;
|
||||
case MISCREG_PCR:
|
||||
panic("PCR not implemented\n");
|
||||
case MISCREG_PIC:
|
||||
panic("ASR number %d not implemented\n", miscReg - AsrStart);
|
||||
panic("PIC not implemented\n");
|
||||
case MISCREG_GSR:
|
||||
return gsr;
|
||||
case MISCREG_SOFTINT:
|
||||
|
|
@ -154,8 +156,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
|||
switch (miscReg) {
|
||||
case MISCREG_TICK:
|
||||
case MISCREG_PRIVTICK:
|
||||
return tc->getCpuPtr()->curCycle() - tickFields.counter |
|
||||
tickFields.npt << 63;
|
||||
return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
|
||||
(tick & ~(mask(63))) << 63;
|
||||
case MISCREG_FPRS:
|
||||
panic("FPU not implemented\n");
|
||||
case MISCREG_PCR:
|
||||
|
|
@ -171,7 +173,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
|||
SparcSystem *sys;
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
|
||||
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
|
||||
#endif
|
||||
case MISCREG_HVER:
|
||||
return NWindows | MaxTL << 8 | MaxGL << 16;
|
||||
|
|
@ -198,8 +200,9 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
|
|||
tick = val;
|
||||
break;
|
||||
case MISCREG_PCR:
|
||||
panic("PCR not implemented\n");
|
||||
case MISCREG_PIC:
|
||||
panic("ASR number %d not implemented\n", miscReg - AsrStart);
|
||||
panic("PIC not implemented\n");
|
||||
case MISCREG_GSR:
|
||||
gsr = val;
|
||||
break;
|
||||
|
|
@ -303,12 +306,12 @@ inline void MiscRegFile::setImplicitAsis()
|
|||
if(tl == 0)
|
||||
{
|
||||
implicitInstAsi = implicitDataAsi =
|
||||
pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
|
||||
(pstate & (1 << 9)) ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
|
||||
}
|
||||
else if(tl <= MaxPTL)
|
||||
{
|
||||
implicitInstAsi = ASI_NUCLEUS;
|
||||
implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
|
||||
implicitDataAsi = (pstate & (1 << 9)) ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -328,8 +331,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
|||
#endif
|
||||
switch (miscReg) {
|
||||
case MISCREG_TICK:
|
||||
tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
|
||||
tickFields.npt = val & Bit64 ? 1 : 0;
|
||||
tick = tc->getCpuPtr()->curCycle() - val & ~Bit64;
|
||||
tick |= val & Bit64;
|
||||
break;
|
||||
case MISCREG_FPRS:
|
||||
//Configure the fpu based on the fprs
|
||||
|
|
@ -369,10 +372,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
|||
if (tickCompare == NULL)
|
||||
tickCompare = new TickCompareEvent(this, tc);
|
||||
setReg(miscReg, val);
|
||||
if (tick_cmprFields.int_dis && tickCompare->scheduled())
|
||||
if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
|
||||
tickCompare->deschedule();
|
||||
time = tick_cmprFields.tick_cmpr - tickFields.counter;
|
||||
if (!tick_cmprFields.int_dis && time > 0)
|
||||
time = (tick_cmpr & mask(63)) - (tick & mask(63));
|
||||
if (!(tick_cmpr & ~mask(63)) && time > 0)
|
||||
tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
|
||||
break;
|
||||
#endif
|
||||
|
|
@ -390,17 +393,17 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
|||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
|
||||
stickFields.npt = val & Bit64 ? 1 : 0;
|
||||
stick |= val & Bit64;
|
||||
break;
|
||||
case MISCREG_STICK_CMPR:
|
||||
if (sTickCompare == NULL)
|
||||
sTickCompare = new STickCompareEvent(this, tc);
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
if (stick_cmprFields.int_dis && sTickCompare->scheduled())
|
||||
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
|
||||
sTickCompare->deschedule();
|
||||
time = stick_cmprFields.tick_cmpr - sys->sysTick;
|
||||
if (!stick_cmprFields.int_dis && time > 0)
|
||||
time = (stick_cmpr & mask(63)) - sys->sysTick;
|
||||
if (!(stick_cmpr & ~mask(63)) && time > 0)
|
||||
sTickCompare->schedule(time * Clock::Int::ns);
|
||||
break;
|
||||
case MISCREG_HSTICK_CMPR:
|
||||
|
|
@ -408,10 +411,10 @@ void MiscRegFile::setRegWithEffect(int miscReg,
|
|||
hSTickCompare = new HSTickCompareEvent(this, tc);
|
||||
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
|
||||
assert(sys != NULL);
|
||||
if (hstick_cmprFields.int_dis && hSTickCompare->scheduled())
|
||||
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
|
||||
hSTickCompare->deschedule();
|
||||
int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
|
||||
if (!hstick_cmprFields.int_dis && time > 0)
|
||||
int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
|
||||
if (!(hstick_cmpr & ~mask(63)) && time > 0)
|
||||
hSTickCompare->schedule(time * Clock::Int::ns);
|
||||
break;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -92,8 +92,7 @@ namespace SparcISA
|
|||
MISCREG_HSTICK_CMPR,
|
||||
|
||||
/** Floating Point Status Register */
|
||||
MISCREG_FSR,
|
||||
NumMiscRegs
|
||||
MISCREG_FSR
|
||||
};
|
||||
|
||||
// The control registers, broken out into fields
|
||||
|
|
@ -102,93 +101,16 @@ namespace SparcISA
|
|||
private:
|
||||
|
||||
/* ASR Registers */
|
||||
union {
|
||||
uint64_t y; // Y (used in obsolete multiplication)
|
||||
struct {
|
||||
uint64_t value:32; // The actual value stored in y
|
||||
uint64_t :32; // reserved bits
|
||||
} yFields;
|
||||
};
|
||||
union {
|
||||
uint8_t ccr; // Condition Code Register
|
||||
struct {
|
||||
union {
|
||||
uint8_t icc:4; // 32-bit condition codes
|
||||
struct {
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} iccFields;
|
||||
};
|
||||
union {
|
||||
uint8_t xcc:4; // 64-bit condition codes
|
||||
struct {
|
||||
uint8_t c:1; // Carry
|
||||
uint8_t v:1; // Overflow
|
||||
uint8_t z:1; // Zero
|
||||
uint8_t n:1; // Negative
|
||||
} xccFields;
|
||||
};
|
||||
} ccrFields;
|
||||
};
|
||||
uint64_t y; // Y (used in obsolete multiplication)
|
||||
uint8_t ccr; // Condition Code Register
|
||||
uint8_t asi; // Address Space Identifier
|
||||
union {
|
||||
uint64_t tick; // Hardware clock-tick counter
|
||||
struct {
|
||||
int64_t counter:63; // Clock-tick count
|
||||
uint64_t npt:1; // Non-priveleged trap
|
||||
} tickFields;
|
||||
};
|
||||
union {
|
||||
uint8_t fprs; // Floating-Point Register State
|
||||
struct {
|
||||
uint8_t dl:1; // Dirty lower
|
||||
uint8_t du:1; // Dirty upper
|
||||
uint8_t fef:1; // FPRS enable floating-Point
|
||||
} fprsFields;
|
||||
};
|
||||
union {
|
||||
uint64_t gsr; //General Status Register
|
||||
struct {
|
||||
uint64_t mask:32;
|
||||
uint64_t :4;
|
||||
uint64_t im:1;
|
||||
uint64_t irnd:2;
|
||||
uint64_t :17;
|
||||
uint64_t scale:5;
|
||||
uint64_t align:3;
|
||||
} gsrFields;
|
||||
};
|
||||
union {
|
||||
uint64_t softint;
|
||||
struct {
|
||||
uint64_t tm:1;
|
||||
uint64_t int_level:14;
|
||||
uint64_t sm:1;
|
||||
} softintFields;
|
||||
};
|
||||
union {
|
||||
uint64_t tick_cmpr; // Hardware tick compare registers
|
||||
struct {
|
||||
uint64_t tick_cmpr:63; // Clock-tick count
|
||||
uint64_t int_dis:1; // Non-priveleged trap
|
||||
} tick_cmprFields;
|
||||
};
|
||||
union {
|
||||
uint64_t stick; // Hardware clock-tick counter
|
||||
struct {
|
||||
int64_t :63; // Not used, storage in SparcSystem
|
||||
uint64_t npt:1; // Non-priveleged trap
|
||||
} stickFields;
|
||||
};
|
||||
union {
|
||||
uint64_t stick_cmpr; // Hardware tick compare registers
|
||||
struct {
|
||||
uint64_t tick_cmpr:63; // Clock-tick count
|
||||
uint64_t int_dis:1; // Non-priveleged trap
|
||||
} stick_cmprFields;
|
||||
};
|
||||
uint64_t tick; // Hardware clock-tick counter
|
||||
uint8_t fprs; // Floating-Point Register State
|
||||
uint64_t gsr; // General Status Register
|
||||
uint64_t softint;
|
||||
uint64_t tick_cmpr; // Hardware tick compare registers
|
||||
uint64_t stick; // Hardware clock-tick counter
|
||||
uint64_t stick_cmpr; // Hardware tick compare registers
|
||||
|
||||
|
||||
/* Privileged Registers */
|
||||
|
|
@ -196,37 +118,12 @@ namespace SparcISA
|
|||
// previous trap level)
|
||||
uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
|
||||
// previous trap level)
|
||||
union {
|
||||
uint64_t tstate[MaxTL]; // Trap State
|
||||
struct {
|
||||
//Values are from previous trap level
|
||||
uint64_t cwp:5; // Current Window Pointer
|
||||
uint64_t :3; // Reserved bits
|
||||
uint64_t pstate:13; // Process State
|
||||
uint64_t :3; // Reserved bits
|
||||
uint64_t asi:8; // Address Space Identifier
|
||||
uint64_t ccr:8; // Condition Code Register
|
||||
uint64_t gl:8; // Global level
|
||||
} tstateFields[MaxTL];
|
||||
};
|
||||
uint64_t tstate[MaxTL]; // Trap State
|
||||
uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
|
||||
// on the previous level)
|
||||
uint64_t tba; // Trap Base Address
|
||||
|
||||
union {
|
||||
uint16_t pstate; // Process State Register
|
||||
struct {
|
||||
uint16_t :1; // reserved
|
||||
uint16_t ie:1; // Interrupt enable
|
||||
uint16_t priv:1; // Privelege mode
|
||||
uint16_t am:1; // Address mask
|
||||
uint16_t pef:1; // PSTATE enable floating-point
|
||||
uint16_t :1; // reserved2
|
||||
uint16_t mm:2; // Memory Model
|
||||
uint16_t tle:1; // Trap little-endian
|
||||
uint16_t cle:1; // Current little-endian
|
||||
} pstateFields;
|
||||
};
|
||||
uint16_t pstate; // Process State Register
|
||||
uint8_t tl; // Trap Level
|
||||
uint8_t pil; // Process Interrupt Register
|
||||
uint8_t cwp; // Current Window Pointer
|
||||
|
|
@ -234,97 +131,20 @@ namespace SparcISA
|
|||
uint8_t canrestore; // Restorable windows
|
||||
uint8_t cleanwin; // Clean windows
|
||||
uint8_t otherwin; // Other windows
|
||||
union {
|
||||
uint8_t wstate; // Window State
|
||||
struct {
|
||||
uint8_t normal:3; // Bits TT<4:2> are set to on a normal
|
||||
// register window trap
|
||||
uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin"
|
||||
// register window trap
|
||||
} wstateFields;
|
||||
};
|
||||
uint8_t wstate; // Window State
|
||||
uint8_t gl; // Global level register
|
||||
|
||||
|
||||
/** Hyperprivileged Registers */
|
||||
union {
|
||||
uint64_t hpstate; // Hyperprivileged State Register
|
||||
struct {
|
||||
uint8_t tlz: 1;
|
||||
uint8_t :1;
|
||||
uint8_t hpriv:1;
|
||||
uint8_t :2;
|
||||
uint8_t red:1;
|
||||
uint8_t :4;
|
||||
uint8_t ibe:1;
|
||||
uint8_t id:1;
|
||||
} hpstateFields;
|
||||
};
|
||||
|
||||
uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
|
||||
uint64_t hpstate; // Hyperprivileged State Register
|
||||
uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
|
||||
uint64_t hintp;
|
||||
uint64_t htba; // Hyperprivileged Trap Base Address register
|
||||
union {
|
||||
uint64_t hstick_cmpr; // Hardware tick compare registers
|
||||
struct {
|
||||
uint64_t tick_cmpr:63; // Clock-tick count
|
||||
uint64_t int_dis:1; // Non-priveleged trap
|
||||
} hstick_cmprFields;
|
||||
};
|
||||
|
||||
uint64_t strandStatusReg; // Per strand status register
|
||||
uint64_t htba; // Hyperprivileged Trap Base Address register
|
||||
uint64_t hstick_cmpr; // Hardware tick compare registers
|
||||
|
||||
uint64_t strandStatusReg;// Per strand status register
|
||||
|
||||
/** Floating point misc registers. */
|
||||
union {
|
||||
uint64_t fsr; // Floating-Point State Register
|
||||
struct {
|
||||
union {
|
||||
uint64_t cexc:5; // Current excpetion
|
||||
struct {
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} cexcFields;
|
||||
};
|
||||
union {
|
||||
uint64_t aexc:5; // Accrued exception
|
||||
struct {
|
||||
uint64_t nxc:1; // Inexact
|
||||
uint64_t dzc:1; // Divide by zero
|
||||
uint64_t ufc:1; // Underflow
|
||||
uint64_t ofc:1; // Overflow
|
||||
uint64_t nvc:1; // Invalid operand
|
||||
} aexcFields;
|
||||
};
|
||||
uint64_t fcc0:2; // Floating-Point condtion codes
|
||||
uint64_t :1; // Reserved bits
|
||||
uint64_t qne:1; // Deferred trap queue not empty
|
||||
// with no queue, it should read 0
|
||||
uint64_t ftt:3; // Floating-Point trap type
|
||||
uint64_t ver:3; // Version (of the FPU)
|
||||
uint64_t :2; // Reserved bits
|
||||
uint64_t ns:1; // Nonstandard floating point
|
||||
union {
|
||||
uint64_t tem:5; // Trap Enable Mask
|
||||
struct {
|
||||
uint64_t nxm:1; // Inexact
|
||||
uint64_t dzm:1; // Divide by zero
|
||||
uint64_t ufm:1; // Underflow
|
||||
uint64_t ofm:1; // Overflow
|
||||
uint64_t nvm:1; // Invalid operand
|
||||
} temFields;
|
||||
};
|
||||
uint64_t :2; // Reserved bits
|
||||
uint64_t rd:2; // Rounding direction
|
||||
uint64_t fcc1:2; // Floating-Point condition codes
|
||||
uint64_t fcc2:2; // Floating-Point condition codes
|
||||
uint64_t fcc3:2; // Floating-Point condition codes
|
||||
uint64_t :26; // Reserved bits
|
||||
} fsrFields;
|
||||
};
|
||||
uint64_t fsr; // Floating-Point State Register
|
||||
|
||||
ASI implicitInstAsi;
|
||||
ASI implicitDataAsi;
|
||||
|
|
@ -386,8 +206,8 @@ namespace SparcISA
|
|||
|
||||
protected:
|
||||
|
||||
bool isHyperPriv() { return hpstateFields.hpriv; }
|
||||
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
|
||||
bool isHyperPriv() { return (hpstate & (1 << 2)); }
|
||||
bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
|
||||
bool isNonPriv() { return !isPriv(); }
|
||||
inline void setImplicitAsis();
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue