Merge ktlim@zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 349dbc2a39eba7fa5019c811123a643a41fdc6ff
This commit is contained in:
commit
6ee38f143e
|
@ -59,8 +59,12 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
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tc->setIntReg(16, cpuId);
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tc->setIntReg(0, cpuId);
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tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
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AlphaFault *reset = new ResetFault;
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tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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delete reset;
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}
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////////////////////////////////////////////////////////////////////////
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@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
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0xe000: rc({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(0);
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}}, IsNonSpeculative);
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}}, IsNonSpeculative, IsUnverifiable);
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0xf000: rs({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(1);
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}}, IsNonSpeculative);
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}}, IsNonSpeculative, IsUnverifiable);
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}
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#else
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format FailUnimpl {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -103,6 +103,8 @@ BaseDynInst<Impl>::initVars()
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readyRegs = 0;
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instResult.integer = 0;
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// May want to turn this into a bit vector or something.
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completed = false;
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resultReady = false;
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@ -242,31 +244,7 @@ template <class Impl>
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void
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BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
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{
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// Need to create a MemReq here so we can do a translation. This
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// will casue a TLB miss trap if necessary... not sure whether
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// that's the best thing to do or not. We don't really need the
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// MemReq otherwise, since wh64 has no functional effect.
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/*
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MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
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req->asid = asid;
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fault = cpu->translateDataWriteReq(req);
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if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
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// Record key MemReq parameters so we can generate another one
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// just like it for the timing access without calling translate()
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// again (which might mess up the TLB).
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effAddr = req->vaddr;
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physEffAddr = req->paddr;
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memReqFlags = req->flags;
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} else {
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// ignore faults & accesses to uncacheable space... treat as no-op
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effAddr = physEffAddr = MemReq::inval_addr;
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}
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storeSize = size;
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storeData = 0;
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*/
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// Not currently supported.
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}
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/**
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@ -276,22 +254,7 @@ template <class Impl>
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Fault
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BaseDynInst<Impl>::copySrcTranslate(Addr src)
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{
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/*
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MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
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req->asid = asid;
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// translate to physical address
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Fault fault = cpu->translateDataReadReq(req);
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if (fault == NoFault) {
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thread->copySrcAddr = src;
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thread->copySrcPhysAddr = req->paddr;
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} else {
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thread->copySrcAddr = 0;
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thread->copySrcPhysAddr = 0;
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}
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return fault;
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*/
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// Not currently supported.
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return NoFault;
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}
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@ -302,26 +265,7 @@ template <class Impl>
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Fault
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BaseDynInst<Impl>::copy(Addr dest)
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{
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/*
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uint8_t data[64];
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FunctionalMemory *mem = thread->mem;
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assert(thread->copySrcPhysAddr);
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MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
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req->asid = asid;
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// translate to physical address
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Fault fault = cpu->translateDataWriteReq(req);
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if (fault == NoFault) {
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Addr dest_addr = req->paddr;
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// Need to read straight from memory since we have more than 8 bytes.
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req->paddr = thread->copySrcPhysAddr;
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mem->read(req, data);
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req->paddr = dest_addr;
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mem->write(req, data);
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}
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return fault;
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*/
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// Not currently supported.
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return NoFault;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -44,12 +44,6 @@
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "sim/system.hh"
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/*
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#include "encumbered/cpu/full/bpred_update.hh"
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#include "encumbered/cpu/full/spec_memory.hh"
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#include "encumbered/cpu/full/spec_state.hh"
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#include "encumbered/mem/functional/main.hh"
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*/
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/**
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* @file
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@ -202,10 +196,9 @@ class BaseDynInst : public FastAlloc, public RefCounted
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Fault fault;
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/** The memory request. */
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// MemReqPtr req;
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Request *req;
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// Packet pkt;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** The effective virtual address (lds & stores only). */
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@ -288,21 +281,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
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void initVars();
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public:
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/**
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* @todo: Make this function work; currently it is a dummy function.
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* @param fault Last fault.
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* @param cmd Last command.
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* @param addr Virtual address of access.
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* @param p Memory accessed.
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* @param nbytes Access size.
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*/
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// void
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// trace_mem(Fault fault,
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// MemCmd cmd,
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// Addr addr,
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// void *p,
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// int nbytes);
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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@ -439,11 +417,13 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/** Returns the result of a floating point (double) instruction. */
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double readDoubleResult() { return instResult.dbl; }
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/** Records an integer register being set to a value. */
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void setIntReg(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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}
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/** Records an fp register being set to a value. */
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void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
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{
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if (width == 32)
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@ -454,16 +434,19 @@ class BaseDynInst : public FastAlloc, public RefCounted
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panic("Unsupported width!");
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}
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/** Records an fp register being set to a value. */
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void setFloatReg(const StaticInst *si, int idx, FloatReg val)
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{
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instResult.fp = val;
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}
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/** Records an fp register being set to an integer value. */
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void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
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{
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instResult.integer = val;
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}
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/** Records an fp register being set to an integer value. */
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void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
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{
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instResult.integer = val;
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@ -590,14 +573,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
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void setNextPC(uint64_t val)
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{
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nextPC = val;
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// instResult.integer = val;
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}
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/** Sets the ASID. */
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void setASID(short addr_space_id) { asid = addr_space_id; }
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void setThread(unsigned tid) { threadNumber = tid; }
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/** Sets the thread id. */
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void setTid(unsigned tid) { threadNumber = tid; }
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void setState(ImplState *state) { thread = state; }
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void setThreadState(ImplState *state) { thread = state; }
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/** Returns the thread context.
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*/
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@ -84,6 +84,8 @@ CheckerCPU::CheckerCPU(Params *p)
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#else
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process = p->process;
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#endif
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result.integer = 0;
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}
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CheckerCPU::~CheckerCPU()
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@ -92,11 +92,6 @@ Param<unsigned> commitToIEWDelay;
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Param<unsigned> renameToIEWDelay;
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Param<unsigned> issueToExecuteDelay;
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Param<unsigned> issueWidth;
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Param<unsigned> executeWidth;
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Param<unsigned> executeIntWidth;
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Param<unsigned> executeFloatWidth;
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Param<unsigned> executeBranchWidth;
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Param<unsigned> executeMemoryWidth;
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SimObjectParam<FUPool *> fuPool;
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Param<unsigned> iewToCommitDelay;
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@ -213,11 +208,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
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INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
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"to the IEW stage)"),
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INIT_PARAM(issueWidth, "Issue width"),
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INIT_PARAM(executeWidth, "Execute width"),
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INIT_PARAM(executeIntWidth, "Integer execute width"),
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INIT_PARAM(executeFloatWidth, "Floating point execute width"),
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INIT_PARAM(executeBranchWidth, "Branch execute width"),
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INIT_PARAM(executeMemoryWidth, "Memory execute width"),
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INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
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INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
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@ -344,11 +334,6 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
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params->renameToIEWDelay = renameToIEWDelay;
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params->issueToExecuteDelay = issueToExecuteDelay;
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params->issueWidth = issueWidth;
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params->executeWidth = executeWidth;
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params->executeIntWidth = executeIntWidth;
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params->executeFloatWidth = executeFloatWidth;
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params->executeBranchWidth = executeBranchWidth;
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params->executeMemoryWidth = executeMemoryWidth;
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params->fuPool = fuPool;
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params->iewToCommitDelay = iewToCommitDelay;
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|
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@ -105,11 +105,6 @@ class AlphaSimpleParams : public BaseFullCPU::Params
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unsigned renameToIEWDelay;
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unsigned issueToExecuteDelay;
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unsigned issueWidth;
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unsigned executeWidth;
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unsigned executeIntWidth;
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unsigned executeFloatWidth;
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unsigned executeBranchWidth;
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unsigned executeMemoryWidth;
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FUPool *fuPool;
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//
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|
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@ -365,11 +365,6 @@ class DefaultCommit
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*/
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unsigned renameWidth;
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/** IEW width, in instructions. Used so ROB knows how many
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* instructions to get from the IEW instruction queue.
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*/
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unsigned iewWidth;
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/** Commit width, in instructions. */
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unsigned commitWidth;
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|
|
|
@ -72,7 +72,6 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
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renameToROBDelay(params->renameToROBDelay),
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fetchToCommitDelay(params->commitToFetchDelay),
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renameWidth(params->renameWidth),
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iewWidth(params->executeWidth),
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commitWidth(params->commitWidth),
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numThreads(params->numberOfThreads),
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switchPending(false),
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|
@ -434,7 +433,7 @@ DefaultCommit<Impl>::setNextStatus()
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}
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}
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assert(squashes == squashCounter);
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squashCounter = squashes;
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|
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// If commit is currently squashing, then it will have activity for the
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// next cycle. Set its next status as active.
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|
@ -539,8 +538,6 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
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|||
|
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commitStatus[tid] = ROBSquashing;
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cpu->activityThisCycle();
|
||||
|
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++squashCounter;
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -558,8 +555,6 @@ DefaultCommit<Impl>::squashFromTC(unsigned tid)
|
|||
cpu->activityThisCycle();
|
||||
|
||||
tcSquash[tid] = false;
|
||||
|
||||
++squashCounter;
|
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}
|
||||
|
||||
template <class Impl>
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||||
|
@ -585,10 +580,12 @@ DefaultCommit<Impl>::tick()
|
|||
|
||||
if (rob->isDoneSquashing(tid)) {
|
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commitStatus[tid] = Running;
|
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--squashCounter;
|
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} else {
|
||||
DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
|
||||
"insts this cycle.\n", tid);
|
||||
rob->doSquash(tid);
|
||||
toIEW->commitInfo[tid].robSquashing = true;
|
||||
wroteToTimeBuffer = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -694,29 +691,7 @@ DefaultCommit<Impl>::commit()
|
|||
|
||||
while (threads != (*activeThreads).end()) {
|
||||
unsigned tid = *threads++;
|
||||
/*
|
||||
if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
|
||||
// Record the fault. Wait until it's empty in the ROB.
|
||||
// Then handle the trap. Ignore it if there's already a
|
||||
// trap pending as fetch will be redirected.
|
||||
fetchFault = fromFetch->fetchFault;
|
||||
fetchFaultTick = curTick + fetchTrapLatency;
|
||||
commitStatus[0] = FetchTrapPending;
|
||||
DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
|
||||
"ROB empties without squashing the fault.\n");
|
||||
fetchTrapWait = 0;
|
||||
}
|
||||
|
||||
// Fetch may tell commit to clear the trap if it's been squashed.
|
||||
if (fromFetch->clearFetchFault) {
|
||||
DPRINTF(Commit, "Received clear fetch fault signal\n");
|
||||
fetchTrapWait = 0;
|
||||
if (commitStatus[0] == FetchTrapPending) {
|
||||
DPRINTF(Commit, "Clearing fault from fetch\n");
|
||||
commitStatus[0] = Running;
|
||||
}
|
||||
}
|
||||
*/
|
||||
// Not sure which one takes priority. I think if we have
|
||||
// both, that's a bad sign.
|
||||
if (trapSquash[tid] == true) {
|
||||
|
@ -744,8 +719,6 @@ DefaultCommit<Impl>::commit()
|
|||
|
||||
commitStatus[tid] = ROBSquashing;
|
||||
|
||||
++squashCounter;
|
||||
|
||||
// If we want to include the squashing instruction in the squash,
|
||||
// then use one older sequence number.
|
||||
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
|
||||
|
|
|
@ -515,7 +515,7 @@ DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|||
|
||||
// Check ROB squash signals from commit.
|
||||
if (fromCommit->commitInfo[tid].robSquashing) {
|
||||
DPRINTF(Decode, "[tid:%]: ROB is still squashing.\n",tid);
|
||||
DPRINTF(Decode, "[tid:%u]: ROB is still squashing.\n", tid);
|
||||
|
||||
// Continue to squash.
|
||||
decodeStatus[tid] = Squashing;
|
||||
|
|
|
@ -817,7 +817,7 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|||
|
||||
// Check ROB squash signals from commit.
|
||||
if (fromCommit->commitInfo[tid].robSquashing) {
|
||||
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid);
|
||||
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
|
||||
|
||||
// Continue to squash.
|
||||
fetchStatus[tid] = Squashing;
|
||||
|
@ -984,11 +984,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
|||
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
|
||||
next_PC,
|
||||
inst_seq, cpu);
|
||||
instruction->setThread(tid);
|
||||
instruction->setTid(tid);
|
||||
|
||||
instruction->setASID(tid);
|
||||
|
||||
instruction->setState(cpu->thread[tid]);
|
||||
instruction->setThreadState(cpu->thread[tid]);
|
||||
|
||||
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
|
||||
"[sn:%lli]\n",
|
||||
|
@ -1065,11 +1065,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
|
|||
next_PC,
|
||||
inst_seq, cpu);
|
||||
instruction->setPredTarg(next_PC + instSize);
|
||||
instruction->setThread(tid);
|
||||
instruction->setTid(tid);
|
||||
|
||||
instruction->setASID(tid);
|
||||
|
||||
instruction->setState(cpu->thread[tid]);
|
||||
instruction->setThreadState(cpu->thread[tid]);
|
||||
|
||||
instruction->traceData = NULL;
|
||||
|
||||
|
|
|
@ -261,6 +261,9 @@ class DefaultIEW
|
|||
/** Processes inputs and changes state accordingly. */
|
||||
void checkSignalsAndUpdate(unsigned tid);
|
||||
|
||||
/** Removes instructions from rename from a thread's instruction list. */
|
||||
void emptyRenameInsts(unsigned tid);
|
||||
|
||||
/** Sorts instructions coming from rename into lists separated by thread. */
|
||||
void sortInsts();
|
||||
|
||||
|
@ -390,11 +393,6 @@ class DefaultIEW
|
|||
/** Width of issue, in instructions. */
|
||||
unsigned issueWidth;
|
||||
|
||||
/** Width of execute, in instructions. Might make more sense to break
|
||||
* down into FP vs int.
|
||||
*/
|
||||
unsigned executeWidth;
|
||||
|
||||
/** Index into queue of instructions being written back. */
|
||||
unsigned wbNumInst;
|
||||
|
||||
|
|
|
@ -52,7 +52,6 @@ DefaultIEW<Impl>::DefaultIEW(Params *params)
|
|||
issueToExecuteDelay(params->issueToExecuteDelay),
|
||||
issueReadWidth(params->issueWidth),
|
||||
issueWidth(params->issueWidth),
|
||||
executeWidth(params->executeWidth),
|
||||
numThreads(params->numberOfThreads),
|
||||
switchedOut(false)
|
||||
{
|
||||
|
@ -456,16 +455,7 @@ DefaultIEW<Impl>::squash(unsigned tid)
|
|||
skidBuffer[tid].pop();
|
||||
}
|
||||
|
||||
while (!insts[tid].empty()) {
|
||||
if (insts[tid].front()->isLoad() ||
|
||||
insts[tid].front()->isStore() ) {
|
||||
toRename->iewInfo[tid].dispatchedToLSQ++;
|
||||
}
|
||||
|
||||
toRename->iewInfo[tid].dispatched++;
|
||||
|
||||
insts[tid].pop();
|
||||
}
|
||||
emptyRenameInsts(tid);
|
||||
}
|
||||
|
||||
template<class Impl>
|
||||
|
@ -799,10 +789,12 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|||
}
|
||||
|
||||
if (fromCommit->commitInfo[tid].robSquashing) {
|
||||
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
|
||||
DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
|
||||
|
||||
dispatchStatus[tid] = Squashing;
|
||||
|
||||
emptyRenameInsts(tid);
|
||||
wroteToTimeBuffer = true;
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -851,6 +843,22 @@ DefaultIEW<Impl>::sortInsts()
|
|||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
|
||||
{
|
||||
while (!insts[tid].empty()) {
|
||||
if (insts[tid].front()->isLoad() ||
|
||||
insts[tid].front()->isStore() ) {
|
||||
toRename->iewInfo[tid].dispatchedToLSQ++;
|
||||
}
|
||||
|
||||
toRename->iewInfo[tid].dispatched++;
|
||||
|
||||
insts[tid].pop();
|
||||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
DefaultIEW<Impl>::wakeCPU()
|
||||
|
|
|
@ -1206,7 +1206,7 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
|
|||
}
|
||||
|
||||
DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
|
||||
" Adding to front of list.", tid);
|
||||
" Adding to front of list.\n", tid);
|
||||
|
||||
serializeInst[tid] = NULL;
|
||||
|
||||
|
|
Loading…
Reference in a new issue