Fixes for checker. The RC/RS instructions check the interrupt flag, which isn't verifiable by the checker.
src/arch/alpha/isa/decoder.isa: src/cpu/checker/cpu.cc: Fixes for checker. --HG-- extra : convert_revision : b0ec8f3c4a10453a567cd6691283fc498403795e
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@ -659,11 +659,11 @@ decode OPCODE default Unknown::unknown() {
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0xe000: rc({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(0);
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}}, IsNonSpeculative);
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}}, IsNonSpeculative, IsUnverifiable);
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0xf000: rs({{
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Ra = xc->readIntrFlag();
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xc->setIntrFlag(1);
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}}, IsNonSpeculative);
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}}, IsNonSpeculative, IsUnverifiable);
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}
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#else
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format FailUnimpl {
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@ -84,6 +84,8 @@ CheckerCPU::CheckerCPU(Params *p)
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#else
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process = p->process;
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#endif
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result.integer = 0;
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}
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CheckerCPU::~CheckerCPU()
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