First cut at full blown SPARC faults. There are a few details that are missing.
--HG-- extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895
This commit is contained in:
Gabe Black
parent
67b9a2ebd8
commit
63bbc8929d
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@ -33,6 +33,7 @@
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/types.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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@ -269,25 +270,132 @@ template<> SparcFaultBase::FaultVals
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#endif
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler. It will need to be expanded to include the state machine in
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* the manual. Right now it assumes that traps will always be to the
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* privileged level.
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* This causes the thread context to enter RED state. This causes the side
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* effects which go with entering RED state because of a trap.
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*/
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void doNormalFault(ThreadContext *tc, TrapType tt)
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void enterREDState(ThreadContext *tc)
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{
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uint64_t TL = tc->readMiscReg(MISCREG_TL);
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uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
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uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
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uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
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uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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uint64_t GL = tc->readMiscReg(MISCREG_GL);
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uint64_t PC = tc->readPC();
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uint64_t NPC = tc->readNextPC();
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//@todo Disable the mmu?
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//@todo Disable watchpoints?
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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//HPSTATE.red = 1
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HPSTATE |= (1 << 5);
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//HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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}
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/**
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* This sets everything up for a RED state trap except for actually jumping to
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* the handler.
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*/
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void doREDFault(ThreadContext *tc, TrapType tt)
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{
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MiscReg TL = tc->readMiscReg(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg PC = tc->readPC();
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MiscReg NPC = tc->readNextPC();
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TL++;
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//set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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//set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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//set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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//set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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//set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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//Write back TSTATE
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tc->setMiscReg(MISCREG_TSTATE, TSTATE);
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//set TPC to PC
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tc->setMiscReg(MISCREG_TPC, PC);
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//set TNPC to NPC
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tc->setMiscReg(MISCREG_TNPC, NPC);
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//set HTSTATE.hpstate to hpstate
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tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
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//TT = trap type;
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tc->setMiscReg(MISCREG_TT, tt);
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//Update GL
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tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
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//set PSTATE.mm to 00
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//set PSTATE.pef to 1
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PSTATE |= (1 << 4);
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//set PSTATE.am to 0
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PSTATE &= ~(1 << 3);
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//set PSTATE.priv to 0
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PSTATE &= ~(1 << 2);
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//set PSTATE.ie to 0
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PSTATE &= ~(1 << 1);
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//set PSTATE.cle to 0
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PSTATE &= ~(1 << 9);
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//PSTATE.tle is unchanged
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//XXX Where is the tct bit?
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//set PSTATE.tct to 0
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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//set HPSTATE.red to 1
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HPSTATE |= (1 << 5);
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//set HPSTATE.hpriv to 1
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HPSTATE |= (1 << 2);
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//set HPSTATE.ibe to 0
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HPSTATE &= ~(1 << 10);
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//set HPSTATE.tlz to 0
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HPSTATE &= ~(1 << 0);
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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bool changedCWP = true;
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if(tt == 0x24)
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CWP++;
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else if(0x80 <= tt && tt <= 0xbf)
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CWP += (CANSAVE + 2);
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else if(0xc0 <= tt && tt <= 0xff)
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CWP--;
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else
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changedCWP = false;
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if(changedCWP)
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{
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CWP = (CWP + NWindows) % NWindows;
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tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
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}
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}
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler.
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*/
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void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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{
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MiscReg TL = tc->readMiscReg(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
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MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
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MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
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MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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MiscReg GL = tc->readMiscReg(MISCREG_GL);
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MiscReg PC = tc->readPC();
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MiscReg NPC = tc->readNextPC();
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//Increment the trap level
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TL++;
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@ -321,10 +429,10 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
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tc->setMiscReg(MISCREG_TT, tt);
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//Update the global register level
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if(1/*We're delivering the trap in priveleged mode*/)
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tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
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if(!gotoHpriv)
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tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
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else
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tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
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tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
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//PSTATE.mm is unchanged
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//PSTATE.pef = whether or not an fpu is present
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@ -333,7 +441,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
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PSTATE |= (1 << 4);
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//PSTATE.am = 0
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PSTATE &= ~(1 << 3);
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if(1/*We're delivering the trap in priveleged mode*/)
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if(!gotoHpriv)
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{
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//PSTATE.priv = 1
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PSTATE |= (1 << 2);
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@ -354,7 +462,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
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//XXX Where exactly is this field?
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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if(0/*We're delivering the trap in hyperprivileged mode*/)
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if(gotoHpriv)
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{
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//HPSTATE.red = 0
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HPSTATE &= ~(1 << 5);
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@ -383,6 +491,29 @@ void doNormalFault(ThreadContext *tc, TrapType tt)
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}
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}
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void getREDVector(Addr & PC, Addr & NPC)
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{
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const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
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PC = RSTVAddr | 0xA0;
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NPC = PC + sizeof(MachInst);
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}
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void getHyperVector(Addr & PC, Addr & NPC, MiscReg TT)
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{
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Addr HTBA ;
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PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
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NPC = PC + sizeof(MachInst);
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}
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void getPrivVector(Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
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{
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Addr TBA ;
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PC = (TBA & ~mask(15)) |
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(TL > 1 ? (1 << 14) : 0) |
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((TT << 5) & mask(14));
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NPC = PC + sizeof(MachInst);
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}
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#if FULL_SYSTEM
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void SparcFaultBase::invoke(ThreadContext * tc)
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@ -390,11 +521,64 @@ void SparcFaultBase::invoke(ThreadContext * tc)
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FaultBase::invoke(tc);
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countStat()++;
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//Use the SPARC trap state machine
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//We can refer to this to see what the trap level -was-, but something
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//in the middle could change it in the regfile out from under us.
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MiscReg TL = tc->readMiscReg(MISCREG_TL);
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MiscReg TT = tc->readMiscReg(MISCREG_TT);
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MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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Addr PC, NPC;
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PrivilegeLevel current;
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if(!(PSTATE & (1 << 2)))
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current = User;
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else if(!(HPSTATE & (1 << 2)))
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current = Privileged;
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else
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current = Hyperprivileged;
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PrivilegeLevel level = getNextLevel(current);
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if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
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{
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getREDVector(PC, NPC);
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enterREDState(tc);
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doREDFault(tc, TT);
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}
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else if(TL == MaxTL)
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{
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//Do error_state somehow?
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//Probably inject a WDR fault using the interrupt mechanism.
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//What should the PC and NPC be set to?
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}
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else if(TL > MaxPTL && level == Privileged)
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{
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//guest_watchdog fault
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doNormalFault(tc, trapType(), true);
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getHyperVector(PC, NPC, 2);
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}
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else if(level == Hyperprivileged)
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{
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doNormalFault(tc, trapType(), true);
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getHyperVector(PC, NPC, trapType());
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}
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else
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{
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doNormalFault(tc, trapType(), false);
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getPrivVector(PC, NPC, trapType(), TL+1);
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}
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tc->setPC(PC);
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tc->setNextPC(NPC);
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tc->setNextNPC(NPC + sizeof(MachInst));
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}
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void PowerOnReset::invoke(ThreadContext * tc)
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{
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//First, enter RED state.
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enterREDState(tc);
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//For SPARC, when a system is first started, there is a power
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//on reset Trap which sets the processor into the following state.
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//Bits that aren't set aren't defined on startup.
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@ -426,17 +610,15 @@ void PowerOnReset::invoke(ThreadContext * tc)
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*/
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}
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#endif
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#if !FULL_SYSTEM
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#else // !FULL_SYSTEM
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void SpillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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doNormalFault(tc, trapType(), false);
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Process *p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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//XXX This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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@ -449,15 +631,15 @@ void SpillNNormal::invoke(ThreadContext *tc)
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void FillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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doNormalFault(tc, trapType(), false);
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Process * p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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//XXX This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//The adjust the PC and NPC
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//Then adjust the PC and NPC
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Addr fillStart = lp->readFillStart();
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tc->setPC(fillStart);
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tc->setNextPC(fillStart + sizeof(MachInst));
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