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more steps toward O3 SMT

Browse source 
src/arch/mips/isa/formats/fp.isa:
    Adjust for newmem
src/cpu/cpu_models.py:
    Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
    take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
    open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
    Add O3DynInst
src/cpu/o3/dyn_inst.hh:
    Use to get ISA-specific O3DynInst

--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
This commit is contained in:
Korey Sewell 2006-07-06 11:25:44 -04:00
parent f4c5609988
commit 215041215b
6 changed files with 82 additions and 56 deletions
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16
src/arch/mips/isa/formats/fp.isa
View file

@ -142,10 +142,10 @@ output exec {{
cpu->setFloatRegBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
//Write FCSR from FloatRegFile
cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
if (traceData) { traceData->setData(mips_nan); }
return true;
@ -158,12 +158,12 @@ output exec {{
fpResetCauseBits(%(CPU_exec_context)s *cpu)
{
//Read FCSR from FloatRegFile
uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
//Write FCSR from FloatRegFile
cpu->tc->setFloatRegBits(FCSR, fcsr);
cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
}
}};
@ -176,8 +176,9 @@ def template FloatingPointExecute {{
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
#if FULL_SYSTEM
fpResetCauseBits(xc);
#endif
%(op_decl)s;
%(op_rd)s;
@ -192,7 +193,10 @@ def template FloatingPointExecute {{
//----
//Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
if (!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
if (
#if FULL_SYSTEM
!fpInvalidOp((FPOp*)this, xc, Fd, traceData) &&
#endif
fault == NoFault)
{
%(op_wb)s;

16
src/cpu/cpu_models.py
View file

@ -79,18 +79,6 @@ CpuModel('OzoneCPU', 'ozone_exec.cc',
CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
'#include "cpu/checker/cpu.hh"',
{ 'CPU_exec_context': 'CheckerCPU' })
# Maybe there is a more clever way to determine ISA
# here but since the environment variable isnt passed through
# here the easiest way is this...
sub_template = 'not found'
for argument in sys.argv:
if 'ALPHA' in argument:
sub_template = 'AlphaDynInst<AlphaSimpleImpl>'
if sub_template == 'not found':
sys.exit('NO CPU_exec_context substitution defined for this ISA')
CpuModel('O3CPU', 'o3_cpu_exec.cc',
'#include "cpu/o3/isa_specific.hh"',
{ 'CPU_exec_context': sub_template })
'#include "cpu/o3/alpha/dyn_inst.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })

4
src/cpu/o3/alpha/impl.hh
View file

@ -36,6 +36,7 @@
#include "cpu/o3/alpha/params.hh"
#include "cpu/o3/cpu_policy.hh"
// Forward declarations.
template <class Impl>
class AlphaDynInst;
@ -88,7 +89,4 @@ struct AlphaSimpleImpl
/** The O3Impl to be used. */
typedef AlphaSimpleImpl O3CPUImpl;
/** The O3Impl to be used. */
typedef DynInst O3DynInst;
#endif // __CPU_O3_ALPHA_IMPL_HH__

61
src/cpu/o3/cpu.cc
View file

@ -463,14 +463,13 @@ template <class Impl>
void
FullO3CPU<Impl>::insertThread(unsigned tid)
{
DPRINTF(O3CPU,"[tid:%i] Initializing thread data");
DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
// Will change now that the PC and thread state is internal to the CPU
// and not in the ThreadContext.
#if 0
#if FULL_SYSTEM
ThreadContext *src_tc = system->threadContexts[tid];
#else
ThreadContext *src_tc = thread[tid];
ThreadContext *src_tc = tcBase(tid);
#endif
//Bind Int Regs to Rename Map
@ -490,11 +489,14 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
}
//Copy Thread Data Into RegFile
this->copyFromTC(tid);
//this->copyFromTC(tid);
//Set PC/NPC
regFile.pc[tid] = src_tc->readPC();
regFile.npc[tid] = src_tc->readNextPC();
//Set PC/NPC/NNPC
setPC(src_tc->readPC(), tid);
setNextPC(src_tc->readNextPC(), tid);
#if THE_ISA != ALPHA_ISA
setNextNPC(src_tc->readNextNPC(), tid);
#endif
src_tc->setStatus(ThreadContext::Active);
@ -503,16 +505,19 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
//Reset ROB/IQ/LSQ Entries
commit.rob->resetEntries();
iew.resetEntries();
#endif
}
template <class Impl>
void
FullO3CPU<Impl>::removeThread(unsigned tid)
{
DPRINTF(O3CPU,"[tid:%i] Removing thread data");
#if 0
//Unbind Int Regs from Rename Map
DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU.");
// Copy Thread Data From RegFile
// If thread is suspended, it might be re-allocated
//this->copyToTC(tid);
// Unbind Int Regs from Rename Map
for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
@ -520,7 +525,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
freeList.addReg(phys_reg);
}
//Unbind Float Regs from Rename Map
// Unbind Float Regs from Rename Map
for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
@ -528,27 +533,18 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
freeList.addReg(phys_reg);
}
//Copy Thread Data From RegFile
/* Fix Me:
* Do we really need to do this if we are removing a thread
* in the sense that it's finished (exiting)? If the thread is just
* being suspended we might...
*/
// this->copyToTC(tid);
//Squash Throughout Pipeline
// Squash Throughout Pipeline
fetch.squash(0,tid);
decode.squash(tid);
rename.squash(tid);
assert(iew.ldstQueue.getCount(tid) == 0);
//Reset ROB/IQ/LSQ Entries
// Reset ROB/IQ/LSQ Entries
if (activeThreads.size() >= 1) {
commit.rob->resetEntries();
iew.resetEntries();
}
#endif
}
@ -656,7 +652,7 @@ template <class Impl>
void
FullO3CPU<Impl>::suspendContext(int tid)
{
DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid);
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
unscheduleTickEvent();
_status = Idle;
/*
@ -676,27 +672,26 @@ template <class Impl>
void
FullO3CPU<Impl>::deallocateContext(int tid)
{
DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid);
/*
//Remove From Active List, if Active
list<unsigned>::iterator isActive = find(
activeThreads.begin(), activeThreads.end(), tid);
DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid);
if (isActive != activeThreads.end()) {
//Remove From Active List, if Active
list<unsigned>::iterator thread_it =
find(activeThreads.begin(), activeThreads.end(), tid);
if (thread_it != activeThreads.end()) {
DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
tid);
activeThreads.erase(isActive);
activeThreads.erase(thread_it);
removeThread(tid);
}
*/
}
template <class Impl>
void
FullO3CPU<Impl>::haltContext(int tid)
{
DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid);
DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid);
/*
//Remove From Active List, if Active
list<unsigned>::iterator isActive = find(

39
src/cpu/o3/dyn_inst.hh Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
*/
#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__
#include "cpu/o3/isa_specific.hh"
/** The O3Impl to be used. */
typedef DynInst O3DynInst;
#endif // __CPU_O3_DYN_INST_HH__

2
src/cpu/static_inst.hh
View file

@ -53,6 +53,8 @@ class Packet;
template <class Impl>
class AlphaDynInst;
//class O3DynInst;
template <class Impl>
class OzoneDynInst;