Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
This commit is contained in:
Ali Saidi
parent
ed22eb781d
commit
81a00fdcfe
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@ -551,34 +551,26 @@ void SparcFaultBase::invoke(ThreadContext * tc)
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PrivilegeLevel level = getNextLevel(current);
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if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
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{
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if(HPSTATE & (1 << 5) || TL == MaxTL - 1) {
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getREDVector(5, PC, NPC);
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doREDFault(tc, TT);
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//This changes the hpstate and pstate, so we need to make sure we
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//save the old version on the trap stack in doREDFault.
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enterREDState(tc);
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}
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else if(TL == MaxTL)
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{
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} else if(TL == MaxTL) {
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panic("Should go to error state here.. crap\n");
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//Do error_state somehow?
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//Probably inject a WDR fault using the interrupt mechanism.
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//What should the PC and NPC be set to?
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}
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else if(TL > MaxPTL && level == Privileged)
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{
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} else if(TL > MaxPTL && level == Privileged) {
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//guest_watchdog fault
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doNormalFault(tc, trapType(), true);
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getHyperVector(tc, PC, NPC, 2);
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}
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else if(level == Hyperprivileged)
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{
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} else if(level == Hyperprivileged ||
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level == Privileged && trapType() >= 384) {
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doNormalFault(tc, trapType(), true);
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getHyperVector(tc, PC, NPC, trapType());
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}
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else
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{
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} else {
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doNormalFault(tc, trapType(), false);
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getPrivVector(tc, PC, NPC, trapType(), TL+1);
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}
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@ -67,7 +67,7 @@ namespace SparcISA
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(unsigned int)(-1) :
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(1 << FrameOffsetBits) - 1;
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IntReg regGlobals[MaxGL][RegsPerFrame];
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IntReg regGlobals[MaxGL+1][RegsPerFrame];
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IntReg regSegments[2 * NWindows][RegsPerFrame];
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IntReg microRegs[NumMicroIntRegs];
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@ -526,7 +526,7 @@ decode OP default Unknown::unknown()
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0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
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//0x01 should cause an illegal instruction exception
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0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
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0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
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0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
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//0x04-0x05 should cause an illegal instruction exception
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0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
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//0x07-0x0E should cause an illegal instruction exception
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@ -1017,6 +1017,7 @@ decode OP default Unknown::unknown()
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Asi = Tstate<31:24>;
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Ccr = Tstate<39:32>;
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Gl = Tstate<42:40>;
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Hpstate = Htstate;
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NPC = Tpc;
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NNPC = Tnpc;
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Tl = Tl - 1;
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@ -32,6 +32,7 @@
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#define __ARCH_SPARC_PAGETABLE_HH__
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#include "arch/sparc/isa_traits.hh"
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#include "base/bitfield.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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@ -80,20 +81,19 @@ class PageTableEntry
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if (type == sun4u)
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entry4u = entry;
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else {
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uint64_t entry4u = 0;
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entry4u |= entry & ULL(0x8000000000000000); //valid
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entry4u |= (entry & 0x3) << 61; //size[1:0]
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entry4u |= (entry & ULL(0x4000000000000000)) >> 2; //nfo
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entry4u |= (entry & 0x1000) << 47; //ie
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//entry4u |= (entry & 0x3F00000000000000) >> 7; //soft2
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entry4u |= (entry & 0x4) << 48; //size[2]
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//diag?
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entry4u |= (entry & ULL(0x0000FFFFFFFFE000)); //paddr
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entry4u |= (entry & 0x400) >> 5; //cp
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entry4u |= (entry & 0x200) >> 5; //cv
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entry4u |= (entry & 0x800) >> 8; //e
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entry4u |= (entry & 0x100) >> 6; //p
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entry4u |= (entry & 0x40) >> 5; //w
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entry4u = 0;
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entry4u |= mbits(entry,63,63); //valid
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entry4u |= bits(entry,1,0) << 61; //size[1:0]
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entry4u |= bits(entry,62,62) << 60; //nfo
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entry4u |= bits(entry,12,12) << 59; //ie
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entry4u |= bits(entry,2,2) << 48; //size[2]
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entry4u |= mbits(entry,39,13); //paddr
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entry4u |= bits(entry,61,61) << 6;; // locked
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entry4u |= bits(entry,10,10) << 5; //cp
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entry4u |= bits(entry,9,9) << 4; //cv
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entry4u |= bits(entry,11,11) << 3; //e
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entry4u |= bits(entry,8,8) << 2; //p
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entry4u |= bits(entry,6,6) << 1; //w
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}
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}
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@ -112,30 +112,21 @@ class PageTableEntry
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const PageTableEntry &operator=(const PageTableEntry &e)
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{ populated = true; entry4u = e.entry4u; return *this; }
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bool valid() const { return entry4u & ULL(0x8000000000000000) && populated; }
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bool valid() const { return bits(entry4u,63,63) && populated; }
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uint8_t _size() const { assert(populated);
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return ((entry4u & 0x6) >> 61) |
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((entry4u & ULL(0x000080000000000)) >> 46); }
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Addr size() const { return pageSizes[_size()]; }
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bool ie() const { return entry4u >> 59 & 0x1; }
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Addr pfn() const { assert(populated);
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return entry4u >> 13 & ULL(0xFFFFFFFFFF); }
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Addr paddr() const { assert(populated);
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return entry4u & ULL(0x0000FFFFFFFFE000); }
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bool locked() const { assert(populated);
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return entry4u & 0x40; }
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bool cv() const { assert(populated);
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return entry4u & 0x10; }
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bool cp() const { assert(populated);
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return entry4u & 0x20; }
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bool priv() const { assert(populated);
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return entry4u & 0x4; }
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bool writable() const { assert(populated);
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return entry4u & 0x2; }
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bool nofault() const { assert(populated);
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return entry4u & ULL(0x1000000000000000); }
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bool sideffect() const { assert(populated);
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return entry4u & 0x8; }
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return bits(entry4u, 62,61) |
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bits(entry4u, 48,48) << 2; }
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Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
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bool ie() const { return bits(entry4u, 59,59); }
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Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
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Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
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bool locked() const { assert(populated); return bits(entry4u,6,6); }
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bool cv() const { assert(populated); return bits(entry4u,4,4); }
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bool cp() const { assert(populated); return bits(entry4u,5,5); }
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bool priv() const { assert(populated); return bits(entry4u,2,2); }
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bool writable() const { assert(populated); return bits(entry4u,1,1); }
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bool nofault() const { assert(populated); return bits(entry4u,60,60); }
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bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
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};
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struct TlbRange {
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@ -71,27 +71,32 @@ TLB::clearUsedBits()
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void
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TLB::insert(Addr va, int partition_id, int context_id, bool real,
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const PageTableEntry& PTE)
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const PageTableEntry& PTE, int entry)
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{
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MapIter i;
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TlbEntry *new_entry;
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TlbEntry *new_entry = NULL;
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int x;
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DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n",
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va, partition_id, context_id, (int)real);
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DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n",
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va, PTE.paddr(), partition_id, context_id, (int)real);
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int x = -1;
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for (x = 0; x < size; x++) {
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if (!tlb[x].valid || !tlb[x].used) {
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new_entry = &tlb[x];
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break;
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if (entry != -1) {
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assert(entry < size && entry >= 0);
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new_entry = &tlb[entry];
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} else {
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for (x = 0; x < size; x++) {
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if (!tlb[x].valid || !tlb[x].used) {
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new_entry = &tlb[x];
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break;
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}
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}
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}
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// Update the last ently if their all locked
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if (x == -1)
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x = size - 1;
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if (!new_entry)
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new_entry = &tlb[size-1];
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assert(PTE.valid());
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new_entry->range.va = va;
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@ -152,10 +157,11 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id)
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DPRINTF(TLB, "TLB: No valid entry found\n");
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return NULL;
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}
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DPRINTF(TLB, "TLB: Valid entry found\n");
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// Mark the entries used bit and clear other used bits in needed
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t = i->second;
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DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
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t->pte.size());
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if (!t->used) {
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t->used = true;
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usedEntries++;
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@ -169,6 +175,18 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id)
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return t;
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}
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void
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TLB::dumpAll()
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{
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for (int x = 0; x < size; x++) {
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if (tlb[x].valid) {
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DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
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x, tlb[x].range.partitionId, tlb[x].range.contextId,
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tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
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tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
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}
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}
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}
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void
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TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
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@ -285,9 +303,14 @@ TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
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sfsr |= 1 << 6;
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sfsr |= ft << 7;
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sfsr |= asi << 16;
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tc->setMiscReg(reg, sfsr);
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tc->setMiscRegWithEffect(reg, sfsr);
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}
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void
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TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
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{
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tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
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}
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void
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ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
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@ -298,6 +321,12 @@ ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
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TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
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}
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void
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ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
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{
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TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
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}
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void
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DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
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bool se, FaultTypes ft, int asi)
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@ -305,9 +334,16 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
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DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
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a, (int)write, ct, ft, asi);
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TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
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tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
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tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
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}
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void
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DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
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{
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TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
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}
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Fault
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ITB::translate(RequestPtr &req, ThreadContext *tc)
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|
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@ -349,7 +385,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
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}
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// If the asi is unaligned trap
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if (vaddr & 0x7) {
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if (vaddr & req->getSize()-1) {
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writeSfsr(tc, false, ct, false, OtherFault, asi);
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return new MemAddressNotAligned;
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}
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@ -385,8 +421,9 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
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return new InstructionAccessException;
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}
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req->setPaddr(e->pte.paddr() & ~e->pte.size() |
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req->getVaddr() & e->pte.size());
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req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
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req->getVaddr() & e->pte.size()-1 );
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DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
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return NoFault;
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}
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@ -456,20 +493,12 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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return new DataAccessException;
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}
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}
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|
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// If the asi is unaligned trap
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if (vaddr & size-1) {
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writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
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return new MemAddressNotAligned;
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}
|
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|
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if (addr_mask)
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vaddr = vaddr & VAddrAMask;
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|
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if (!validVirtualAddress(vaddr, addr_mask)) {
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writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
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return new DataAccessException;
|
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} else if (hpriv) {
|
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if (asi == ASI_P) {
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ct = Primary;
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context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
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goto continueDtbFlow;
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}
|
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}
|
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|
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if (!implicit) {
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|
|
@ -499,6 +528,22 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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panic("Accessing ASI %#X. Should we?\n", asi);
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}
|
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|
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continueDtbFlow:
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// If the asi is unaligned trap
|
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if (vaddr & size-1) {
|
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writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
|
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return new MemAddressNotAligned;
|
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}
|
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|
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if (addr_mask)
|
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vaddr = vaddr & VAddrAMask;
|
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|
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if (!validVirtualAddress(vaddr, addr_mask)) {
|
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writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
|
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return new DataAccessException;
|
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}
|
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|
||||
|
||||
if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
|
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real = true;
|
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context = 0;
|
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|
|
@ -542,8 +587,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
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return new DataAccessException;
|
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}
|
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|
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req->setPaddr(e->pte.paddr() & ~e->pte.size() |
|
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req->getVaddr() & e->pte.size());
|
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req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
|
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req->getVaddr() & e->pte.size()-1);
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DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
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return NoFault;
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/** Normal flow ends here. */
|
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|
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|
|
@ -664,12 +710,28 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
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assert(va == 0);
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
|
||||
break;
|
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case ASI_SPARC_ERROR_STATUS_REG:
|
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warn("returning 0 for SPARC ERROR regsiter read\n");
|
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pkt->set(0);
|
||||
break;
|
||||
case ASI_HYP_SCRATCHPAD:
|
||||
case ASI_SCRATCHPAD:
|
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pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
|
||||
break;
|
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case ASI_IMMU:
|
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switch (va) {
|
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case 0x30:
|
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
|
||||
break;
|
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default:
|
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goto doMmuReadError;
|
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}
|
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break;
|
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case ASI_DMMU:
|
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switch (va) {
|
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case 0x30:
|
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pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
|
||||
break;
|
||||
case 0x80:
|
||||
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
|
||||
break;
|
||||
|
|
@ -693,6 +755,14 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
|
|||
Addr va = pkt->getAddr();
|
||||
ASI asi = (ASI)pkt->req->getAsi();
|
||||
|
||||
Addr ta_insert;
|
||||
Addr va_insert;
|
||||
Addr ct_insert;
|
||||
int part_insert;
|
||||
int entry_insert = -1;
|
||||
bool real_insert;
|
||||
PageTableEntry pte;
|
||||
|
||||
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
|
||||
(uint32_t)asi, va, data);
|
||||
|
||||
|
|
@ -774,8 +844,47 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
|
|||
case ASI_SCRATCHPAD:
|
||||
tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
|
||||
break;
|
||||
case ASI_IMMU:
|
||||
switch (va) {
|
||||
case 0x30:
|
||||
tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
|
||||
break;
|
||||
default:
|
||||
goto doMmuWriteError;
|
||||
}
|
||||
break;
|
||||
case ASI_ITLB_DATA_ACCESS_REG:
|
||||
entry_insert = bits(va, 8,3);
|
||||
case ASI_ITLB_DATA_IN_REG:
|
||||
assert(entry_insert != -1 || mbits(va,10,9) == va);
|
||||
ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
|
||||
va_insert = mbits(ta_insert, 63,13);
|
||||
ct_insert = mbits(ta_insert, 12,0);
|
||||
part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
|
||||
real_insert = bits(va, 9,9);
|
||||
pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
|
||||
PageTableEntry::sun4u);
|
||||
tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
|
||||
pte, entry_insert);
|
||||
break;
|
||||
case ASI_DTLB_DATA_ACCESS_REG:
|
||||
entry_insert = bits(va, 8,3);
|
||||
case ASI_DTLB_DATA_IN_REG:
|
||||
assert(entry_insert != -1 || mbits(va,10,9) == va);
|
||||
ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
|
||||
va_insert = mbits(ta_insert, 63,13);
|
||||
ct_insert = mbits(ta_insert, 12,0);
|
||||
part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
|
||||
real_insert = bits(va, 9,9);
|
||||
pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
|
||||
PageTableEntry::sun4u);
|
||||
insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
|
||||
break;
|
||||
case ASI_DMMU:
|
||||
switch (va) {
|
||||
case 0x30:
|
||||
tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
|
||||
break;
|
||||
case 0x80:
|
||||
tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@ class TLB : public SimObject
|
|||
|
||||
/** Insert a PTE into the TLB. */
|
||||
void insert(Addr vpn, int partition_id, int context_id, bool real,
|
||||
const PageTableEntry& PTE);
|
||||
const PageTableEntry& PTE, int entry = -1);
|
||||
|
||||
/** Given an entry id, read that tlb entries' tag. */
|
||||
uint64_t TagRead(int entry);
|
||||
|
|
@ -114,9 +114,13 @@ class TLB : public SimObject
|
|||
void TLB::clearUsedBits();
|
||||
|
||||
|
||||
void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
|
||||
|
||||
public:
|
||||
TLB(const std::string &name, int size);
|
||||
|
||||
void dumpAll();
|
||||
|
||||
// Checkpointing
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
|
@ -133,6 +137,8 @@ class ITB : public TLB
|
|||
private:
|
||||
void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
|
||||
bool se, FaultTypes ft, int asi);
|
||||
void writeTagAccess(ThreadContext *tc, Addr va, int context);
|
||||
friend class DTB;
|
||||
};
|
||||
|
||||
class DTB : public TLB
|
||||
|
|
@ -149,6 +155,8 @@ class DTB : public TLB
|
|||
private:
|
||||
void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
|
||||
bool se, FaultTypes ft, int asi);
|
||||
void writeTagAccess(ThreadContext *tc, Addr va, int context);
|
||||
|
||||
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -393,12 +393,13 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
|
||||
diffCleanwin = true;
|
||||
|
||||
if (diffPC || diffCC || diffInst || diffRegs || diffTpc ||
|
||||
if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
|
||||
diffTnpc || diffTstate || diffTt || diffHpstate ||
|
||||
diffHtstate || diffHtba || diffPstate || diffY ||
|
||||
diffCcr || diffTl || diffGl || diffAsi || diffPil ||
|
||||
diffCwp || diffCansave || diffCanrestore ||
|
||||
diffOtherwin || diffCleanwin) {
|
||||
diffOtherwin || diffCleanwin)
|
||||
&& !((staticInst->machInst & 0xE1F80000) == 0xE1F80000)) {
|
||||
outs << "Differences found between M5 and Legion:";
|
||||
if (diffPC)
|
||||
outs << " [PC]";
|
||||
|
|
@ -570,6 +571,9 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
<< endl;*/
|
||||
}
|
||||
}
|
||||
thread->getITBPtr()->dumpAll();
|
||||
thread->getDTBPtr()->dumpAll();
|
||||
|
||||
diffcount++;
|
||||
if (diffcount > 3)
|
||||
fatal("Differences found between Legion and M5\n");
|
||||
|
|
|
|||
Loading…
Reference in a new issue