Add support for mmapped iprs to atomic cpu

src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115

src/arch/SConscript

@@ -53,6 +53,7 @@ isa_switch_hdrs = Split('''
 	isa_traits.hh
 	kernel_stats.hh
         locked_mem.hh
+        mmaped_ipr.hh
 	process.hh
 	regfile.hh
 	remote_gdb.hh

src/arch/alpha/mmaped_ipr.hh

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
+#define __ARCH_ALPHA_MMAPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "mem/packet.hh"
+
+
+namespace AlphaISA
+{
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+    panic("No handleIprRead implementation in Alpha\n");
+}
+
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+    panic("No handleIprWrite implementation in Alpha\n");
+}
+
+
+} // namespace AlphaISA
+
+#endif

src/arch/mips/mmaped_ipr.hh

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
+#define __ARCH_MIPS_MMAPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "mem/packet.hh"
+
+
+namespace MipsISA
+{
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+    panic("No implementation for handleIprRead in MIPS\n");
+}
+
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+    panic("No implementation for handleIprWrite in MIPS\n");
+}
+
+
+} // namespace MipsISA
+
+#endif

src/arch/sparc/asi.hh

@@ -35,6 +35,7 @@
 namespace SparcISA
 {
     enum ASI {
+        ASI_IMPLICIT = 0x00,
         /* Priveleged ASIs */
         //0x00-0x03 implementation dependent
         ASI_NUCLEUS = 0x4,
@@ -242,7 +243,6 @@ namespace SparcISA
         ASI_BLK_SL = 0xF9,
         ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
         //0xFA-0xFF implementation dependent
-        ASI_IMPLICIT = 0xFF,
         MAX_ASI = 0xFF
     };
 

src/arch/sparc/miscregfile.hh

@@ -32,7 +32,6 @@
 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
 #define __ARCH_SPARC_MISCREGFILE_HH__
 
-#include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/types.hh"

src/arch/sparc/mmaped_ipr.hh

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
+#define __ARCH_SPARC_MMAPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+#include "arch/sparc/tlb.hh"
+
+
+namespace SparcISA
+{
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+    return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
+}
+
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+    return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
+}
+
+
+} // namespace SparcISA
+
+#endif

src/arch/sparc/tlb.cc

@@ -508,13 +508,31 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     req->setPaddr(e->pte.paddr() & ~e->pte.size() |
                   req->getVaddr() & e->pte.size());
     return NoFault;
-    /*** End of normal Path ***/
+    /** Normal flow ends here. */
 
-handleMmuRegAccess:
 handleScratchRegAccess:
-    panic("How are we ever going to deal with this?\n");
+    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
+        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+        return new DataAccessException;
+    }
+handleMmuRegAccess:
+    req->setMmapedIpr(true);
+    req->setPaddr(req->getVaddr());
+    return NoFault;
 };
 
+Tick
+DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+{
+    panic("need to implement DTB::doMmuRegRead()\n");
+}
+
+Tick
+DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+{
+    panic("need to implement DTB::doMmuRegWrite()\n");
+}
+
 void
 TLB::serialize(std::ostream &os)
 {

src/arch/sparc/tlb.hh

@@ -38,6 +38,7 @@
 #include "sim/sim_object.hh"
 
 class ThreadContext;
+class Packet;
 
 namespace SparcISA
 {
@@ -142,6 +143,8 @@ class DTB : public TLB
     }
 
     Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
 
   private:
     void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,

src/cpu/simple/atomic.cc

@@ -29,6 +29,7 @@
  */
 
 #include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
@@ -285,7 +286,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     if (fault == NoFault) {
         pkt->reinitFromRequest();
 
-        dcache_latency = dcachePort.sendAtomic(pkt);
+        if (req->isMmapedIpr())
+            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
+        else
+            dcache_latency = dcachePort.sendAtomic(pkt);
         dcache_access = true;
 
         assert(pkt->result == Packet::Success);
@@ -372,11 +376,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         }
 
         if (do_access) {
-            data = htog(data);
             pkt->reinitFromRequest();
             pkt->dataStatic(&data);
 
-            dcache_latency = dcachePort.sendAtomic(pkt);
+            if (req->isMmapedIpr()) {
+                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
+            } else {
+                data = htog(data);
+                dcache_latency = dcachePort.sendAtomic(pkt);
+            }
             dcache_access = true;
 
             assert(pkt->result == Packet::Success);

src/mem/request.hh

@@ -49,26 +49,28 @@ class Request;
 typedef Request* RequestPtr;
 
 
+/** ASI information for this request if it exsits. */
+const uint32_t ASI_BITS         = 0x000FF;
 /** The request is a Load locked/store conditional. */
-const unsigned LOCKED		= 0x001;
+const uint32_t LOCKED		= 0x00100;
 /** The virtual address is also the physical address. */
-const unsigned PHYSICAL		= 0x002;
+const uint32_t PHYSICAL		= 0x00200;
 /** The request is an ALPHA VPTE pal access (hw_ld). */
-const unsigned VPTE		= 0x004;
+const uint32_t VPTE		= 0x00400;
 /** Use the alternate mode bits in ALPHA. */
-const unsigned ALTMODE		= 0x008;
+const uint32_t ALTMODE		= 0x00800;
 /** The request is to an uncacheable address. */
-const unsigned UNCACHEABLE	= 0x010;
+const uint32_t UNCACHEABLE	= 0x01000;
 /** The request should not cause a page fault. */
-const unsigned NO_FAULT         = 0x020;
+const uint32_t NO_FAULT         = 0x02000;
 /** The request should be prefetched into the exclusive state. */
-const unsigned PF_EXCLUSIVE	= 0x100;
+const uint32_t PF_EXCLUSIVE	= 0x10000;
 /** The request should be marked as LRU. */
-const unsigned EVICT_NEXT	= 0x200;
+const uint32_t EVICT_NEXT	= 0x20000;
 /** The request should ignore unaligned access faults */
-const unsigned NO_ALIGN_FAULT   = 0x400;
+const uint32_t NO_ALIGN_FAULT   = 0x40000;
 /** The request was an instruction read. */
-const unsigned INST_READ        = 0x800;
+const uint32_t INST_READ        = 0x80000;
 
 class Request
 {
@@ -95,10 +97,9 @@ class Request
 
     /** The address space ID. */
     int asid;
-    /** The ASI is any -- SPARC ONLY */
-    int asi;
+
     /** This request is to a memory mapped register. */
-    bool mmapedReg;
+    bool mmapedIpr;
 
     /** The virtual address of the request. */
     Addr vaddr;
@@ -169,6 +170,7 @@ class Request
         validAsidVaddr = false;
         validPC = false;
         validScResult = false;
+        mmapedIpr = false;
     }
 
     /**
@@ -186,6 +188,7 @@ class Request
         validAsidVaddr = true;
         validPC = true;
         validScResult = false;
+        mmapedIpr = false;
     }
 
     /** Set just the physical address.  This should only be used to
@@ -221,14 +224,17 @@ class Request
     int getAsid() { assert(validAsidVaddr); return asid; }
 
     /** Accessor function for asi.*/
-    int getAsi() { assert(validAsidVaddr); return asi; }
-    /** Accessor function for asi.*/
-    void setAsi(int a) { assert(validAsidVaddr); asi = a; }
+    uint8_t getAsi() { assert(validAsidVaddr); return flags & ASI_BITS; }
 
     /** Accessor function for asi.*/
-    bool getMmapedReg() { assert(validPaddr); return mmapedReg; }
+    void setAsi(uint8_t a)
+    { assert(validAsidVaddr); flags = (flags & ~ASI_BITS) | a; }
+
     /** Accessor function for asi.*/
-    void setMmapedReg(bool r) { assert(validPaddr); mmapedReg = r; }
+    bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; }
+
+    /** Accessor function for asi.*/
+    void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; }
 
     /** Accessor function to check if sc result is valid. */
     bool scResultValid() { return validScResult; }