Commit graph

61 commits

Author SHA1 Message Date
Nilay Vaish
0d6a6dfd7b stats: updates due to recent changesets including d0934b57735a 2015-09-15 08:14:09 -05:00
Nilay Vaish
66941163e5 stats: updates due to recent changes. 2015-08-30 12:24:19 -05:00
Joel Hestness
93c173a95e stats: Bump for MessageBuffer, cache latency changes 2015-08-14 01:19:34 -05:00
Andreas Hansson
25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00
Steve Reinhardt
0cf36d9409 stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
2015-04-22 20:22:29 -07:00
Nilay Vaish
99fb8f8140 stats: changes to due to recent set of patches 2015-03-09 09:39:09 -05:00
Andreas Hansson
8909843a76 stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 05:04:20 -05:00
Andreas Hansson
de162ad968 tests: Remove deprecated InOrderCPU tests
This patch removes the three MIPS and SPARC regressions that use the
deprecated InOrderCPU.

This is the first step in completely removing the code from the tree,
avoiding confusion, and focusing all development efforts on the
MinorCPU. Brave new world.
2015-01-20 08:12:02 -05:00
Andreas Hansson
df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00
Nilay Vaish
a75e27b4a6 stats: updates due to changes to ruby 2014-11-06 05:42:21 -06:00
Nilay Vaish
d2a0f60b69 stats: updates due to previous mmap and exit_group patches. 2014-10-20 16:48:19 -05:00
Nilay Vaish
1efe42fa97 stats: updates due to changes to x86, stale configs. 2014-10-11 16:18:51 -05:00
Andreas Hansson
0746e92cd3 stats: Add DRAM power statistics to reference output 2014-10-09 17:52:13 -04:00
Andreas Hansson
c4e91289ae stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00
Andreas Hansson
a217eba078 stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
2014-09-03 07:42:59 -04:00
Nilay Vaish
fa1fbcf020 stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
2014-09-01 16:55:52 -05:00
Steve Reinhardt
5b08e211ab stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
2014-06-22 14:33:09 -07:00
Nilay Vaish
0aaa7d10d8 stats: changes due to o3 cpu and ruby message buffer patches 2014-05-23 06:07:02 -05:00
Andreas Hansson
57e5401d95 stats: Bump stats for the fixes, and mostly DRAM controller changes 2014-05-09 18:58:50 -04:00
Andreas Hansson
8b4b1dcb86 stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
2014-03-23 11:12:19 -04:00
Nilay Vaish
83d09ee215 stats: updates due to changes to ruby config scripts
These updates to ruby regression stats are due to renaming piobus to iobus
and dropping piobus in the se mode.
2014-03-20 09:16:35 -05:00
Nilay Vaish
53f697a616 stats: updates due to c0db268f811b 2014-02-24 20:50:06 -06:00
Nilay Vaish
5abbb84f02 stats: updates due to branch predictor warming 2014-02-16 11:40:34 -06:00
Ali Saidi
f3585c841e stats: update stats for cache occupancy and clock domain changes 2014-01-24 15:29:33 -06:00
Nilay Vaish
fc6d1f3399 stats: updates due to changes to ruby 2014-01-10 16:19:58 -06:00
Nilay Vaish
2823982a3c stats: updates due to changes to ticksToCycles() 2013-11-26 17:05:25 -06:00
Andreas Hansson
ccfdc533b9 stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
2013-11-01 11:56:34 -04:00
Steve Reinhardt
10e6450120 test: update stats
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
2013-10-16 10:44:12 -04:00
Steve Reinhardt
fbc1feb39a tests: update reference outputs
Apparently only stats.txt was updated the last time, so
this changeset updates other reference output files
(config.ini, simout, simerr, ruby.stats) so that
test output diffs should not be cluttered with irrelevant
changes.  There are a few stats.txt updates too, but
they are in the minority.
2013-09-28 15:25:17 -04:00
Nilay Vaish
ff87a0dd9c stats: ruby: updates due to recent changes. 2013-09-06 16:21:36 -05:00
Andreas Hansson
b63631536d stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00
Andreas Hansson
5a15909bac stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
2013-06-27 05:49:51 -04:00
Nilay Vaish
247e4e9ab4 stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
2013-06-10 06:46:20 -05:00
Andreas Hansson
74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00
Nilay Vaish
5b49c3d255 stats: updates statistics for ruby regressions 2013-05-21 11:32:57 -05:00
Nilay Vaish
4646369afd regressions: update due to cache latency fix 2013-03-27 18:36:21 -05:00
Nilay Vaish
04fe6b486a regressions: updates to config.ini for ruby tests 2013-03-22 17:21:25 -05:00
Nilay Vaish
d24d5446c5 regressions: stats updates due to no physmem in ruby 2013-03-06 21:57:10 -06:00
Andreas Hansson
cb9e208a4c stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00
Andreas Hansson
fce3433b2e stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
2013-01-31 07:49:16 -05:00
Nilay Vaish
9bc132e473 regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
2013-01-24 12:29:00 -06:00
Nilay Vaish
7fdcfdf08b regressions: update stats due to changes in ruby obj hierarchy 2013-01-14 10:20:16 -06:00
Ali Saidi
9f15510c2c stats: update stats for previous changes. 2013-01-07 13:05:54 -05:00
Ali Saidi
1dbf9bb4ca update stats for preceeding changes 2012-11-02 11:50:06 -05:00
Andreas Hansson
10b70d5452 stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
2012-10-30 09:35:32 -04:00
Andreas Hansson
8fe556338d stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00
Andreas Hansson
d52adc4eb6 Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00
Andreas Hansson
54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00
Nilay Vaish
0de0ce106a Regression Tests: Update statistics 2012-10-02 14:35:46 -05:00
Andreas Hansson
ae1652b813 Stats: Remove the reference stats that are no longer present
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
2012-09-13 08:02:55 -04:00