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stats: updates due to c0db268f811b

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This commit is contained in:
Nilay Vaish 2014-02-24 20:50:06 -06:00
parent 8504b079b8
commit 53f697a616
26 changed files with 305 additions and 101 deletions
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20
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/linux/hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -282,6 +294,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -436,7 +451,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000139 # Nu
sim_ticks 138616 # Number of ticks simulated
final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 22907 # Simulator instruction rate (inst/s)
host_op_rate 22905 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 496843 # Simulator tick rate (ticks/s)
host_mem_usage 174712 # Number of bytes of host memory used
host_seconds 0.28 # Real time elapsed on the host
host_inst_rate 14698 # Simulator instruction rate (inst/s)
host_op_rate 14697 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 318804 # Simulator tick rate (ticks/s)
host_mem_usage 174728 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

20
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/linux/hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -267,6 +279,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -420,7 +435,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000118 # Nu
sim_ticks 117611 # Number of ticks simulated
final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 22851 # Simulator instruction rate (inst/s)
host_op_rate 22850 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 420529 # Simulator tick rate (ticks/s)
host_mem_usage 177976 # Number of bytes of host memory used
host_seconds 0.28 # Real time elapsed on the host
host_inst_rate 21881 # Simulator instruction rate (inst/s)
host_op_rate 21879 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 402676 # Simulator tick rate (ticks/s)
host_mem_usage 177980 # Number of bytes of host memory used
host_seconds 0.29 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/linux/hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -278,6 +290,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -433,7 +448,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000114 # Nu
sim_ticks 113627 # Number of ticks simulated
final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 33215 # Simulator instruction rate (inst/s)
host_op_rate 33212 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 590518 # Simulator tick rate (ticks/s)
host_mem_usage 174836 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 28822 # Simulator instruction rate (inst/s)
host_op_rate 28819 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 512426 # Simulator tick rate (ticks/s)
host_mem_usage 175880 # Number of bytes of host memory used
host_seconds 0.22 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/linux/hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -302,6 +314,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -396,7 +411,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000093 # Nu
sim_ticks 93341 # Number of ticks simulated
final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 36927 # Simulator instruction rate (inst/s)
host_op_rate 36923 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 539288 # Simulator tick rate (ticks/s)
host_mem_usage 175784 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_inst_rate 31508 # Simulator instruction rate (inst/s)
host_op_rate 31505 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 460155 # Simulator tick rate (ticks/s)
host_mem_usage 175808 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/linux/hello
executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -250,6 +262,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -344,7 +359,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000144 # Nu
sim_ticks 143853 # Number of ticks simulated
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 33822 # Simulator instruction rate (inst/s)
host_op_rate 33819 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 761273 # Simulator tick rate (ticks/s)
host_mem_usage 174328 # Number of bytes of host memory used
host_seconds 0.19 # Real time elapsed on the host
host_inst_rate 14935 # Simulator instruction rate (inst/s)
host_op_rate 14935 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 336198 # Simulator tick rate (ticks/s)
host_mem_usage 174340 # Number of bytes of host memory used
host_seconds 0.43 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

20
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -282,6 +294,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -436,7 +451,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000053 # Nu
sim_ticks 52548 # Number of ticks simulated
final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 18733 # Simulator instruction rate (inst/s)
host_op_rate 18730 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 381878 # Simulator tick rate (ticks/s)
host_mem_usage 173280 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
host_inst_rate 15623 # Simulator instruction rate (inst/s)
host_op_rate 15622 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 318507 # Simulator tick rate (ticks/s)
host_mem_usage 173288 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

20
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -267,6 +279,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -420,7 +435,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000045 # Nu
sim_ticks 44968 # Number of ticks simulated
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 20165 # Simulator instruction rate (inst/s)
host_op_rate 20162 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 351768 # Simulator tick rate (ticks/s)
host_mem_usage 175636 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_inst_rate 18935 # Simulator instruction rate (inst/s)
host_op_rate 18932 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 330302 # Simulator tick rate (ticks/s)
host_mem_usage 175652 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
@ -278,6 +290,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.l2_cntrl0]
@ -433,7 +448,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000043 # Nu
sim_ticks 43073 # Number of ticks simulated
final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 26989 # Simulator instruction rate (inst/s)
host_op_rate 26984 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 450937 # Simulator tick rate (ticks/s)
host_mem_usage 173396 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 22164 # Simulator instruction rate (inst/s)
host_op_rate 22160 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 370326 # Simulator tick rate (ticks/s)
host_mem_usage 173416 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -302,6 +314,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -396,7 +411,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000035 # Nu
sim_ticks 35432 # Number of ticks simulated
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 26797 # Simulator instruction rate (inst/s)
host_op_rate 26791 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 368294 # Simulator tick rate (ticks/s)
host_mem_usage 174352 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_inst_rate 22204 # Simulator instruction rate (inst/s)
host_op_rate 22201 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 305145 # Simulator tick rate (ticks/s)
host_mem_usage 174496 # Number of bytes of host memory used
host_seconds 0.12 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9

20
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -108,7 +110,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/alpha/tru64/hello
executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
@ -131,6 +133,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -250,6 +262,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -344,7 +359,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000052 # Nu
sim_ticks 52498 # Number of ticks simulated
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 23247 # Simulator instruction rate (inst/s)
host_op_rate 23243 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 473432 # Simulator tick rate (ticks/s)
host_mem_usage 172892 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
host_inst_rate 10658 # Simulator instruction rate (inst/s)
host_op_rate 10657 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 217095 # Simulator tick rate (ticks/s)
host_mem_usage 172908 # Number of bytes of host memory used
host_seconds 0.24 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

20
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
memories=system.physmem
@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
@ -110,7 +112,7 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/test-progs/hello/bin/mips/linux/hello
executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
@ -133,6 +135,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -252,6 +264,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -346,7 +361,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

10
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000125 # Nu
sim_ticks 125334 # Number of ticks simulated
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 31744 # Simulator instruction rate (inst/s)
host_op_rate 31741 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 684175 # Simulator tick rate (ticks/s)
host_mem_usage 176152 # Number of bytes of host memory used
host_inst_rate 32356 # Simulator instruction rate (inst/s)
host_op_rate 32352 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 697352 # Simulator tick rate (ticks/s)
host_mem_usage 176168 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

16
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -132,6 +132,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -251,6 +261,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@ -345,7 +358,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 31490 # Simulator instruction rate (inst/s)
host_op_rate 31486 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 638004 # Simulator tick rate (ticks/s)
host_mem_usage 182480 # Number of bytes of host memory used
host_seconds 0.17 # Real time elapsed on the host
host_inst_rate 1705 # Simulator instruction rate (inst/s)
host_op_rate 1705 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34543 # Simulator tick rate (ticks/s)
host_mem_usage 182496 # Number of bytes of host memory used
host_seconds 3.13 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message

16
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
View file

@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@ -166,6 +166,16 @@ latency_var=0
null=true
range=0:134217727
[system.piobus]
type=NoncoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
use_default_range=false
width=8
master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@ -286,6 +296,9 @@ using_network_tester=false
using_ruby_tester=false
version=0
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave
mem_master_port=system.piobus.slave[1]
pio_master_port=system.piobus.slave[0]
pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.ruby.memctrl_clk_domain]
@ -380,7 +393,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port

12
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
View file

@ -4,15 +4,17 @@ sim_seconds 0.000122 # Nu
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
host_inst_rate 29778 # Simulator instruction rate (inst/s)
host_op_rate 53940 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 673676 # Simulator tick rate (ticks/s)
host_mem_usage 193492 # Number of bytes of host memory used
host_seconds 0.18 # Real time elapsed on the host
host_inst_rate 27489 # Simulator instruction rate (inst/s)
host_op_rate 49793 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 621883 # Simulator tick rate (ticks/s)
host_mem_usage 193512 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
system.piobus.throughput 0 # Throughput (bytes/s)
system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message