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ruby: correct errors in changeset 4eec7bdde5b0

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Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch.
Firstly, we create interrupt controllers in the se mode, but no piobus was
being created.  RubyPort, which earlier used to ignore range changes now
forwards those to the piobus.  The lack of piobus resulted in segmentation
fault.  This patch creates a piobus even in se mode.  It is not created only
when some tester is running.  Secondly,  I had missed out on modifying port
connections for other coherence protocols.
This commit is contained in:
Nilay Vaish 2014-02-24 20:50:05 -06:00
parent 3b404fb1a0
commit 8504b079b8
7 changed files with 20 additions and 9 deletions
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5
configs/example/se.py
View file

@ -231,9 +231,10 @@ if options.ruby:
# Set the option for physmem so that it is not allocated any space
system.physmem = MemClass(range=AddrRange(options.mem_size),
null = True)
options.use_map = True
Ruby.create_system(options, system)
system.piobus = NoncoherentBus()
Ruby.create_system(options, system, system.piobus)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for i in xrange(np):

4
configs/ruby/MESI_Three_Level.py
View file

@ -117,7 +117,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cluster_id = i, ruby_system = ruby_system)
if piobus != None:
cpu_seq.pio_port = piobus.slave
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
i*num_cpus_per_cluster+j))

4
configs/ruby/MI_example.py
View file

@ -92,7 +92,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#

4
configs/ruby/MOESI_CMP_directory.py
View file

@ -102,7 +102,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#

4
configs/ruby/MOESI_CMP_token.py
View file

@ -122,7 +122,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
cpu_seq.pio_slave_port = piobus.master
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
#

4
configs/ruby/MOESI_hammer.py
View file

@ -115,7 +115,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
if piobus != None:
cpu_seq.pio_port = piobus.slave
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
cpu_seq.pio_slave_port = piobus.master
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency

4
tests/configs/simple-timing-ruby.py
View file

@ -79,8 +79,8 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
system.mem_ranges = AddrRange('256MB')
Ruby.create_system(options, system)
system.piobus = NoncoherentBus()
Ruby.create_system(options, system, system.piobus)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,