ruby: correct errors in changeset 4eec7bdde5b0
Couple of errors were discovered in 4eec7bdde5b0 which necessitated this patch. Firstly, we create interrupt controllers in the se mode, but no piobus was being created. RubyPort, which earlier used to ignore range changes now forwards those to the piobus. The lack of piobus resulted in segmentation fault. This patch creates a piobus even in se mode. It is not created only when some tester is running. Secondly, I had missed out on modifying port connections for other coherence protocols.
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3b404fb1a0
commit
8504b079b8
7 changed files with 20 additions and 9 deletions
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@ -231,9 +231,10 @@ if options.ruby:
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# Set the option for physmem so that it is not allocated any space
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system.physmem = MemClass(range=AddrRange(options.mem_size),
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null = True)
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options.use_map = True
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Ruby.create_system(options, system)
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system.piobus = NoncoherentBus()
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Ruby.create_system(options, system, system.piobus)
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assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
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for i in xrange(np):
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@ -117,7 +117,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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cluster_id = i, ruby_system = ruby_system)
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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cpu_seq.pio_slave_port = piobus.master
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exec("ruby_system.l0_cntrl%d = l0_cntrl" % (
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i*num_cpus_per_cluster+j))
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@ -92,7 +92,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l1_cntrl.sequencer = cpu_seq
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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cpu_seq.pio_slave_port = piobus.master
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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#
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@ -102,7 +102,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l1_cntrl.sequencer = cpu_seq
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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cpu_seq.pio_slave_port = piobus.master
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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#
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@ -122,7 +122,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l1_cntrl.sequencer = cpu_seq
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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cpu_seq.pio_slave_port = piobus.master
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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#
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@ -115,7 +115,9 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
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l1_cntrl.sequencer = cpu_seq
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if piobus != None:
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cpu_seq.pio_port = piobus.slave
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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cpu_seq.pio_slave_port = piobus.master
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if options.recycle_latency:
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l1_cntrl.recycle_latency = options.recycle_latency
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@ -79,8 +79,8 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
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voltage_domain = system.voltage_domain)
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system.mem_ranges = AddrRange('256MB')
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Ruby.create_system(options, system)
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system.piobus = NoncoherentBus()
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Ruby.create_system(options, system, system.piobus)
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# Create a separate clock for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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