stats: Bump for MessageBuffer, cache latency changes
This commit is contained in:
Joel Hestness
parent
905c0b347c
commit
93c173a95e
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:37:52
|
||||
gem5 started Jan 22 2014 17:25:49
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
|
||||
gem5 compiled Aug 13 2015 19:16:05
|
||||
gem5 started Aug 13 2015 20:15:31
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 138616 because target called exit()
|
||||
Exiting @ tick 121460 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000139 # Number of seconds simulated
|
||||
sim_ticks 138724 # Number of ticks simulated
|
||||
final_tick 138724 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000121 # Number of seconds simulated
|
||||
sim_ticks 121460 # Number of ticks simulated
|
||||
final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45032 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45028 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 977453 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451780 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 22637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22636 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 430242 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402016 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 #
|
|||
system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 673567660 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 673567660 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 127793316 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 127793316 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 801360976 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 801360976 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 769306768 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 769306768 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 145957517 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 145957517 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 915264285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 915264285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1460 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 277 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 75008 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 18432 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 6464 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 74176 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 155 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 105 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 87 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 394 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 138621 # Total gap between requests
|
||||
system.mem_ctrls.totGap 121373 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 1172 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 1159 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -136,11 +136,11 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
||||
|
|
@ -150,9 +150,9 @@ system.mem_ctrls.wrQLenPdf::26 6 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,88 +184,86 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 233 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 343.622318 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 215.641138 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 323.027267 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 63 27.04% 27.04% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 61 26.18% 53.22% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 29 12.45% 65.67% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 14 6.01% 71.67% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 15 6.44% 78.11% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 14 6.01% 84.12% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7 3.00% 87.12% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 7 3.00% 90.13% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 23 9.87% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 233 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 179.333333 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 129.319022 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 112.290100 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 66.67% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::320-335 1 16.67% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.833333 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.809662 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.983192 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 3 50.00% 50.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 16.67% 66.67% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 8028 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 30296 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5860 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.85 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 361.079070 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 218.518186 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 343.911785 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 62 28.84% 28.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 53 24.65% 53.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 19 8.84% 62.33% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 18 8.37% 70.70% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 12 5.58% 76.28% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 6 2.79% 79.07% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 11 5.12% 84.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 8 3.72% 87.91% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 26 12.09% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 150.200000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 107.544474 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 96.970098 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::240-247 1 20.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 8037 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 30058 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5795 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.93 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.85 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 540.70 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 46.60 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 673.57 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 127.79 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.93 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 610.70 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 44.26 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 769.31 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 145.96 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.22 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.36 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 22.86 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.46 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 79.80 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.98 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 604800 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 336000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5840640 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 383616 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 75398688 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 13434000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 104643264 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 789.033976 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 25868 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 22.44 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 944 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 81.45 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 69.88 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 80.28 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 66392460 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 11991000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 92751972 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 792.413259 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 22133 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 106302 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 93571 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 8087040 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 89353656 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1192800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 109683048 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 827.035092 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1330 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 78596388 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1285800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 98062908 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 837.786484 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1555 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 126886 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 111609 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -301,7 +299,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 138724 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 121460 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -320,7 +318,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 138724 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 121460 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -363,9 +361,9 @@ system.ruby.clk_domain.clock 1 # Cl
|
|||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 9645 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.162571 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.010166 # delay histogram for all message
|
||||
system.ruby.delayHist | 9296 96.38% 96.38% | 0 0.00% 96.38% | 204 2.12% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.164852 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.012053 # delay histogram for all message
|
||||
system.ruby.delayHist | 9285 96.27% 96.27% | 0 0.00% 96.27% | 215 2.23% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 9645 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -377,25 +375,25 @@ system.ruby.outstanding_req_hist::total 8449
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 15.420928
|
||||
system.ruby.latency_hist::gmean 5.221828
|
||||
system.ruby.latency_hist::stdev 29.495379
|
||||
system.ruby.latency_hist | 7276 86.13% 86.13% | 1152 13.64% 99.76% | 4 0.05% 99.81% | 4 0.05% 99.86% | 4 0.05% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.377367
|
||||
system.ruby.latency_hist::gmean 2.098947
|
||||
system.ruby.latency_hist::stdev 29.666839
|
||||
system.ruby.latency_hist | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 6958
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6958
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1490
|
||||
system.ruby.miss_latency_hist::mean 73.424161
|
||||
system.ruby.miss_latency_hist::gmean 69.478292
|
||||
system.ruby.miss_latency_hist::stdev 29.116195
|
||||
system.ruby.miss_latency_hist | 318 21.34% 21.34% | 1152 77.32% 98.66% | 4 0.27% 98.93% | 4 0.27% 99.19% | 4 0.27% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 71.177181
|
||||
system.ruby.miss_latency_hist::gmean 66.939744
|
||||
system.ruby.miss_latency_hist::stdev 30.560087
|
||||
system.ruby.miss_latency_hist | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1490
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
|
||||
|
|
@ -416,7 +414,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 30 # N
|
|||
system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 3.773860
|
||||
system.ruby.network.routers0.percent_links_utilized 4.310267
|
||||
system.ruby.network.routers0.msg_count.Control::0 1490
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 1490
|
||||
|
|
@ -433,7 +431,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers1.percent_links_utilized 7.327679
|
||||
system.ruby.network.routers1.percent_links_utilized 8.369216
|
||||
system.ruby.network.routers1.msg_count.Control::0 2950
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 3227
|
||||
|
|
@ -450,14 +448,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers2.percent_links_utilized 3.553819
|
||||
system.ruby.network.routers2.percent_links_utilized 4.058949
|
||||
system.ruby.network.routers2.msg_count.Control::0 1460
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 1737
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 2627
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 11680
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
|
||||
system.ruby.network.routers3.percent_links_utilized 4.885120
|
||||
system.ruby.network.routers3.percent_links_utilized 5.579477
|
||||
system.ruby.network.routers3.msg_count.Control::0 2950
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 3227
|
||||
|
|
@ -486,14 +484,14 @@ system.ruby.network.msg_byte.Response_Data 697032
|
|||
system.ruby.network.msg_byte.Response_Control 114288
|
||||
system.ruby.network.msg_byte.Writeback_Data 61776
|
||||
system.ruby.network.msg_byte.Writeback_Control 6984
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.365690
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.128355
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.182031
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.492178
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
|
||||
|
|
@ -506,7 +504,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.441394
|
||||
system.ruby.network.routers1.throttle0.link_utilization 8.499094
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
|
||||
|
|
@ -521,7 +519,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.213964
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.239338
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
|
||||
|
|
@ -530,26 +528,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.848274
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.110983
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.259364
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.006916
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.365690
|
||||
system.ruby.network.routers3.throttle0.link_utilization 6.128355
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.441394
|
||||
system.ruby.network.routers3.throttle1.link_utilization 8.499094
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
|
||||
|
|
@ -564,7 +562,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.848274
|
||||
system.ruby.network.routers3.throttle2.link_utilization 2.110983
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
|
||||
|
|
@ -581,9 +579,9 @@ system.ruby.delayVCHist.vnet_0::total 2725 # de
|
|||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.069400 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.366068 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 5675 96.53% 96.53% | 0 0.00% 96.53% | 204 3.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.073142 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.375443 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 5664 96.34% 96.34% | 0 0.00% 96.34% | 215 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||||
|
|
@ -593,71 +591,71 @@ system.ruby.delayVCHist.vnet_2::total 1041 # de
|
|||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 35.984784
|
||||
system.ruby.LD.latency_hist::gmean 13.718106
|
||||
system.ruby.LD.latency_hist::stdev 39.109328
|
||||
system.ruby.LD.latency_hist | 793 67.03% 67.03% | 384 32.46% 99.49% | 1 0.08% 99.58% | 1 0.08% 99.66% | 2 0.17% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 33.972105
|
||||
system.ruby.LD.latency_hist::gmean 7.701642
|
||||
system.ruby.LD.latency_hist::stdev 40.478944
|
||||
system.ruby.LD.latency_hist | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 600
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 600
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 583
|
||||
system.ruby.LD.miss_latency_hist::mean 69.931389
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.571846
|
||||
system.ruby.LD.miss_latency_hist::stdev 28.816437
|
||||
system.ruby.LD.miss_latency_hist | 193 33.10% 33.10% | 384 65.87% 98.97% | 1 0.17% 99.14% | 1 0.17% 99.31% | 2 0.34% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 67.905660
|
||||
system.ruby.LD.miss_latency_hist::gmean 62.953372
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.457951
|
||||
system.ruby.LD.miss_latency_hist | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 583
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 18.053179
|
||||
system.ruby.ST.latency_hist::gmean 6.262232
|
||||
system.ruby.ST.latency_hist::stdev 31.945584
|
||||
system.ruby.ST.latency_hist | 769 88.90% 88.90% | 92 10.64% 99.54% | 1 0.12% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 15.273988
|
||||
system.ruby.ST.latency_hist::gmean 2.701326
|
||||
system.ruby.ST.latency_hist::stdev 28.276128
|
||||
system.ruby.ST.latency_hist | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 649
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 649
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 216
|
||||
system.ruby.ST.miss_latency_hist::mean 63.282407
|
||||
system.ruby.ST.miss_latency_hist::gmean 57.152160
|
||||
system.ruby.ST.miss_latency_hist::stdev 36.903379
|
||||
system.ruby.ST.miss_latency_hist | 120 55.56% 55.56% | 92 42.59% 98.15% | 1 0.46% 98.61% | 0 0.00% 98.61% | 1 0.46% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 58.162037
|
||||
system.ruby.ST.miss_latency_hist::gmean 53.494090
|
||||
system.ruby.ST.miss_latency_hist::stdev 27.387260
|
||||
system.ruby.ST.miss_latency_hist | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 216
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 11.264062
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.262075
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.133535
|
||||
system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 676 10.56% 99.84% | 2 0.03% 99.88% | 3 0.05% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.314219
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.595263
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.608064
|
||||
system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 5709
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5709
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 691
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 79.541245
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 77.547127
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 24.993726
|
||||
system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 676 97.83% 98.55% | 2 0.29% 98.84% | 3 0.43% 99.28% | 1 0.14% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 78.005789
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 75.617268
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 28.004761
|
||||
system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 691
|
||||
system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data 277 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:42:56
|
||||
gem5 started Jan 22 2014 17:26:22
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
gem5 compiled Aug 13 2015 19:22:33
|
||||
gem5 started Aug 13 2015 20:16:04
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 117611 because target called exit()
|
||||
Exiting @ tick 108694 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000126 # Number of seconds simulated
|
||||
sim_ticks 126343 # Number of ticks simulated
|
||||
final_tick 126343 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000109 # Number of seconds simulated
|
||||
sim_ticks 108694 # Number of ticks simulated
|
||||
final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 43834 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43830 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 866526 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 454420 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 31686 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31684 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 538927 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 405952 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 #
|
|||
system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 598751019 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 598751019 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 98272164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 98272164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 697023183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 697023183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 695972179 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 695972179 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 114228936 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 114228936 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 810201115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 810201115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1182 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 64512 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 64448 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 78 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 82 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 20 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 363 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 9 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 126275 # Total gap between requests
|
||||
system.mem_ctrls.totGap 108642 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 1008 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 1007 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -136,7 +136,7 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
||||
|
|
@ -147,11 +147,11 @@ system.mem_ctrls.wrQLenPdf::23 6 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,86 +184,87 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 212 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 326.339623 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 200.746581 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 319.329567 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 67 31.60% 31.60% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 54 25.47% 57.08% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 23 10.85% 67.92% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 13 6.13% 74.06% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 12 5.66% 79.72% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 12 5.66% 85.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 6 2.83% 88.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.62% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 22 10.38% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 212 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 335.524752 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 204.886741 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 324.305016 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 65 32.18% 32.18% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 55.45% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 21 10.40% 65.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 14 6.93% 72.77% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 12 5.94% 78.71% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 11 5.45% 84.16% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 6 2.97% 87.13% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 89.60% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 21 10.40% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 136.800000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 103.930082 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 78.649221 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 141.200000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 107.481731 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 78.180560 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::112-119 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 7952 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 27104 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5040 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 7.89 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.totQLat 6988 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 26121 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5035 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 26.89 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 510.61 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 42.55 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 598.75 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 98.27 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 592.93 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 50.05 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 695.97 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 114.23 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.32 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.99 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.33 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 5.02 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 22.50 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 801 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 74 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 79.46 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 63.79 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 91.77 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5116800 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 63365076 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 19318200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 97130076 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 778.061425 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 32699 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 21.56 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 77 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.14 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 68.75 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 78.95 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.00 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 62170812 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 6351000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 81199236 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 800.165908 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 15769 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 88969 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 87863 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1028160 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 571200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 7300800 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 559872 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 84071808 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1154400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 102823200 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 823.666250 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1294 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 67286448 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1863600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 84579504 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 833.476261 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 2630 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 119396 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 95482 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -299,7 +300,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 126343 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 108694 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -318,7 +319,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 126343 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 108694 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -368,25 +369,25 @@ system.ruby.outstanding_req_hist::total 8449
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 13.955374
|
||||
system.ruby.latency_hist::gmean 4.957459
|
||||
system.ruby.latency_hist::stdev 28.739433
|
||||
system.ruby.latency_hist | 7439 88.06% 88.06% | 992 11.74% 99.80% | 2 0.02% 99.82% | 0 0.00% 99.82% | 4 0.05% 99.87% | 10 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.866241
|
||||
system.ruby.latency_hist::gmean 1.974485
|
||||
system.ruby.latency_hist::stdev 27.814086
|
||||
system.ruby.latency_hist | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 7027
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7027
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1421
|
||||
system.ruby.miss_latency_hist::mean 68.130894
|
||||
system.ruby.miss_latency_hist::gmean 59.425748
|
||||
system.ruby.miss_latency_hist::stdev 37.179084
|
||||
system.ruby.miss_latency_hist | 412 28.99% 28.99% | 992 69.81% 98.80% | 2 0.14% 98.94% | 0 0.00% 98.94% | 4 0.28% 99.23% | 10 0.70% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 65.600985
|
||||
system.ruby.miss_latency_hist::gmean 57.082853
|
||||
system.ruby.miss_latency_hist::stdev 33.588801
|
||||
system.ruby.miss_latency_hist | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1421
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses
|
||||
|
|
@ -398,7 +399,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 239 # N
|
|||
system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.967287
|
||||
system.ruby.network.routers0.percent_links_utilized 6.936215
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
|
||||
|
|
@ -411,7 +412,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers1.percent_links_utilized 8.962309
|
||||
system.ruby.network.routers1.percent_links_utilized 10.417548
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 2364
|
||||
|
|
@ -428,7 +429,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192
|
||||
system.ruby.network.routers2.percent_links_utilized 2.995021
|
||||
system.ruby.network.routers2.percent_links_utilized 3.481333
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
|
||||
|
|
@ -439,7 +440,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85104
|
|||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers3.percent_links_utilized 5.974873
|
||||
system.ruby.network.routers3.percent_links_utilized 6.945032
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 2364
|
||||
|
|
@ -468,14 +469,14 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624
|
|||
system.ruby.network.msg_byte.Writeback_Data 324432
|
||||
system.ruby.network.msg_byte.Writeback_Control 74304
|
||||
system.ruby.network.msg_byte.Unblock_Control 63576
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.597065
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.505879
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.337510
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.366552
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354
|
||||
|
|
@ -484,7 +485,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers1.throttle0.link_utilization 10.624253
|
||||
system.ruby.network.routers1.throttle0.link_utilization 12.349348
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308
|
||||
|
|
@ -497,7 +498,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.300365
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.485749
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
|
||||
|
|
@ -512,7 +513,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.703300
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.979870
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
|
||||
|
|
@ -521,19 +522,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456
|
|||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.286743
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.982796
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.597065
|
||||
system.ruby.network.routers3.throttle0.link_utilization 6.505879
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers3.throttle1.link_utilization 10.624253
|
||||
system.ruby.network.routers3.throttle1.link_utilization 12.349348
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308
|
||||
|
|
@ -546,7 +547,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176
|
|||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.703300
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.979870
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
|
||||
|
|
@ -558,77 +559,77 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456
|
|||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 29.639053
|
||||
system.ruby.LD.latency_hist::gmean 10.782209
|
||||
system.ruby.LD.latency_hist::stdev 38.418359
|
||||
system.ruby.LD.latency_hist | 863 72.95% 72.95% | 315 26.63% 99.58% | 1 0.08% 99.66% | 0 0.00% 99.66% | 1 0.08% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 27.265427
|
||||
system.ruby.LD.latency_hist::gmean 5.733715
|
||||
system.ruby.LD.latency_hist::stdev 35.817674
|
||||
system.ruby.LD.latency_hist | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 658
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 658
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 525
|
||||
system.ruby.LD.miss_latency_hist::mean 63.026667
|
||||
system.ruby.LD.miss_latency_hist::gmean 53.584951
|
||||
system.ruby.LD.miss_latency_hist::stdev 36.351224
|
||||
system.ruby.LD.miss_latency_hist | 205 39.05% 39.05% | 315 60.00% 99.05% | 1 0.19% 99.24% | 0 0.00% 99.24% | 1 0.19% 99.43% | 3 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 60.184762
|
||||
system.ruby.LD.miss_latency_hist::gmean 51.169278
|
||||
system.ruby.LD.miss_latency_hist::stdev 30.689440
|
||||
system.ruby.LD.miss_latency_hist | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 525
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 18.927168
|
||||
system.ruby.ST.latency_hist::gmean 6.798661
|
||||
system.ruby.ST.latency_hist::stdev 29.816693
|
||||
system.ruby.ST.latency_hist | 751 86.82% 86.82% | 112 12.95% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 17.593064
|
||||
system.ruby.ST.latency_hist::gmean 3.080574
|
||||
system.ruby.ST.latency_hist::stdev 34.156278
|
||||
system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 615
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 615
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 250
|
||||
system.ruby.ST.miss_latency_hist::mean 58.108000
|
||||
system.ruby.ST.miss_latency_hist::gmean 50.870585
|
||||
system.ruby.ST.miss_latency_hist::stdev 30.281947
|
||||
system.ruby.ST.miss_latency_hist | 136 54.40% 54.40% | 112 44.80% 99.20% | 1 0.40% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 58.412000
|
||||
system.ruby.ST.miss_latency_hist::gmean 49.053018
|
||||
system.ruby.ST.miss_latency_hist::stdev 41.173185
|
||||
system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 250
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 10.384375
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.114767
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.220182
|
||||
system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 565 8.83% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 3 0.05% 99.89% | 6 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.245781
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.526741
|
||||
system.ruby.IFETCH.latency_hist::stdev 23.776931
|
||||
system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 5754
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5754
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 646
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 76.157895
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 68.646090
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 38.613086
|
||||
system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 565 87.46% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 3 0.46% 98.92% | 6 0.93% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 72.784830
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 66.158480
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 31.122591
|
||||
system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 646
|
||||
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 984 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 517 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00%
|
||||
|
|
@ -641,7 +642,7 @@ system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00%
|
|||
system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 517 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
|
||||
|
|
@ -649,7 +650,7 @@ system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00%
|
|||
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 1362 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
|
||||
|
|
@ -669,12 +670,12 @@ system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.0
|
|||
system.ruby.L1Cache_Controller.M_W.Load 39 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 45 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 229 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 313 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 228 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 242 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 12 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 283 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 354 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 14 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:47:59
|
||||
gem5 started Jan 22 2014 17:27:26
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
gem5 compiled Aug 13 2015 19:28:58
|
||||
gem5 started Aug 13 2015 20:16:36
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 113627 because target called exit()
|
||||
Exiting @ tick 108259 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:32:54
|
||||
gem5 started Jan 22 2014 17:25:16
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
gem5 compiled Aug 13 2015 19:09:46
|
||||
gem5 started Aug 13 2015 20:15:17
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 93341 because target called exit()
|
||||
Exiting @ tick 86673 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000096 # Number of seconds simulated
|
||||
sim_ticks 95773 # Number of ticks simulated
|
||||
final_tick 95773 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000087 # Number of seconds simulated
|
||||
sim_ticks 86673 # Number of ticks simulated
|
||||
final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 67382 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 67372 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1009646 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 452992 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 41119 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41116 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 557651 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401992 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,29 +21,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 #
|
|||
system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 774498032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 774498032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 147014294 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 147014294 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 921512326 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 921512326 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 855814383 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 855814383 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 162449667 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 162449667 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1018264050 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1018264050 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1159 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 63936 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 10240 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesReadDRAM 63680 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 98 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 93 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
|
|
@ -53,27 +53,27 @@ system.mem_ctrls.perBankRdBursts::10 54 # Pe
|
|||
system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 42 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 95693 # Total gap between requests
|
||||
system.mem_ctrls.totGap 86601 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 999 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 995 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -145,11 +145,11 @@ system.mem_ctrls.wrQLenPdf::21 6 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
||||
|
|
@ -185,28 +185,27 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 190 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 358.736842 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 222.774947 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 335.486260 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 51 26.84% 26.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 50 26.32% 53.16% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 20 10.53% 63.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 14 7.37% 71.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 13 6.84% 77.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 7 3.68% 81.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 85.79% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 4 2.11% 87.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 23 12.11% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 360.757895 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 214.175980 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 351.466789 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 60 31.58% 31.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 43 22.63% 54.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 19 10.00% 64.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 13 6.84% 71.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 11 5.79% 76.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 4 2.11% 78.95% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 83.16% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 2.63% 85.79% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 27 14.21% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 190 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 140.600000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 106.599883 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 79.767161 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 143.200000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 107.762756 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 83.250826 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::216-223 2 40.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
|
||||
|
|
@ -215,55 +214,55 @@ system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Wr
|
|||
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 6604 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 25585 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4995 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.61 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.totQLat 6132 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 25037 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4975 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.16 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.61 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 667.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 57.47 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 774.50 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 147.01 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.16 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 734.72 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 63.50 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 855.81 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 162.45 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 5.66 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.22 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 6.24 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.87 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.78 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 69.39 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.73 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 483840 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 268800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5129280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 290304 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 54966924 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 7998600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 75240468 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 803.061820 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 13501 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 20.56 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 81.21 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 62.80 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 80.11 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 256200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 49992876 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 7690200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 69345636 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 807.226922 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 12934 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 77563 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 70523 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 601344 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 61807608 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1998600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 79043952 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 843.648426 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 2911 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 57826728 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 818400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 73589736 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 856.630922 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 958 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 87676 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 82102 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -299,7 +298,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 95773 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 86673 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -318,7 +317,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 95773 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 86673 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -368,26 +367,26 @@ system.ruby.outstanding_req_hist::total 8449
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 10.336766
|
||||
system.ruby.latency_hist::gmean 3.311568
|
||||
system.ruby.latency_hist::stdev 22.755667
|
||||
system.ruby.latency_hist | 8211 97.19% 97.19% | 225 2.66% 99.86% | 1 0.01% 99.87% | 0 0.00% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 9.259588
|
||||
system.ruby.latency_hist::gmean 1.841457
|
||||
system.ruby.latency_hist::stdev 22.233278
|
||||
system.ruby.latency_hist | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 2
|
||||
system.ruby.hit_latency_hist::max_bucket 19
|
||||
system.ruby.hit_latency_hist::samples 7289
|
||||
system.ruby.hit_latency_hist::mean 2.278502
|
||||
system.ruby.hit_latency_hist::gmean 2.102334
|
||||
system.ruby.hit_latency_hist::mean 1.278502
|
||||
system.ruby.hit_latency_hist::gmean 1.069062
|
||||
system.ruby.hit_latency_hist::stdev 1.645548
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7289
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1159
|
||||
system.ruby.miss_latency_hist::mean 61.015531
|
||||
system.ruby.miss_latency_hist::gmean 57.685008
|
||||
system.ruby.miss_latency_hist::stdev 27.944488
|
||||
system.ruby.miss_latency_hist | 922 79.55% 79.55% | 225 19.41% 98.96% | 1 0.09% 99.05% | 0 0.00% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 59.452977
|
||||
system.ruby.miss_latency_hist::gmean 56.282360
|
||||
system.ruby.miss_latency_hist::stdev 25.811948
|
||||
system.ruby.miss_latency_hist | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1159
|
||||
system.ruby.Directory.incomplete_times 1158
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
|
|
@ -402,9 +401,9 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.fully_busy_cycles 34 # cycles for which number of transistions == max transitions
|
||||
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 4.682426
|
||||
system.ruby.network.routers0.percent_links_utilized 5.174045
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
|
||||
|
|
@ -419,22 +418,22 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers1.percent_links_utilized 4.682426
|
||||
system.ruby.network.routers1.percent_links_utilized 5.173757
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 1143
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::5 923
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::5 1159
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::5 1158
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 9272
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers2.percent_links_utilized 4.682426
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9264
|
||||
system.ruby.network.routers2.percent_links_utilized 5.174045
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
|
||||
|
|
@ -453,18 +452,18 @@ system.ruby.network.msg_count.Request_Control 3477
|
|||
system.ruby.network.msg_count.Response_Data 3477
|
||||
system.ruby.network.msg_count.Writeback_Data 660
|
||||
system.ruby.network.msg_count.Writeback_Control 9627
|
||||
system.ruby.network.msg_count.Unblock_Control 3477
|
||||
system.ruby.network.msg_count.Unblock_Control 3476
|
||||
system.ruby.network.msg_byte.Request_Control 27816
|
||||
system.ruby.network.msg_byte.Response_Data 250344
|
||||
system.ruby.network.msg_byte.Writeback_Data 47520
|
||||
system.ruby.network.msg_byte.Writeback_Control 77016
|
||||
system.ruby.network.msg_byte.Unblock_Control 27816
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.042413
|
||||
system.ruby.network.msg_byte.Unblock_Control 27808
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.676820
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.322440
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.671270
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143
|
||||
|
|
@ -475,28 +474,28 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.322440
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.670693
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 923
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1158
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9272
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.042413
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9264
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.676820
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.042413
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.676820
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.322440
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.671270
|
||||
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143
|
||||
|
|
@ -507,99 +506,99 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
|
|||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 22.748943
|
||||
system.ruby.LD.latency_hist::gmean 7.555083
|
||||
system.ruby.LD.latency_hist::stdev 30.673688
|
||||
system.ruby.LD.latency_hist | 1093 92.39% 92.39% | 87 7.35% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 21.460693
|
||||
system.ruby.LD.latency_hist::gmean 5.052192
|
||||
system.ruby.LD.latency_hist::stdev 28.940454
|
||||
system.ruby.LD.latency_hist | 852 72.02% 72.02% | 242 20.46% 92.48% | 85 7.19% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 2
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 19
|
||||
system.ruby.LD.hit_latency_hist::samples 763
|
||||
system.ruby.LD.hit_latency_hist::mean 3.376147
|
||||
system.ruby.LD.hit_latency_hist::gmean 2.559264
|
||||
system.ruby.LD.hit_latency_hist::mean 2.376147
|
||||
system.ruby.LD.hit_latency_hist::gmean 1.390948
|
||||
system.ruby.LD.hit_latency_hist::stdev 3.447211
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 763
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 420
|
||||
system.ruby.LD.miss_latency_hist::mean 57.942857
|
||||
system.ruby.LD.miss_latency_hist::gmean 53.988115
|
||||
system.ruby.LD.miss_latency_hist::stdev 26.600762
|
||||
system.ruby.LD.miss_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 56.130952
|
||||
system.ruby.LD.miss_latency_hist::gmean 52.616261
|
||||
system.ruby.LD.miss_latency_hist::stdev 21.748058
|
||||
system.ruby.LD.miss_latency_hist | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 420
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 11.732948
|
||||
system.ruby.ST.latency_hist::gmean 3.862911
|
||||
system.ruby.ST.latency_hist::stdev 20.767655
|
||||
system.ruby.ST.latency_hist | 707 81.73% 81.73% | 41 4.74% 86.47% | 0 0.00% 86.47% | 78 9.02% 95.49% | 35 4.05% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 10.558382
|
||||
system.ruby.ST.latency_hist::gmean 2.225841
|
||||
system.ruby.ST.latency_hist::stdev 20.458667
|
||||
system.ruby.ST.latency_hist | 707 81.73% 81.73% | 45 5.20% 86.94% | 0 0.00% 86.94% | 76 8.79% 95.72% | 33 3.82% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 2
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 19
|
||||
system.ruby.ST.hit_latency_hist::samples 707
|
||||
system.ruby.ST.hit_latency_hist::mean 2.466761
|
||||
system.ruby.ST.hit_latency_hist::gmean 2.174458
|
||||
system.ruby.ST.hit_latency_hist::mean 1.466761
|
||||
system.ruby.ST.hit_latency_hist::gmean 1.118428
|
||||
system.ruby.ST.hit_latency_hist::stdev 2.110935
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 707
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 158
|
||||
system.ruby.ST.miss_latency_hist::mean 53.196203
|
||||
system.ruby.ST.miss_latency_hist::gmean 50.539760
|
||||
system.ruby.ST.miss_latency_hist::stdev 15.383612
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 51.240506
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.407659
|
||||
system.ruby.ST.miss_latency_hist::stdev 15.670342
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 158
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 7.853750
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.784724
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.410979
|
||||
system.ruby.IFETCH.latency_hist | 6292 98.31% 98.31% | 99 1.55% 99.86% | 1 0.02% 99.88% | 0 0.00% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 6.828750
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.489407
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.190166
|
||||
system.ruby.IFETCH.latency_hist | 6294 98.34% 98.34% | 97 1.52% 99.86% | 0 0.00% 99.86% | 2 0.03% 99.89% | 5 0.08% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 5819
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 2.111703
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 2.040432
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1.111703
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1.027147
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev 1.051067
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5819
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 581
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.363167
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 62.729888
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 30.682702
|
||||
system.ruby.IFETCH.miss_latency_hist | 473 81.41% 81.41% | 99 17.04% 98.45% | 1 0.17% 98.62% | 0 0.00% 98.62% | 4 0.69% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 64.087780
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 61.562973
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 29.566480
|
||||
system.ruby.IFETCH.miss_latency_hist | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 581
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::samples 7086
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 2
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::total 7086
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 2
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 19
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::samples 203
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 12
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 11
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 203
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1159
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 61.015531
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 57.685008
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 27.944488
|
||||
system.ruby.Directory.miss_mach_latency_hist | 922 79.55% 79.55% | 225 19.41% 98.96% | 1 0.09% 99.05% | 0 0.00% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 59.452977
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 56.282360
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 25.811948
|
||||
system.ruby.Directory.miss_mach_latency_hist | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1159
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -630,73 +629,73 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
|
|||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 658
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 658
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 105
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 105
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 420
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.942857
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 53.988115
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.600762
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 56.130952
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.616261
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 21.748058
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 674
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 674
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 33
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.196203
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.539760
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.383612
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.240506
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.407659
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.670342
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 5754
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 5754
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 65
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 65
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.363167
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.729888
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 30.682702
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 473 81.41% 81.41% | 99 17.04% 98.45% | 1 0.17% 98.62% | 0 0.00% 98.62% | 4 0.69% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 64.087780
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.562973
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 29.566480
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581
|
||||
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 1020 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUT 1143 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.UnblockM 1158 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00%
|
||||
|
|
@ -704,7 +703,7 @@ system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00%
|
|||
system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_B.UnblockM 1158 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:20
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
|
||||
gem5 compiled Aug 13 2015 19:05:56
|
||||
gem5 started Aug 13 2015 20:14:39
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 143853 because target called exit()
|
||||
Exiting @ tick 107210 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000124 # Number of seconds simulated
|
||||
sim_ticks 123531 # Number of ticks simulated
|
||||
final_tick 123531 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000107 # Number of seconds simulated
|
||||
sim_ticks 107210 # Number of ticks simulated
|
||||
final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 63521 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 63513 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1227662 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451804 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_inst_rate 29183 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29181 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 489574 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401792 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 #
|
|||
system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 896293238 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 896293238 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 894220884 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 894220884 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790514122 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1790514122 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1730 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1726 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 56832 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 53888 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 56512 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 842 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 118 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 25 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 264 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 73 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 20 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 127 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 48 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 260 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 74 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 123443 # Total gap between requests
|
||||
system.mem_ctrls.totGap 107138 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 888 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -135,13 +135,13 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see
|
||||
|
|
@ -149,7 +149,7 @@ system.mem_ctrls.wrQLenPdf::25 55 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 54 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see
|
||||
|
|
@ -184,88 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 268 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 416.477612 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 263.436899 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 359.508293 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 60 22.39% 22.39% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 57 21.27% 43.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 40 14.93% 58.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 20 7.46% 66.04% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 10 3.73% 69.78% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 14 5.22% 75.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 11 4.10% 79.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 12 4.48% 83.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 44 16.42% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 268 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.997541 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.176444 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 3.70% 3.70% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 22 40.74% 44.44% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 22 40.74% 85.19% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 6 11.11% 96.30% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::22-23 1 1.85% 98.15% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.351852 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.333537 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.804642 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 45 83.33% 83.33% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 8 14.81% 98.15% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 1.85% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 10373 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 27245 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4440 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 11.68 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.totQLat 10919 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 30.68 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 460.06 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 457.47 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 896.29 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 894.22 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.17 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.91 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 672 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 824 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 75.68 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 35.72 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 83.11 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 824040 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 457800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 4520448 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 66802176 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 11631600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 97093584 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 829.505203 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 19845 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 31.00 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 94170 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 5191680 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 4136832 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 69356232 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 9391800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 97445424 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 832.503985 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 15122 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 98043 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -301,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 123531 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 107210 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -320,7 +320,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 123531 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 107210 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -375,32 +375,32 @@ system.ruby.outstanding_req_hist::total 8449
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 13.622514
|
||||
system.ruby.latency_hist::gmean 5.329433
|
||||
system.ruby.latency_hist::stdev 25.311843
|
||||
system.ruby.latency_hist | 8197 97.03% 97.03% | 202 2.39% 99.42% | 36 0.43% 99.85% | 3 0.04% 99.88% | 8 0.09% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.690578
|
||||
system.ruby.latency_hist::gmean 2.205273
|
||||
system.ruby.latency_hist::stdev 25.830363
|
||||
system.ruby.latency_hist | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 6718
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6718
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1730
|
||||
system.ruby.miss_latency_hist::mean 54.872254
|
||||
system.ruby.miss_latency_hist::gmean 49.634160
|
||||
system.ruby.miss_latency_hist::stdev 31.450318
|
||||
system.ruby.miss_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 53.204624
|
||||
system.ruby.miss_latency_hist::gmean 47.556283
|
||||
system.ruby.miss_latency_hist::stdev 33.032605
|
||||
system.ruby.miss_latency_hist | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1730
|
||||
system.ruby.Directory.incomplete_times 1729
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.994196
|
||||
system.ruby.network.routers0.percent_links_utilized 8.058950
|
||||
system.ruby.network.routers0.msg_count.Control::2 1730
|
||||
system.ruby.network.routers0.msg_count.Data::2 1726
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1730
|
||||
|
|
@ -409,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13840
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers1.percent_links_utilized 6.994196
|
||||
system.ruby.network.routers1.percent_links_utilized 8.058950
|
||||
system.ruby.network.routers1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1730
|
||||
|
|
@ -418,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13840
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.percent_links_utilized 6.994196
|
||||
system.ruby.network.routers2.percent_links_utilized 8.058950
|
||||
system.ruby.network.routers2.msg_count.Control::2 1730
|
||||
system.ruby.network.routers2.msg_count.Data::2 1726
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1730
|
||||
|
|
@ -435,32 +435,32 @@ system.ruby.network.msg_byte.Control 41520
|
|||
system.ruby.network.msg_byte.Data 372816
|
||||
system.ruby.network.msg_byte.Response_Data 373680
|
||||
system.ruby.network.msg_byte.Writeback_Control 41424
|
||||
system.ruby.network.routers0.throttle0.link_utilization 7.000672
|
||||
system.ruby.network.routers0.throttle0.link_utilization 8.066412
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.987720
|
||||
system.ruby.network.routers0.throttle1.link_utilization 8.051488
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.987720
|
||||
system.ruby.network.routers1.throttle0.link_utilization 8.051488
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.000672
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.066412
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.throttle0.link_utilization 7.000672
|
||||
system.ruby.network.routers2.throttle0.link_utilization 8.066412
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.987720
|
||||
system.ruby.network.routers2.throttle1.link_utilization 8.051488
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
|
||||
|
|
@ -478,79 +478,79 @@ system.ruby.delayVCHist.vnet_2::total 1726 # de
|
|||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 32.793745
|
||||
system.ruby.LD.latency_hist::gmean 16.273400
|
||||
system.ruby.LD.latency_hist::stdev 32.397171
|
||||
system.ruby.LD.latency_hist | 1086 91.80% 91.80% | 85 7.19% 98.99% | 8 0.68% 99.66% | 1 0.08% 99.75% | 2 0.17% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 31.638208
|
||||
system.ruby.LD.latency_hist::gmean 10.419015
|
||||
system.ruby.LD.latency_hist::stdev 35.065266
|
||||
system.ruby.LD.latency_hist | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 456
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 456
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 727
|
||||
system.ruby.LD.miss_latency_hist::mean 51.481431
|
||||
system.ruby.LD.miss_latency_hist::gmean 46.999464
|
||||
system.ruby.LD.miss_latency_hist::stdev 28.311858
|
||||
system.ruby.LD.miss_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 50.855571
|
||||
system.ruby.LD.miss_latency_hist::gmean 45.315147
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.287061
|
||||
system.ruby.LD.miss_latency_hist | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 727
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 18.649711
|
||||
system.ruby.ST.latency_hist::gmean 7.153271
|
||||
system.ruby.ST.latency_hist::stdev 30.101235
|
||||
system.ruby.ST.latency_hist | 832 96.18% 96.18% | 24 2.77% 98.96% | 6 0.69% 99.65% | 1 0.12% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 16.483237
|
||||
system.ruby.ST.latency_hist::gmean 3.324735
|
||||
system.ruby.ST.latency_hist::stdev 28.016571
|
||||
system.ruby.ST.latency_hist | 592 68.44% 68.44% | 244 28.21% 96.65% | 18 2.08% 98.73% | 2 0.23% 98.96% | 5 0.58% 99.54% | 2 0.23% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 592
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 592
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 273
|
||||
system.ruby.ST.miss_latency_hist::mean 52.586081
|
||||
system.ruby.ST.miss_latency_hist::gmean 47.082552
|
||||
system.ruby.ST.miss_latency_hist::stdev 34.484663
|
||||
system.ruby.ST.miss_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 50.058608
|
||||
system.ruby.ST.miss_latency_hist::gmean 44.997273
|
||||
system.ruby.ST.miss_latency_hist::stdev 28.984216
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 273
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 9.399375
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.166708
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.983950
|
||||
system.ruby.IFETCH.latency_hist | 5670 88.59% 88.59% | 609 9.52% 98.11% | 88 1.38% 99.48% | 5 0.08% 99.56% | 5 0.08% 99.64% | 17 0.27% 99.91% | 1 0.02% 99.92% | 0 0.00% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 7.355625
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.565715
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.264557
|
||||
system.ruby.IFETCH.latency_hist | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 5670
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5670
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 730
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 59.104110
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 53.449398
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 32.750880
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 56.720548
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 50.941265
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 34.853032
|
||||
system.ruby.IFETCH.miss_latency_hist | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 730
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1730
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 54.872254
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 49.634160
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 31.450318
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 53.204624
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 47.556283
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 33.032605
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1730
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -581,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
|
|||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.481431
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.999464
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.311858
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.855571
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.315147
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.287061
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.586081
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.082552
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 34.484663
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 50.058608
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.997273
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 28.984216
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 59.104110
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 53.449398
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.750880
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.720548
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.941265
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.853032
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730
|
||||
system.ruby.Directory_Controller.GETX 1730 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall sigprocmask(1, ...)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:37:52
|
||||
gem5 started Jan 22 2014 17:26:00
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
|
||||
gem5 compiled Aug 13 2015 19:16:05
|
||||
gem5 started Aug 13 2015 20:15:42
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 52548 because target called exit()
|
||||
Exiting @ tick 45733 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000052 # Number of seconds simulated
|
||||
sim_ticks 52301 # Number of ticks simulated
|
||||
final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000046 # Number of seconds simulated
|
||||
sim_ticks 45733 # Number of ticks simulated
|
||||
final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 42059 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42050 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 853239 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 450140 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 17774 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17773 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 315387 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401732 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 #
|
|||
system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 669356226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 669356226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 126039655 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 126039655 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 795395882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 795395882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 765486629 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 765486629 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 144140992 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 144140992 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 909627621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 909627621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 547 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 103 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 52214 # Total gap between requests
|
||||
system.mem_ctrls.totGap 45654 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -184,20 +184,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 334.829268 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 222.665618 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 287.679168 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 22 26.83% 26.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 19 23.17% 50.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 5 6.10% 56.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 17 20.73% 76.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 5 6.10% 82.93% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 4 4.88% 87.80% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 3 3.66% 91.46% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 2 2.44% 93.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 5 6.10% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 358.054054 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 233.275053 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 307.922241 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 18 24.32% 24.32% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 48.65% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 8 10.81% 59.46% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 4 5.41% 64.86% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 9 12.16% 77.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 7 9.46% 86.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 3 4.05% 90.54% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 91.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 6 8.11% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes
|
||||
|
|
@ -210,55 +210,55 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
|
|||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2713 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11035 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totQLat 2733 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11055 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.19 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgQLat 6.24 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.19 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 535.97 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 19.58 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 669.36 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 126.04 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.24 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 612.95 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 22.39 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 765.49 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 144.14 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.34 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.19 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.15 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 4.96 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.79 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 22.51 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 350 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 14 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 79.91 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 80.33 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 356 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 81.28 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 70.24 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 76.65 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1797120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 31347036 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 688200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 37328916 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 794.638028 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 1179 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 26498844 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 269400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 31331604 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 799.479561 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 528 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 44437 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 37581 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2907840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.actEnergy 362880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 201600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2882880 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 31309416 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 721200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 38767224 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 825.255960 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1048 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 26204040 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 528000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 32888088 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 839.195917 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 754 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 44382 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -294,7 +294,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 52301 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 45733 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -313,7 +313,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 52301 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 45733 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -370,25 +370,25 @@ system.ruby.outstanding_req_hist::total 3295
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 14.877656
|
||||
system.ruby.latency_hist::gmean 5.143561
|
||||
system.ruby.latency_hist::stdev 28.438893
|
||||
system.ruby.latency_hist | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 2 0.06% 99.88% | 3 0.09% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 12.883728
|
||||
system.ruby.latency_hist::gmean 2.062291
|
||||
system.ruby.latency_hist::stdev 28.863704
|
||||
system.ruby.latency_hist | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 2722
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2722
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 572
|
||||
system.ruby.miss_latency_hist::mean 71.400350
|
||||
system.ruby.miss_latency_hist::gmean 66.909551
|
||||
system.ruby.miss_latency_hist::stdev 28.130025
|
||||
system.ruby.miss_latency_hist | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 2 0.35% 99.30% | 3 0.52% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 69.435315
|
||||
system.ruby.miss_latency_hist::gmean 64.604000
|
||||
system.ruby.miss_latency_hist::stdev 30.458568
|
||||
system.ruby.miss_latency_hist | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 572
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
|
||||
|
|
@ -409,7 +409,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 25 # N
|
|||
system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 3.803943
|
||||
system.ruby.network.routers0.percent_links_utilized 4.350250
|
||||
system.ruby.network.routers0.msg_count.Control::0 572
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 572
|
||||
|
|
@ -426,7 +426,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers1.percent_links_utilized 7.327776
|
||||
system.ruby.network.routers1.percent_links_utilized 8.380163
|
||||
system.ruby.network.routers1.msg_count.Control::0 1119
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 1222
|
||||
|
|
@ -443,14 +443,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers2.percent_links_utilized 3.523833
|
||||
system.ruby.network.routers2.percent_links_utilized 4.029913
|
||||
system.ruby.network.routers2.msg_count.Control::0 547
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 650
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 975
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 4376
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
|
||||
system.ruby.network.routers3.percent_links_utilized 4.885184
|
||||
system.ruby.network.routers3.percent_links_utilized 5.586775
|
||||
system.ruby.network.routers3.msg_count.Control::0 1119
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 1222
|
||||
|
|
@ -479,14 +479,14 @@ system.ruby.network.msg_byte.Response_Data 263952
|
|||
system.ruby.network.msg_byte.Response_Control 41760
|
||||
system.ruby.network.msg_byte.Writeback_Data 23112
|
||||
system.ruby.network.msg_byte.Writeback_Control 1896
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.452095
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.235104
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.155791
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.465397
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 572
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272
|
||||
|
|
@ -499,7 +499,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.377488
|
||||
system.ruby.network.routers1.throttle0.link_utilization 8.437015
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 572
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908
|
||||
|
|
@ -514,7 +514,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.278064
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.323311
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 547
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675
|
||||
|
|
@ -523,26 +523,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.825969
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.088208
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 547
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.221697
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.971618
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.452095
|
||||
system.ruby.network.routers3.throttle0.link_utilization 6.235104
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.377488
|
||||
system.ruby.network.routers3.throttle1.link_utilization 8.437015
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 572
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908
|
||||
|
|
@ -557,7 +557,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.825969
|
||||
system.ruby.network.routers3.throttle2.link_utilization 2.088208
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 547
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436
|
||||
|
|
@ -586,71 +586,71 @@ system.ruby.delayVCHist.vnet_2::total 431 # de
|
|||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 33.351807
|
||||
system.ruby.LD.latency_hist::gmean 13.076698
|
||||
system.ruby.LD.latency_hist::stdev 35.943616
|
||||
system.ruby.LD.latency_hist | 223 53.73% 53.73% | 75 18.07% 71.81% | 105 25.30% 97.11% | 11 2.65% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 31.356627
|
||||
system.ruby.LD.latency_hist::gmean 7.342788
|
||||
system.ruby.LD.latency_hist::stdev 35.995277
|
||||
system.ruby.LD.latency_hist | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 211
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 211
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 204
|
||||
system.ruby.LD.miss_latency_hist::mean 64.745098
|
||||
system.ruby.LD.miss_latency_hist::gmean 59.953469
|
||||
system.ruby.LD.miss_latency_hist::stdev 26.208218
|
||||
system.ruby.LD.miss_latency_hist | 12 5.88% 5.88% | 75 36.76% 42.65% | 105 51.47% 94.12% | 11 5.39% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 62.754902
|
||||
system.ruby.LD.miss_latency_hist::gmean 57.734169
|
||||
system.ruby.LD.miss_latency_hist::stdev 26.340677
|
||||
system.ruby.LD.miss_latency_hist | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 204
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 16.670068
|
||||
system.ruby.ST.latency_hist::gmean 5.908100
|
||||
system.ruby.ST.latency_hist::stdev 30.631855
|
||||
system.ruby.ST.latency_hist::mean 14.789116
|
||||
system.ruby.ST.latency_hist::gmean 2.517478
|
||||
system.ruby.ST.latency_hist::stdev 31.573573
|
||||
system.ruby.ST.latency_hist | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 226
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 226
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 68
|
||||
system.ruby.ST.miss_latency_hist::mean 62.102941
|
||||
system.ruby.ST.miss_latency_hist::gmean 56.188955
|
||||
system.ruby.ST.miss_latency_hist::stdev 37.122283
|
||||
system.ruby.ST.miss_latency_hist::mean 60.617647
|
||||
system.ruby.ST.miss_latency_hist::gmean 54.148546
|
||||
system.ruby.ST.miss_latency_hist::stdev 39.831747
|
||||
system.ruby.ST.miss_latency_hist | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 68
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 11.707930
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.358751
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.535583
|
||||
system.ruby.IFETCH.latency_hist | 2294 88.74% 88.74% | 0 0.00% 88.74% | 276 10.68% 99.42% | 10 0.39% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 1 0.04% 99.92% | 1 0.04% 99.96% | 1 0.04% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.701354
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.644214
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.994801
|
||||
system.ruby.IFETCH.latency_hist | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2285
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2285
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 300
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 78.033333
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 75.006009
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 25.337433
|
||||
system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 75.976667
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 72.583942
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 29.223784
|
||||
system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 300
|
||||
system.ruby.Directory_Controller.Fetch 547 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data 103 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall sigprocmask(1, ...)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:42:56
|
||||
gem5 started Jan 22 2014 17:26:33
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
gem5 compiled Aug 13 2015 19:22:33
|
||||
gem5 started Aug 13 2015 20:16:13
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 44968 because target called exit()
|
||||
Exiting @ tick 41712 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000048 # Number of seconds simulated
|
||||
sim_ticks 48283 # Number of ticks simulated
|
||||
final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000042 # Number of seconds simulated
|
||||
sim_ticks 41712 # Number of ticks simulated
|
||||
final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45593 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 854052 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451760 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 24481 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 24478 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 396175 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 403616 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29760 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 29760 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 4992 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 465 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 465 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 616366009 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 616366009 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 103390427 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 103390427 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 719756436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 719756436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 465 # Number of read requests accepted
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 711929421 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 711929421 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 119677791 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 119677791 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 831607211 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 831607211 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 464 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 78 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 465 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 78 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24640 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 24576 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 5120 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 29760 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesReadSys 29696 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 4992 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 32 # Number of DRAM write bursts merged with an existing one
|
||||
|
|
@ -49,7 +49,7 @@ system.mem_ctrls.perBankRdBursts::6 24 # Pe
|
|||
system.mem_ctrls.perBankRdBursts::7 69 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts
|
||||
|
|
@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 48195 # Total gap between requests
|
||||
system.mem_ctrls.totGap 41632 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 465 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 464 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 78 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 385 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 384 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -184,23 +184,23 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 305.951220 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 201.196627 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 274.128379 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 25 30.49% 30.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 16 19.51% 50.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 13 15.85% 65.85% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 9 10.98% 76.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 8.54% 85.37% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 3 3.66% 89.02% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 4 4.88% 93.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 2 2.44% 96.34% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 3 3.66% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 336 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 226.772547 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 284.954160 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 17 23.61% 23.61% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 17 23.61% 47.22% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 12 16.67% 63.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 9.72% 80.56% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 6 8.33% 88.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.78% 91.67% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 4.17% 95.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 3 4.17% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 249 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 249.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::248-255 1 100.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes
|
||||
|
|
@ -210,55 +210,55 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
|
|||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2437 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9752 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1925 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.33 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.totQLat 2393 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9689 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.23 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.33 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 510.32 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 21.21 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 616.37 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 103.39 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.23 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 589.18 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 24.55 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 711.93 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 119.68 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.15 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.99 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 4.79 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.60 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 299 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.avgWrQLen 21.63 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 305 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 77.66 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.readRowHitRate 79.43 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 88.76 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1884480 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.avgGap 76.81 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 74.42 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1809600 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 31537872 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 520800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 37264992 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 793.277248 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 968 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 24398280 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 2114400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 31112040 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 793.795989 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 3488 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 44716 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 34510 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 446040 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 247800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2808000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 214200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2708160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 30693132 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 1263000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 38675220 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 823.262378 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 2007 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 26293644 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 449400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 32759652 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 835.918653 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 623 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 43481 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -294,7 +294,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 48283 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 41712 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -313,7 +313,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 48283 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 41712 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -360,28 +360,28 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::bucket_size 32
|
||||
system.ruby.latency_hist::max_bucket 319
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 13.657863
|
||||
system.ruby.latency_hist::gmean 4.922626
|
||||
system.ruby.latency_hist::stdev 27.058784
|
||||
system.ruby.latency_hist | 2909 88.31% 88.31% | 378 11.48% 99.79% | 3 0.09% 99.88% | 0 0.00% 99.88% | 3 0.09% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.663024
|
||||
system.ruby.latency_hist::gmean 1.954156
|
||||
system.ruby.latency_hist::stdev 27.142816
|
||||
system.ruby.latency_hist | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 2750
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2750
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::bucket_size 32
|
||||
system.ruby.miss_latency_hist::max_bucket 319
|
||||
system.ruby.miss_latency_hist::samples 544
|
||||
system.ruby.miss_latency_hist::mean 67.534926
|
||||
system.ruby.miss_latency_hist::gmean 60.177697
|
||||
system.ruby.miss_latency_hist::stdev 30.933879
|
||||
system.ruby.miss_latency_hist | 159 29.23% 29.23% | 378 69.49% 98.71% | 3 0.55% 99.26% | 0 0.00% 99.26% | 3 0.55% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 65.566176
|
||||
system.ruby.miss_latency_hist::gmean 57.783054
|
||||
system.ruby.miss_latency_hist::stdev 31.323348
|
||||
system.ruby.miss_latency_hist | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00%
|
||||
system.ruby.miss_latency_hist::total 544
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses
|
||||
|
|
@ -389,88 +389,88 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.874739
|
||||
system.ruby.network.routers0.percent_links_utilized 6.800201
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers1.percent_links_utilized 8.967442
|
||||
system.ruby.network.routers1.percent_links_utilized 10.372914
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 930
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 928
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 560
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1029
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1027
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 66960
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 66816
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8232
|
||||
system.ruby.network.routers2.percent_links_utilized 3.092186
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216
|
||||
system.ruby.network.routers2.percent_links_utilized 3.572713
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 464
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 463
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3712
|
||||
system.ruby.network.routers3.percent_links_utilized 5.978295
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704
|
||||
system.ruby.network.routers3.percent_links_utilized 6.915276
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 930
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 928
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 560
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1029
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1027
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 66960
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 66816
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8232
|
||||
system.ruby.network.msg_count.Request_Control 3027
|
||||
system.ruby.network.msg_count.Response_Data 2790
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 237
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216
|
||||
system.ruby.network.msg_count.Request_Control 3024
|
||||
system.ruby.network.msg_count.Response_Data 2784
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 240
|
||||
system.ruby.network.msg_count.Writeback_Data 1680
|
||||
system.ruby.network.msg_count.Writeback_Control 3480
|
||||
system.ruby.network.msg_count.Unblock_Control 3086
|
||||
system.ruby.network.msg_byte.Request_Control 24216
|
||||
system.ruby.network.msg_byte.Response_Data 200880
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 17064
|
||||
system.ruby.network.msg_count.Unblock_Control 3081
|
||||
system.ruby.network.msg_byte.Request_Control 24192
|
||||
system.ruby.network.msg_byte.Response_Data 200448
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 17280
|
||||
system.ruby.network.msg_byte.Writeback_Data 120960
|
||||
system.ruby.network.msg_byte.Writeback_Control 27840
|
||||
system.ruby.network.msg_byte.Unblock_Control 24688
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.589959
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.msg_byte.Unblock_Control 24648
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.470560
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.159518
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.129843
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502
|
||||
|
|
@ -479,165 +479,165 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers1.throttle0.link_utilization 10.574115
|
||||
system.ruby.network.routers1.throttle0.link_utilization 12.229095
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.360769
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.516734
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 465
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 463
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3720
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.769774
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.046174
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 464
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 463
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3712
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.414597
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.099252
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.589959
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers3.throttle0.link_utilization 6.470560
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers3.throttle1.link_utilization 10.574115
|
||||
system.ruby.network.routers3.throttle1.link_utilization 12.229095
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 33408
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.770810
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers3.throttle2.link_utilization 2.046174
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 465
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 463
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3720
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 27.831325
|
||||
system.ruby.LD.latency_hist::gmean 10.396167
|
||||
system.ruby.LD.latency_hist::stdev 35.321716
|
||||
system.ruby.LD.latency_hist | 274 66.02% 66.02% | 45 10.84% 76.87% | 87 20.96% 97.83% | 7 1.69% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 25.657831
|
||||
system.ruby.LD.latency_hist::gmean 5.487426
|
||||
system.ruby.LD.latency_hist::stdev 34.035908
|
||||
system.ruby.LD.latency_hist | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 233
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 233
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 182
|
||||
system.ruby.LD.miss_latency_hist::mean 59.620879
|
||||
system.ruby.LD.miss_latency_hist::gmean 51.035744
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.307641
|
||||
system.ruby.LD.miss_latency_hist | 41 22.53% 22.53% | 45 24.73% 47.25% | 87 47.80% 95.05% | 7 3.85% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 57.225275
|
||||
system.ruby.LD.miss_latency_hist::gmean 48.520263
|
||||
system.ruby.LD.miss_latency_hist::stdev 29.410954
|
||||
system.ruby.LD.miss_latency_hist | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 182
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 20.806122
|
||||
system.ruby.ST.latency_hist::gmean 7.447374
|
||||
system.ruby.ST.latency_hist::stdev 29.113873
|
||||
system.ruby.ST.latency_hist | 202 68.71% 68.71% | 12 4.08% 72.79% | 0 0.00% 72.79% | 35 11.90% 84.69% | 37 12.59% 97.28% | 7 2.38% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 18.809524
|
||||
system.ruby.ST.latency_hist::gmean 3.456048
|
||||
system.ruby.ST.latency_hist::stdev 29.072895
|
||||
system.ruby.ST.latency_hist | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 202
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 202
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 92
|
||||
system.ruby.ST.miss_latency_hist::mean 59.902174
|
||||
system.ruby.ST.miss_latency_hist::gmean 54.831044
|
||||
system.ruby.ST.miss_latency_hist::stdev 21.909935
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 12 13.04% 13.04% | 0 0.00% 13.04% | 35 38.04% 51.09% | 37 40.22% 91.30% | 7 7.61% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 57.913043
|
||||
system.ruby.ST.miss_latency_hist::gmean 52.615480
|
||||
system.ruby.ST.miss_latency_hist::stdev 21.714254
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 92
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 10.569439
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.165075
|
||||
system.ruby.IFETCH.latency_hist::stdev 24.278647
|
||||
system.ruby.IFETCH.latency_hist | 2341 90.56% 90.56% | 239 9.25% 99.81% | 2 0.08% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.603482
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.551701
|
||||
system.ruby.IFETCH.latency_hist::stdev 24.714457
|
||||
system.ruby.IFETCH.latency_hist | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2315
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2315
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 270
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 75.470370
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 69.413198
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 30.681798
|
||||
system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 73.796296
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 67.113694
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 33.225253
|
||||
system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 270
|
||||
system.ruby.Directory_Controller.GETX 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 385 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 384 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 121 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 464 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 121 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00%
|
||||
|
|
@ -645,7 +645,7 @@ system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00%
|
|||
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 294 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 506 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 508 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 436 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 108 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 20 0.00% 0.00%
|
||||
|
|
@ -659,18 +659,18 @@ system.ruby.L1Cache_Controller.S.Load 108 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.S.Ifetch 2315 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Store 34 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 396 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 9 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 13 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 14 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 14 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 89 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 93 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 84 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 103 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 112 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 94 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 58 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SM.Exclusive_Data 34 0.00% 0.00%
|
||||
|
|
@ -681,43 +681,44 @@ system.ruby.L1Cache_Controller.SI.Writeback_Ack 20 0.00% 0.0
|
|||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 376 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 452 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 92 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 93 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTS_only 396 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 465 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 464 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 78 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 456 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 455 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 108 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 443 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 384 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 45 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_GETX 32 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETS 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETS 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 336 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 335 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 20 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L2_Replacement 29 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L2_Replacement 30 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 16 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 78 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SW.Unblock 20 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 384 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 383 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMLS.Data 34 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.Unblock 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall sigprocmask(1, ...)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:47:59
|
||||
gem5 started Jan 22 2014 17:27:30
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
gem5 compiled Aug 13 2015 19:28:58
|
||||
gem5 started Aug 13 2015 20:16:47
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 43073 because target called exit()
|
||||
Exiting @ tick 40524 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000044 # Number of seconds simulated
|
||||
sim_ticks 43869 # Number of ticks simulated
|
||||
final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000041 # Number of seconds simulated
|
||||
sim_ticks 40524 # Number of ticks simulated
|
||||
final_tick 40524 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 59464 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 59448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1011716 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 453568 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 26896 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 26893 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 422859 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402036 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 #
|
|||
system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 653582256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 653582256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 122546673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 122546673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 776128929 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 776128929 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 707531339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 707531339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 132662126 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 132662126 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 840193466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 840193466 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 448 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 84 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 43790 # Total gap between requests
|
||||
system.mem_ctrls.totGap 40449 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -184,20 +184,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 309.621622 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 203.292189 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 280.679347 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 21 28.38% 28.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 52.70% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 10 13.51% 66.22% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 7 9.46% 75.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 8 10.81% 86.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 3 4.05% 90.54% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.70% 93.24% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 94.59% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 4 5.41% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 73 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 334.027397 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 221.884458 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 291.386817 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 19 26.03% 26.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 15 20.55% 46.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 13 17.81% 64.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 6 8.22% 72.60% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 9.59% 82.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 6.85% 89.04% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 1 1.37% 90.41% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 2 2.74% 93.15% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 73 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes
|
||||
|
|
@ -210,55 +210,55 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
|
|||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2657 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9782 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totQLat 2598 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9723 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgQLat 6.93 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 547.08 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 23.34 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 653.58 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 122.55 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.93 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 592.24 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 25.27 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 707.53 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 132.66 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.46 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.27 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 4.82 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.20 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 294 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.avgWrQLen 21.86 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 297 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 78.40 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.readRowHitRate 79.20 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 82.31 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.avgGap 76.03 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 74.11 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1697280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1896960 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 25360668 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 1267800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 31115508 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 793.965501 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 1987 # Time in different power states
|
||||
system.mem_ctrls_0.actBackEnergy 25074756 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 1518600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 31280076 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 798.164736 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 2492 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 35917 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 35499 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2483520 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2658240 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 26385300 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 369000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 32499228 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 829.273488 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 583 # Time in different power states
|
||||
system.mem_ctrls_1.actBackEnergy 26158212 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 568200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 32704860 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 834.520541 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 821 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 37415 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -294,7 +294,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 43869 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 40524 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -313,7 +313,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 43869 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 40524 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -363,26 +363,26 @@ system.ruby.outstanding_req_hist::total 3295
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 12.317851
|
||||
system.ruby.latency_hist::gmean 3.428799
|
||||
system.ruby.latency_hist::stdev 27.095383
|
||||
system.ruby.latency_hist | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.302368
|
||||
system.ruby.latency_hist::gmean 1.905870
|
||||
system.ruby.latency_hist::stdev 27.097752
|
||||
system.ruby.latency_hist | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 4
|
||||
system.ruby.hit_latency_hist::max_bucket 39
|
||||
system.ruby.hit_latency_hist::samples 2846
|
||||
system.ruby.hit_latency_hist::mean 2.554462
|
||||
system.ruby.hit_latency_hist::gmean 2.127153
|
||||
system.ruby.hit_latency_hist::stdev 3.497278
|
||||
system.ruby.hit_latency_hist::mean 1.554814
|
||||
system.ruby.hit_latency_hist::gmean 1.080771
|
||||
system.ruby.hit_latency_hist::stdev 3.499483
|
||||
system.ruby.hit_latency_hist | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2846
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 448
|
||||
system.ruby.miss_latency_hist::mean 74.341518
|
||||
system.ruby.miss_latency_hist::gmean 71.175015
|
||||
system.ruby.miss_latency_hist::stdev 29.464753
|
||||
system.ruby.miss_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 1 0.22% 99.33% | 3 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 73.225446
|
||||
system.ruby.miss_latency_hist::gmean 70.006194
|
||||
system.ruby.miss_latency_hist::stdev 29.723417
|
||||
system.ruby.miss_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 448
|
||||
system.ruby.Directory.incomplete_times 447
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits
|
||||
|
|
@ -395,7 +395,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 64 # N
|
|||
system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.531811
|
||||
system.ruby.network.routers0.percent_links_utilized 5.988427
|
||||
system.ruby.network.routers0.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70
|
||||
|
|
@ -408,7 +408,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040
|
|||
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64
|
||||
system.ruby.network.routers1.percent_links_utilized 4.129340
|
||||
system.ruby.network.routers1.percent_links_utilized 4.470191
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70
|
||||
|
|
@ -423,7 +423,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers2.percent_links_utilized 3.197588
|
||||
system.ruby.network.routers2.percent_links_utilized 3.461529
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::4 84
|
||||
|
|
@ -434,7 +434,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 32256
|
|||
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers3.percent_links_utilized 4.286246
|
||||
system.ruby.network.routers3.percent_links_utilized 4.640049
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers3.msg_count.Response_Data::4 448
|
||||
|
|
@ -465,7 +465,7 @@ system.ruby.network.msg_byte.Response_Control 24
|
|||
system.ruby.network.msg_byte.Writeback_Data 126576
|
||||
system.ruby.network.msg_byte.Writeback_Control 8760
|
||||
system.ruby.network.msg_byte.Persistent_Control 192
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.319246
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.758316
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
|
||||
|
|
@ -474,21 +474,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256
|
|||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.744375
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.218537
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.744375
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.218537
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.514304
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.721844
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
|
||||
|
|
@ -499,7 +499,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.799676
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.948228
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365
|
||||
|
|
@ -508,24 +508,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632
|
|||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.595500
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.974830
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.314687
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.753381
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers3.throttle1.link_utilization 5.744375
|
||||
system.ruby.network.routers3.throttle1.link_utilization 6.218537
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.799676
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.948228
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365
|
||||
|
|
@ -534,100 +534,100 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632
|
|||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 27.568675
|
||||
system.ruby.LD.latency_hist::gmean 8.538256
|
||||
system.ruby.LD.latency_hist::stdev 33.282054
|
||||
system.ruby.LD.latency_hist | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 67 16.14% 92.29% | 19 4.58% 96.87% | 11 2.65% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 26.997590
|
||||
system.ruby.LD.latency_hist::gmean 5.744725
|
||||
system.ruby.LD.latency_hist::stdev 35.628552
|
||||
system.ruby.LD.latency_hist | 266 64.10% 64.10% | 50 12.05% 76.14% | 86 20.72% 96.87% | 10 2.41% 99.28% | 2 0.48% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 4
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 39
|
||||
system.ruby.LD.hit_latency_hist::samples 266
|
||||
system.ruby.LD.hit_latency_hist::mean 4.830827
|
||||
system.ruby.LD.hit_latency_hist::gmean 2.733388
|
||||
system.ruby.LD.hit_latency_hist::stdev 7.539428
|
||||
system.ruby.LD.hit_latency_hist::mean 3.834586
|
||||
system.ruby.LD.hit_latency_hist::gmean 1.482071
|
||||
system.ruby.LD.hit_latency_hist::stdev 7.549265
|
||||
system.ruby.LD.hit_latency_hist | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 266
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 149
|
||||
system.ruby.LD.miss_latency_hist::mean 68.161074
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.233010
|
||||
system.ruby.LD.miss_latency_hist::stdev 20.215751
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 67 44.97% 78.52% | 19 12.75% 91.28% | 11 7.38% 98.66% | 0 0.00% 98.66% | 1 0.67% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 68.348993
|
||||
system.ruby.LD.miss_latency_hist::gmean 64.521093
|
||||
system.ruby.LD.miss_latency_hist::stdev 27.623170
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 149
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 13.656463
|
||||
system.ruby.ST.latency_hist::gmean 4.101596
|
||||
system.ruby.ST.latency_hist::stdev 23.959601
|
||||
system.ruby.ST.latency_hist | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 22 7.48% 97.62% | 7 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 12.608844
|
||||
system.ruby.ST.latency_hist::gmean 2.382135
|
||||
system.ruby.ST.latency_hist::stdev 23.834900
|
||||
system.ruby.ST.latency_hist | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 4
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 39
|
||||
system.ruby.ST.hit_latency_hist::samples 242
|
||||
system.ruby.ST.hit_latency_hist::mean 3.223140
|
||||
system.ruby.ST.hit_latency_hist::gmean 2.303884
|
||||
system.ruby.ST.hit_latency_hist::mean 2.223140
|
||||
system.ruby.ST.hit_latency_hist::gmean 1.195990
|
||||
system.ruby.ST.hit_latency_hist::stdev 4.967926
|
||||
system.ruby.ST.hit_latency_hist | 228 94.21% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 7 2.89% 97.11% | 7 2.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 242
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 52
|
||||
system.ruby.ST.miss_latency_hist::mean 62.211538
|
||||
system.ruby.ST.miss_latency_hist::gmean 60.076620
|
||||
system.ruby.ST.miss_latency_hist::stdev 16.157723
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 22 42.31% 86.54% | 7 13.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 60.942308
|
||||
system.ruby.ST.miss_latency_hist::gmean 58.827137
|
||||
system.ruby.ST.miss_latency_hist::stdev 15.919421
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 52
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 9.717215
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.901893
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.469799
|
||||
system.ruby.IFETCH.latency_hist | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.634043
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.556496
|
||||
system.ruby.IFETCH.latency_hist::stdev 24.921625
|
||||
system.ruby.IFETCH.latency_hist | 2338 90.44% 90.44% | 243 9.40% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 4
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 39
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2338
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 2.226262
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 2.050316
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1.226262
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1.031758
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev 2.270469
|
||||
system.ruby.IFETCH.hit_latency_hist | 2315 99.02% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2338
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 247
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 80.623482
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 77.743783
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 34.404574
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 78.753036
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 76.281493
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 31.886864
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 247
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::samples 2776
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 2
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 2776 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 2776 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::total 2776
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 4
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 39
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::samples 70
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 24.542857
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 24.511430
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.200069
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 23.557143
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 23.524270
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.199465
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 70
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 448
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 74.341518
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 71.175015
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 29.464753
|
||||
system.ruby.Directory.miss_mach_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 1 0.22% 99.33% | 3 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 73.225446
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 70.006194
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 29.723417
|
||||
system.ruby.Directory.miss_mach_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 448
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -650,78 +650,78 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 83
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 83.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 82
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 82.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 233
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 233
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 33
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 24.818182
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 24.809790
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 0.635145
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 23.848485
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 23.840140
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 0.618527
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 33
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 149
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 68.161074
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.233010
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 20.215751
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 67 44.97% 78.52% | 19 12.75% 91.28% | 11 7.38% 98.66% | 0 0.00% 98.66% | 1 0.67% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 68.348993
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 64.521093
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 27.623170
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 149
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 228
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 228 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 228 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 228
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 14
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 23.142857
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 23.062251
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 22.142857
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 22.058564
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 1.994498
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 14
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 52
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.211538
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 60.076620
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 16.157723
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 22 42.31% 86.54% | 7 13.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 60.942308
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 58.827137
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.919421
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 52
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 2315
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 2315
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 23
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 25
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 25.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 24
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 24.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 23 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 23
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 247
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 80.623482
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.743783
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.404574
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 78.753036
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 76.281493
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 31.886864
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247
|
||||
system.ruby.Directory_Controller.GETX 61 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 398 0.00% 0.00%
|
||||
|
|
@ -767,20 +767,20 @@ system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1150 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1099 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 104 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1007 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1058 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 92 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 93 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 69 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data_All_Tokens 58 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall sigprocmask(1, ...)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:32:54
|
||||
gem5 started Jan 22 2014 17:25:27
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
gem5 compiled Aug 13 2015 19:09:46
|
||||
gem5 started Aug 13 2015 20:15:17
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 35432 because target called exit()
|
||||
Exiting @ tick 32936 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000036 # Number of seconds simulated
|
||||
sim_ticks 36238 # Number of ticks simulated
|
||||
final_tick 36238 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32936 # Number of ticks simulated
|
||||
final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 67399 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 67374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 947126 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 452704 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 21294 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 21292 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 272103 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401708 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 #
|
|||
system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 778850930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 778850930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 143054252 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 143054252 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 921905182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 921905182 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 856934661 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 856934661 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 157396162 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 157396162 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1014330823 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1014330823 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 441 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 81 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 36170 # Total gap between requests
|
||||
system.mem_ctrls.totGap 32872 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -185,17 +185,17 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 349.611940 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 229.746544 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 299.426571 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 17 25.37% 25.37% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 14 20.90% 46.27% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 61.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 5 7.46% 68.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 10.45% 79.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 7.46% 86.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 4 5.97% 92.54% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 1 1.49% 94.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 358.208955 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 229.774303 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 311.560906 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 18 26.87% 26.87% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 13 19.40% 46.27% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 8 11.94% 58.21% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 68.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 5 7.46% 76.12% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 6 8.96% 85.07% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.99% 88.06% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 4 5.97% 94.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
|
|
@ -210,55 +210,55 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
|
|||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2372 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9497 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totQLat 2381 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9506 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.33 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgQLat 6.35 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.33 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 662.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 28.26 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 778.85 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 143.05 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 25.35 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 728.69 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 31.09 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 856.93 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 157.40 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 5.39 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.17 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.22 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 5.94 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.69 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.24 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.52 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 301 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.27 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 69.29 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1634880 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.avgGap 62.97 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 151200 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 84000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1859520 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 20835324 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 565800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 25293684 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 805.428735 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 845 # Time in different power states
|
||||
system.mem_ctrls_0.actBackEnergy 21272400 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 182400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 25583760 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 814.665648 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 206 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 29533 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 30172 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 309960 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 172200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2446080 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2620800 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 21069936 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 360000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 26558304 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 845.698128 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states
|
||||
system.mem_ctrls_1.actBackEnergy 20904408 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 505200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 26783256 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 852.861292 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1046 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 29876 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -294,7 +294,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 36238 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 32936 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -313,7 +313,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 36238 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 32936 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -363,26 +363,26 @@ system.ruby.outstanding_req_hist::total 3295
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 10.001214
|
||||
system.ruby.latency_hist::gmean 3.249510
|
||||
system.ruby.latency_hist::stdev 22.284852
|
||||
system.ruby.latency_hist | 3202 97.21% 97.21% | 88 2.67% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.09% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 8.998786
|
||||
system.ruby.latency_hist::gmean 1.800750
|
||||
system.ruby.latency_hist::stdev 22.386902
|
||||
system.ruby.latency_hist | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 2
|
||||
system.ruby.hit_latency_hist::max_bucket 19
|
||||
system.ruby.hit_latency_hist::samples 2853
|
||||
system.ruby.hit_latency_hist::mean 2.241851
|
||||
system.ruby.hit_latency_hist::gmean 2.088573
|
||||
system.ruby.hit_latency_hist::mean 1.241851
|
||||
system.ruby.hit_latency_hist::gmean 1.059708
|
||||
system.ruby.hit_latency_hist::stdev 1.536503
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2853
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 441
|
||||
system.ruby.miss_latency_hist::mean 60.199546
|
||||
system.ruby.miss_latency_hist::gmean 56.719819
|
||||
system.ruby.miss_latency_hist::stdev 28.025250
|
||||
system.ruby.miss_latency_hist | 349 79.14% 79.14% | 88 19.95% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 3 0.68% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 59.181406
|
||||
system.ruby.miss_latency_hist::gmean 55.608631
|
||||
system.ruby.miss_latency_hist::stdev 28.659343
|
||||
system.ruby.miss_latency_hist | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 441
|
||||
system.ruby.Directory.incomplete_times 440
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
|
|
@ -397,9 +397,9 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.fully_busy_cycles 11 # cycles for which number of transistions == max transitions
|
||||
system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 4.672581
|
||||
system.ruby.network.routers0.percent_links_utilized 5.141031
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -414,7 +414,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers1.percent_links_utilized 4.672581
|
||||
system.ruby.network.routers1.percent_links_utilized 5.141031
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -429,7 +429,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers2.percent_links_utilized 4.672581
|
||||
system.ruby.network.routers2.percent_links_utilized 5.141031
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -454,12 +454,12 @@ system.ruby.network.msg_byte.Response_Data 95256
|
|||
system.ruby.network.msg_byte.Writeback_Data 17496
|
||||
system.ruby.network.msg_byte.Writeback_Control 28656
|
||||
system.ruby.network.msg_byte.Unblock_Control 10560
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.062697
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.670513
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.282466
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.611550
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -470,7 +470,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.282466
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.611550
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -481,17 +481,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.062697
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.670513
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.062697
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.670513
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.282466
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.611550
|
||||
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -502,99 +502,99 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 22.067470
|
||||
system.ruby.LD.latency_hist::gmean 7.299119
|
||||
system.ruby.LD.latency_hist::stdev 32.750562
|
||||
system.ruby.LD.latency_hist | 313 75.42% 75.42% | 69 16.63% 92.05% | 31 7.47% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 19.850602
|
||||
system.ruby.LD.latency_hist::gmean 4.833066
|
||||
system.ruby.LD.latency_hist::stdev 26.151303
|
||||
system.ruby.LD.latency_hist | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 2
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 19
|
||||
system.ruby.LD.hit_latency_hist::samples 269
|
||||
system.ruby.LD.hit_latency_hist::mean 3.338290
|
||||
system.ruby.LD.hit_latency_hist::gmean 2.541963
|
||||
system.ruby.LD.hit_latency_hist::mean 2.338290
|
||||
system.ruby.LD.hit_latency_hist::gmean 1.378379
|
||||
system.ruby.LD.hit_latency_hist::stdev 3.411031
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 269
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::samples 146
|
||||
system.ruby.LD.miss_latency_hist::mean 56.575342
|
||||
system.ruby.LD.miss_latency_hist::gmean 50.969029
|
||||
system.ruby.LD.miss_latency_hist::stdev 34.513533
|
||||
system.ruby.LD.miss_latency_hist | 44 30.14% 30.14% | 69 47.26% 77.40% | 31 21.23% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 2 1.37% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 52.116438
|
||||
system.ruby.LD.miss_latency_hist::gmean 48.763829
|
||||
system.ruby.LD.miss_latency_hist::stdev 17.717519
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 146
|
||||
system.ruby.ST.latency_hist::bucket_size 8
|
||||
system.ruby.ST.latency_hist::max_bucket 79
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 10.251701
|
||||
system.ruby.ST.latency_hist::gmean 3.559470
|
||||
system.ruby.ST.latency_hist::stdev 19.106793
|
||||
system.ruby.ST.latency_hist | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 4 1.36% 97.96% | 6 2.04% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 10.064626
|
||||
system.ruby.ST.latency_hist::gmean 2.035894
|
||||
system.ruby.ST.latency_hist::stdev 25.936505
|
||||
system.ruby.ST.latency_hist | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 2
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 19
|
||||
system.ruby.ST.hit_latency_hist::samples 247
|
||||
system.ruby.ST.hit_latency_hist::mean 2.445344
|
||||
system.ruby.ST.hit_latency_hist::gmean 2.166130
|
||||
system.ruby.ST.hit_latency_hist::mean 1.445344
|
||||
system.ruby.ST.hit_latency_hist::gmean 1.112699
|
||||
system.ruby.ST.hit_latency_hist::stdev 2.066980
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 247
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 8
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 79
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 47
|
||||
system.ruby.ST.miss_latency_hist::mean 51.276596
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.413040
|
||||
system.ruby.ST.miss_latency_hist::stdev 15.988722
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 4 8.51% 87.23% | 6 12.77% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 55.361702
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.711518
|
||||
system.ruby.ST.miss_latency_hist::stdev 42.031265
|
||||
system.ruby.ST.miss_latency_hist | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 47
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 8.035590
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.824197
|
||||
system.ruby.IFETCH.latency_hist::stdev 19.808514
|
||||
system.ruby.IFETCH.latency_hist | 2536 98.10% 98.10% | 47 1.82% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.04% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 7.135397
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.515500
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.744191
|
||||
system.ruby.IFETCH.latency_hist | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2337
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 2.094138
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 2.034021
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1.094138
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1.022830
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev 0.965875
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2337
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 248
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 64.024194
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 62.244534
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 24.791752
|
||||
system.ruby.IFETCH.miss_latency_hist | 199 80.24% 80.24% | 47 18.95% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 64.064516
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 61.606137
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 29.893804
|
||||
system.ruby.IFETCH.miss_latency_hist | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 248
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::samples 2784
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 2
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::mean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::gmean 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::total 2784
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 2
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 19
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::samples 69
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 12
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 11
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 69
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 441
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 60.199546
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 56.719819
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 28.025250
|
||||
system.ruby.Directory.miss_mach_latency_hist | 349 79.14% 79.14% | 88 19.95% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 3 0.68% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 59.181406
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 55.608631
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 28.659343
|
||||
system.ruby.Directory.miss_mach_latency_hist | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 441
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -625,71 +625,71 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total
|
|||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 233
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 233
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 36
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 36
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 146
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 56.575342
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 50.969029
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 34.513533
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 44 30.14% 30.14% | 69 47.26% 77.40% | 31 21.23% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 2 1.37% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.116438
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 48.763829
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 17.717519
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 146
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 236
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 236
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 11
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 11
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 8
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 79
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 47
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.276596
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.413040
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.988722
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 4 8.51% 87.23% | 6 12.77% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.361702
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.711518
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 42.031265
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 47
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::samples 2315
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 2
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 2.000000
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::mean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::total 2315
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::max_bucket 19
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::samples 22
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 12
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 12.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 11
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 11.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 22
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 248
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 64.024194
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.244534
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 24.791752
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 199 80.24% 80.24% | 47 18.95% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 64.064516
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.606137
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 29.893804
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248
|
||||
system.ruby.Directory_Controller.GETX 51 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 409 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 410 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUT 425 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
|
|
@ -705,7 +705,7 @@ system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00%
|
|||
system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Load 422 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,6 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ignoring syscall sigprocmask(1, ...)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:30
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
|
||||
gem5 compiled Aug 13 2015 19:05:56
|
||||
gem5 started Aug 13 2015 20:14:52
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 52498 because target called exit()
|
||||
Exiting @ tick 41659 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000047 # Number of seconds simulated
|
||||
sim_ticks 47487 # Number of ticks simulated
|
||||
final_tick 47487 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000042 # Number of seconds simulated
|
||||
sim_ticks 41659 # Number of ticks simulated
|
||||
final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 68488 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68466 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1261208 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449476 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 30850 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30846 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 498580 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 399460 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 #
|
|||
system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 843683534 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 843683534 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 838292585 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 838292585 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1681976120 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1681976120 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 961712955 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 961712955 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 955567824 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 955567824 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917280780 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1917280780 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 626 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 622 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24640 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 15424 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 24960 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 15104 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 24000 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 227 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 236 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 219 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 58 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 62 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 54 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 47448 # Total gap between requests
|
||||
system.mem_ctrls.totGap 41626 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 385 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 390 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -135,25 +135,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 18 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,88 +184,87 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 424.212389 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 291.141419 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 329.481775 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 17 15.04% 15.04% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 29 25.66% 40.71% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 14 12.39% 53.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 9 7.96% 61.06% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 9 7.96% 69.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 10 8.85% 77.88% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 4 3.54% 88.50% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 13 11.50% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.622974 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 4.396969 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 9.09% 9.09% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 7 31.82% 40.91% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 7 31.82% 72.73% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.592012 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.292670 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 4.55% 81.82% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 13.64% 95.45% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::20 1 4.55% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 3756 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11071 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1925 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 9.76 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 105 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 455.923810 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 317.170384 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 344.729986 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 11 10.48% 10.48% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 29 27.62% 38.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 10 9.52% 47.62% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 10 9.52% 57.14% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 14 13.33% 70.48% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 4.76% 75.24% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 4 3.81% 79.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 4.76% 83.81% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 17 16.19% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 105 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.434783 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.058223 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 4.388270 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 3 13.04% 13.04% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 10 43.48% 56.52% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 5 21.74% 78.26% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 17.39% 95.65% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 4.35% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 23 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.304348 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.283756 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.875670 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 20 86.96% 86.96% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 4.35% 91.30% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 2 8.70% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 23 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 4371 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11781 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1950 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 11.21 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 28.76 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 518.88 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 493.27 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 843.68 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 838.29 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 30.21 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 599.15 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 576.11 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 961.71 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 955.57 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.91 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.05 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.85 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 9.18 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.68 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.50 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.54 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 294 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 76.36 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 86.58 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 38.02 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 81.54 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 257040 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 142800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 2046720 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 1638144 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 30869604 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 1107000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 39112668 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 832.609588 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 1942 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 24.82 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 298 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 355 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 76.41 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 33.35 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 82.35 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 130200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 1555200 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 26028252 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 682200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 33144852 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 845.747691 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 1011 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 43739 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 36893 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 597240 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 331800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2733120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 2156544 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 31287528 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 740400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 40897992 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 870.614612 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1080 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 536760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 298200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 2608320 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 2166912 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 26345628 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 403800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 34902420 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 890.595050 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 832 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 44350 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -301,7 +300,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 47487 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 41659 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -320,7 +319,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 47487 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 41659 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -375,32 +374,32 @@ system.ruby.outstanding_req_hist::total 3295
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 13.416211
|
||||
system.ruby.latency_hist::gmean 5.177559
|
||||
system.ruby.latency_hist::stdev 25.037672
|
||||
system.ruby.latency_hist | 3186 96.72% 96.72% | 90 2.73% 99.45% | 15 0.46% 99.91% | 0 0.00% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.646934
|
||||
system.ruby.latency_hist::gmean 2.114776
|
||||
system.ruby.latency_hist::stdev 26.263922
|
||||
system.ruby.latency_hist | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 2668
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2668
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 626
|
||||
system.ruby.miss_latency_hist::mean 57.809904
|
||||
system.ruby.miss_latency_hist::gmean 52.994493
|
||||
system.ruby.miss_latency_hist::stdev 29.424898
|
||||
system.ruby.miss_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 57.023962
|
||||
system.ruby.miss_latency_hist::gmean 51.467697
|
||||
system.ruby.miss_latency_hist::stdev 32.986607
|
||||
system.ruby.miss_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 626
|
||||
system.ruby.Directory.incomplete_times 625
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.570219
|
||||
system.ruby.network.routers0.percent_links_utilized 7.489378
|
||||
system.ruby.network.routers0.msg_count.Control::2 626
|
||||
system.ruby.network.routers0.msg_count.Data::2 622
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 626
|
||||
|
|
@ -409,7 +408,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers1.percent_links_utilized 6.570219
|
||||
system.ruby.network.routers1.percent_links_utilized 7.489378
|
||||
system.ruby.network.routers1.msg_count.Control::2 626
|
||||
system.ruby.network.routers1.msg_count.Data::2 622
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 626
|
||||
|
|
@ -418,7 +417,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.percent_links_utilized 6.570219
|
||||
system.ruby.network.routers2.percent_links_utilized 7.489378
|
||||
system.ruby.network.routers2.msg_count.Control::2 626
|
||||
system.ruby.network.routers2.msg_count.Data::2 622
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 626
|
||||
|
|
@ -435,32 +434,32 @@ system.ruby.network.msg_byte.Control 15024
|
|||
system.ruby.network.msg_byte.Data 134352
|
||||
system.ruby.network.msg_byte.Response_Data 135216
|
||||
system.ruby.network.msg_byte.Writeback_Control 14928
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.587066
|
||||
system.ruby.network.routers0.throttle0.link_utilization 7.508582
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.553373
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.470175
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 626
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 622
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.553373
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.470175
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 626
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 622
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.587066
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.508582
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.587066
|
||||
system.ruby.network.routers2.throttle0.link_utilization 7.508582
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.553373
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.470175
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 626
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 622
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008
|
||||
|
|
@ -475,82 +474,82 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 33.036145
|
||||
system.ruby.LD.latency_hist::gmean 15.653569
|
||||
system.ruby.LD.latency_hist::stdev 33.343638
|
||||
system.ruby.LD.latency_hist | 375 90.36% 90.36% | 35 8.43% 98.80% | 4 0.96% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 30.537349
|
||||
system.ruby.LD.latency_hist::gmean 9.686440
|
||||
system.ruby.LD.latency_hist::stdev 30.265140
|
||||
system.ruby.LD.latency_hist | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 170
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 170
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 245
|
||||
system.ruby.LD.miss_latency_hist::mean 53.877551
|
||||
system.ruby.LD.miss_latency_hist::gmean 49.256670
|
||||
system.ruby.LD.miss_latency_hist::stdev 28.665419
|
||||
system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 51.032653
|
||||
system.ruby.LD.miss_latency_hist::gmean 46.821080
|
||||
system.ruby.LD.miss_latency_hist::stdev 22.902478
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 245
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 17.955782
|
||||
system.ruby.ST.latency_hist::gmean 6.677068
|
||||
system.ruby.ST.latency_hist::stdev 30.544793
|
||||
system.ruby.ST.latency_hist | 210 71.43% 71.43% | 73 24.83% 96.26% | 7 2.38% 98.64% | 0 0.00% 98.64% | 3 1.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 16.663265
|
||||
system.ruby.ST.latency_hist::gmean 3.036238
|
||||
system.ruby.ST.latency_hist::stdev 32.952425
|
||||
system.ruby.ST.latency_hist | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 210
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 210
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 84
|
||||
system.ruby.ST.miss_latency_hist::mean 55.345238
|
||||
system.ruby.ST.miss_latency_hist::gmean 49.345449
|
||||
system.ruby.ST.miss_latency_hist::stdev 36.232680
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 55.821429
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.772534
|
||||
system.ruby.ST.miss_latency_hist::stdev 40.751129
|
||||
system.ruby.ST.miss_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 84
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 9.750097
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.211373
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.913083
|
||||
system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 240 9.28% 97.79% | 46 1.78% 99.57% | 2 0.08% 99.65% | 2 0.08% 99.73% | 6 0.23% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.043714
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.589638
|
||||
system.ruby.IFETCH.latency_hist::stdev 23.152025
|
||||
system.ruby.IFETCH.latency_hist | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 2288
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2288
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 297
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 61.750842
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 57.437802
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 27.433554
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 62.306397
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 56.498895
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 36.624977
|
||||
system.ruby.IFETCH.miss_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 297
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 626
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 57.809904
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 52.994493
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 29.424898
|
||||
system.ruby.Directory.miss_mach_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 57.023962
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 51.467697
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 32.986607
|
||||
system.ruby.Directory.miss_mach_latency_hist | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 626
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -578,29 +577,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.877551
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.256670
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.665419
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.032653
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.821080
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.902478
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.345238
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.345449
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.232680
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.821429
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.772534
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 40.751129
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.750842
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 57.437802
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.433554
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 62.306397
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 56.498895
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.624977
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297
|
||||
system.ruby.Directory_Controller.GETX 626 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 622 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,9 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:53:01
|
||||
gem5 started Jan 22 2014 17:28:34
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
|
||||
gem5 compiled Aug 13 2015 19:34:57
|
||||
gem5 started Aug 13 2015 20:18:18
|
||||
gem5 executing on artery
|
||||
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 125334 because target called exit()
|
||||
Exiting @ tick 100307 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000115 # Number of seconds simulated
|
||||
sim_ticks 115089 # Number of ticks simulated
|
||||
final_tick 115089 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000100 # Number of seconds simulated
|
||||
sim_ticks 100307 # Number of ticks simulated
|
||||
final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 64252 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64242 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1314462 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449728 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 40999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 40995 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 731101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 399732 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 #
|
|||
system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 817454318 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 817454318 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 815229952 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 815229952 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1632684270 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1632684270 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 937920584 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 937920584 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 935368419 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 935368419 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1873289003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1873289003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1470 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1466 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 58496 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 35584 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 59392 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 58560 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 35520 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 59456 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 556 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 513 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 516 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 78 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 64 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 241 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 243 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 115 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 165 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 33 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 113 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 160 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 9 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 245 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 98 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 186 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 83 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 239 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 97 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 117 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 176 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 11 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 115018 # Total gap between requests
|
||||
system.mem_ctrls.totGap 100258 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 914 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 915 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 15 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 58 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 58 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 54 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 61 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 62 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,89 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 343 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 339.965015 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 217.922152 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 320.777927 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 88 25.66% 25.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 98 28.57% 54.23% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 42 12.24% 66.47% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 32 9.33% 75.80% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 16 4.66% 80.47% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 13 3.79% 84.26% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 8 2.33% 86.59% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 1.46% 88.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 41 11.95% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 343 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 56 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.125000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.967614 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.737368 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 3.57% 3.57% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 19 33.93% 37.50% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 27 48.21% 85.71% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 7 12.50% 98.21% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 1.79% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 56 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 56 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.571429 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.541189 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.041976 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 41 73.21% 73.21% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 3 5.36% 78.57% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 8 14.29% 92.86% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 5.36% 98.21% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::20 1 1.79% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 56 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 12397 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 29763 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4570 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 13.56 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 346 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 337.017341 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 221.831279 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 312.425842 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 75 21.68% 21.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 111 32.08% 53.76% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 54 15.61% 69.36% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 22 6.36% 75.72% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 14 4.05% 79.77% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 16 4.62% 84.39% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 11 3.18% 87.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 8 2.31% 89.88% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 35 10.12% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 346 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 15.982456 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.826931 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.722205 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.298246 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.275827 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.905635 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 51 89.47% 89.47% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 3.51% 92.98% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 12902 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 30287 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4575 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 14.10 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 32.56 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 508.27 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 516.05 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 817.45 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 815.23 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 33.10 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 583.81 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 592.74 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 937.92 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 935.37 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 8.00 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.03 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 9.19 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.56 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.63 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.10 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 631 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 861 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 69.04 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 39.18 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.91 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 544320 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 302400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1522560 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 1202688 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 49529808 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 22111200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 82332816 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 753.521892 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 36376 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 25.61 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 68.52 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 91.05 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 34.15 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 80.00 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 1497600 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 1254528 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 47014056 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 14974800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 71631624 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 764.543654 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 25717 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 69262 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 71078 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1988280 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 1104600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 9397440 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 8076672 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 74119608 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 541200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 102347640 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 936.700469 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1950480 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 1083600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 9197760 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 7713792 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 63796680 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 253200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 90098232 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 961.642744 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 100 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 105142 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 90486 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
|
|
@ -288,7 +287,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 115089 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 100307 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5624 # Number of instructions committed
|
||||
|
|
@ -307,7 +306,7 @@ system.cpu.num_mem_refs 2034 # nu
|
|||
system.cpu.num_load_insts 1132 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 115089 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 100307 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 883 # Number of branches fetched
|
||||
|
|
@ -362,32 +361,32 @@ system.ruby.outstanding_req_hist::total 7659
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 7658
|
||||
system.ruby.latency_hist::mean 14.028598
|
||||
system.ruby.latency_hist::gmean 5.234161
|
||||
system.ruby.latency_hist::stdev 27.167008
|
||||
system.ruby.latency_hist | 7344 95.90% 95.90% | 261 3.41% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 9 0.12% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 12.098329
|
||||
system.ruby.latency_hist::gmean 2.138684
|
||||
system.ruby.latency_hist::stdev 27.490264
|
||||
system.ruby.latency_hist | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 7658
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 6188
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6188
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1470
|
||||
system.ruby.miss_latency_hist::mean 60.453741
|
||||
system.ruby.miss_latency_hist::gmean 54.500138
|
||||
system.ruby.miss_latency_hist::stdev 34.320124
|
||||
system.ruby.miss_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 58.817007
|
||||
system.ruby.miss_latency_hist::gmean 52.469450
|
||||
system.ruby.miss_latency_hist::stdev 35.158300
|
||||
system.ruby.miss_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1470
|
||||
system.ruby.Directory.incomplete_times 1469
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.377673
|
||||
system.ruby.network.routers0.percent_links_utilized 7.317535
|
||||
system.ruby.network.routers0.msg_count.Control::2 1470
|
||||
system.ruby.network.routers0.msg_count.Data::2 1466
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1470
|
||||
|
|
@ -396,7 +395,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers1.percent_links_utilized 6.377673
|
||||
system.ruby.network.routers1.percent_links_utilized 7.317535
|
||||
system.ruby.network.routers1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1470
|
||||
|
|
@ -405,7 +404,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.percent_links_utilized 6.377673
|
||||
system.ruby.network.routers2.percent_links_utilized 7.317535
|
||||
system.ruby.network.routers2.msg_count.Control::2 1470
|
||||
system.ruby.network.routers2.msg_count.Data::2 1466
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1470
|
||||
|
|
@ -422,32 +421,32 @@ system.ruby.network.msg_byte.Control 35280
|
|||
system.ruby.network.msg_byte.Data 316656
|
||||
system.ruby.network.msg_byte.Response_Data 317520
|
||||
system.ruby.network.msg_byte.Writeback_Control 35184
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.384624
|
||||
system.ruby.network.routers0.throttle0.link_utilization 7.325511
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.370722
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.309560
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.370722
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.309560
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.384624
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.325511
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.384624
|
||||
system.ruby.network.routers2.throttle0.link_utilization 7.325511
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.370722
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.309560
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
|
||||
|
|
@ -462,82 +461,82 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 1132
|
||||
system.ruby.LD.latency_hist::mean 35.838339
|
||||
system.ruby.LD.latency_hist::gmean 16.062923
|
||||
system.ruby.LD.latency_hist::stdev 41.117345
|
||||
system.ruby.LD.latency_hist | 998 88.16% 88.16% | 109 9.63% 97.79% | 13 1.15% 98.94% | 2 0.18% 99.12% | 7 0.62% 99.73% | 3 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 33.356007
|
||||
system.ruby.LD.latency_hist::gmean 9.984943
|
||||
system.ruby.LD.latency_hist::stdev 37.413851
|
||||
system.ruby.LD.latency_hist | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1132
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 465
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 465
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 667
|
||||
system.ruby.LD.miss_latency_hist::mean 58.731634
|
||||
system.ruby.LD.miss_latency_hist::gmean 51.741753
|
||||
system.ruby.LD.miss_latency_hist::stdev 39.915394
|
||||
system.ruby.LD.miss_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 55.913043
|
||||
system.ruby.LD.miss_latency_hist::gmean 49.663893
|
||||
system.ruby.LD.miss_latency_hist::stdev 33.713440
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 667
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 901
|
||||
system.ruby.ST.latency_hist::mean 14.653718
|
||||
system.ruby.ST.latency_hist::gmean 5.820052
|
||||
system.ruby.ST.latency_hist::stdev 24.674998
|
||||
system.ruby.ST.latency_hist | 684 75.92% 75.92% | 188 20.87% 96.78% | 26 2.89% 99.67% | 0 0.00% 99.67% | 0 0.00% 99.67% | 1 0.11% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 12.753607
|
||||
system.ruby.ST.latency_hist::gmean 2.500911
|
||||
system.ruby.ST.latency_hist::stdev 24.939066
|
||||
system.ruby.ST.latency_hist | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 901
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 684
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 684
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 217
|
||||
system.ruby.ST.miss_latency_hist::mean 51.387097
|
||||
system.ruby.ST.miss_latency_hist::gmean 47.001474
|
||||
system.ruby.ST.miss_latency_hist::stdev 27.408897
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 49.801843
|
||||
system.ruby.ST.miss_latency_hist::gmean 44.971096
|
||||
system.ruby.ST.miss_latency_hist::stdev 27.840525
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 217
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 5625
|
||||
system.ruby.IFETCH.latency_hist::mean 9.539378
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.106431
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.247440
|
||||
system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 435 7.73% 97.32% | 121 2.15% 99.47% | 5 0.09% 99.56% | 8 0.14% 99.70% | 15 0.27% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 7.715378
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.529642
|
||||
system.ruby.IFETCH.latency_hist::stdev 23.186705
|
||||
system.ruby.IFETCH.latency_hist | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 5625
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 5039
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5039
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 586
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.771331
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 61.076979
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 28.360902
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.460751
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 59.138692
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 37.945521
|
||||
system.ruby.IFETCH.miss_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 586
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1470
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 60.453741
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 54.500138
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 34.320124
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 58.817007
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 52.469450
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 35.158300
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1470
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -565,29 +564,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.731634
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 51.741753
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 39.915394
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 55.913043
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.663893
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.713440
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.387097
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.001474
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.408897
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 49.801843
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.971096
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.840525
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.771331
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.076979
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.360902
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.460751
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 59.138692
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.945521
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586
|
||||
system.ruby.Directory_Controller.GETX 1470 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
|
||||
Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 15 2014 16:11:41
|
||||
gem5 started Feb 15 2014 16:12:47
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
|
||||
gem5 compiled Aug 13 2015 19:50:15
|
||||
gem5 started Aug 13 2015 20:18:47
|
||||
gem5 executing on artery
|
||||
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello World!Exiting @ tick 107952 because target called exit()
|
||||
Hello World!Exiting @ tick 81703 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000095 # Number of seconds simulated
|
||||
sim_ticks 95241 # Number of ticks simulated
|
||||
final_tick 95241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000082 # Number of seconds simulated
|
||||
sim_ticks 81703 # Number of ticks simulated
|
||||
final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 71470 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71456 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1277340 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449880 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 27632 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27631 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 423765 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 400152 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 #
|
|||
system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 866181581 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 866181581 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 863493663 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 863493663 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1729675245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1729675245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1009705886 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1009705886 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1006572586 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 1006572586 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2016278472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 2016278472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1289 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1285 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 43328 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 39168 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 43904 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 43904 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 38592 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 43776 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 612 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 580 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 603 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 579 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::0 28 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 113 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 123 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 119 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 115 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 134 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 58 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 9 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 113 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 127 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 117 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 112 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 138 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 56 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 14 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 9 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 13 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 95177 # Total gap between requests
|
||||
system.mem_ctrls.totGap 81643 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 677 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 686 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -137,11 +137,11 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 34 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 48 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see
|
||||
|
|
@ -184,92 +184,93 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 241 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 353.991701 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 236.521382 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 306.711183 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 49 20.33% 20.33% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 67 27.80% 48.13% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 30 12.45% 60.58% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 30 12.45% 73.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 18 7.47% 80.50% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 7 2.90% 83.40% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 9 3.73% 87.14% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 14 5.81% 92.95% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 17 7.05% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 241 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::samples 227 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 379.207048 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 252.014148 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 323.708826 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 44 19.38% 19.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 63 27.75% 47.14% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 29 12.78% 59.91% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 17 7.49% 67.40% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 17 7.49% 74.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 17 7.49% 82.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 9 3.96% 86.34% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 6 2.64% 88.99% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 25 11.01% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 227 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 42 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.047619 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.828866 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.297837 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 1 2.38% 2.38% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 18 42.86% 45.24% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 17 40.48% 85.71% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 5 11.90% 97.62% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.190476 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.978361 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.255300 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 3 7.14% 7.14% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 10 23.81% 30.95% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 26 61.90% 92.86% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 1 2.38% 95.24% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 1 2.38% 97.62% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.38% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 42 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 42 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.313589 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.845841 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 35 83.33% 83.33% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 3 7.14% 90.48% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 1 2.38% 92.86% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 7.14% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.285714 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.270299 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.741972 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 36 85.71% 85.71% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 2.38% 88.10% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 4 9.52% 97.62% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 2.38% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 42 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 8633 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 21496 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3385 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 12.75 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.totQLat 8350 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 21384 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3430 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 12.17 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 31.75 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 454.93 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 460.98 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 866.18 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 863.49 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 31.17 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 537.36 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 535.79 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1009.71 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 1006.57 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.16 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.55 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.60 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 8.38 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.20 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.19 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.53 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 621 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 73.26 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 36.98 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 80.82 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 634200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 5079360 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 4178304 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 60945084 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 2754600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 80835828 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 862.782607 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 4199 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 503 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 73.32 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 89.94 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 31.72 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 960120 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 533400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 3981312 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 5085600 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 48305448 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 4498800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 68356680 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 875.021505 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 2600 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 86387 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 68316 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 680400 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 378000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 3194880 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 2768256 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 57004560 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 6211200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 76340016 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 814.797592 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 10140 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 390600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 3107520 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 2602368 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 5085600 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 45961380 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 6555000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 64405548 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 824.443779 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 10688 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 2600 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 80556 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 64875 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 95241 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 81703 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
|
|
@ -287,10 +288,10 @@ system.cpu.num_fp_register_writes 0 # nu
|
|||
system.cpu.num_mem_refs 1401 # number of memory refs
|
||||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.999990 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 95240.000010 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000010 # Percentage of idle cycles
|
||||
system.cpu.num_idle_cycles 0.999988 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 81702.000012 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999988 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000012 # Percentage of idle cycles
|
||||
system.cpu.Branches 1121 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
|
||||
|
|
@ -343,32 +344,32 @@ system.ruby.outstanding_req_hist::total 6759
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 6758
|
||||
system.ruby.latency_hist::mean 13.093075
|
||||
system.ruby.latency_hist::gmean 5.137326
|
||||
system.ruby.latency_hist::stdev 25.295268
|
||||
system.ruby.latency_hist | 6551 96.94% 96.94% | 168 2.49% 99.42% | 27 0.40% 99.82% | 4 0.06% 99.88% | 3 0.04% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.089819
|
||||
system.ruby.latency_hist::gmean 2.095228
|
||||
system.ruby.latency_hist::stdev 25.111209
|
||||
system.ruby.latency_hist | 6551 96.94% 96.94% | 169 2.50% 99.44% | 28 0.41% 99.85% | 2 0.03% 99.88% | 5 0.07% 99.96% | 2 0.03% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 6758
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 5469
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 5469
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1289
|
||||
system.ruby.miss_latency_hist::mean 55.916214
|
||||
system.ruby.miss_latency_hist::gmean 50.341721
|
||||
system.ruby.miss_latency_hist::stdev 32.999000
|
||||
system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 53.899147
|
||||
system.ruby.miss_latency_hist::gmean 48.323546
|
||||
system.ruby.miss_latency_hist::stdev 32.275754
|
||||
system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1289
|
||||
system.ruby.Directory.incomplete_times 1288
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.756544
|
||||
system.ruby.network.routers0.percent_links_utilized 7.876088
|
||||
system.ruby.network.routers0.msg_count.Control::2 1289
|
||||
system.ruby.network.routers0.msg_count.Data::2 1285
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1289
|
||||
|
|
@ -377,7 +378,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers1.percent_links_utilized 6.756544
|
||||
system.ruby.network.routers1.percent_links_utilized 7.876088
|
||||
system.ruby.network.routers1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1289
|
||||
|
|
@ -386,7 +387,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.percent_links_utilized 6.756544
|
||||
system.ruby.network.routers2.percent_links_utilized 7.876088
|
||||
system.ruby.network.routers2.msg_count.Control::2 1289
|
||||
system.ruby.network.routers2.msg_count.Data::2 1285
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1289
|
||||
|
|
@ -403,32 +404,32 @@ system.ruby.network.msg_byte.Control 30936
|
|||
system.ruby.network.msg_byte.Data 277560
|
||||
system.ruby.network.msg_byte.Response_Data 278424
|
||||
system.ruby.network.msg_byte.Writeback_Control 30840
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.764944
|
||||
system.ruby.network.routers0.throttle0.link_utilization 7.885879
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.748144
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.866296
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.748144
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.866296
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1289
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1285
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.764944
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.885879
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.764944
|
||||
system.ruby.network.routers2.throttle0.link_utilization 7.885879
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.748144
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.866296
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312
|
||||
|
|
@ -443,82 +444,82 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 715
|
||||
system.ruby.LD.latency_hist::mean 29.991608
|
||||
system.ruby.LD.latency_hist::gmean 13.799155
|
||||
system.ruby.LD.latency_hist::stdev 30.436552
|
||||
system.ruby.LD.latency_hist | 320 44.76% 44.76% | 332 46.43% 91.19% | 50 6.99% 98.18% | 5 0.70% 98.88% | 4 0.56% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 28.394406
|
||||
system.ruby.LD.latency_hist::gmean 8.251059
|
||||
system.ruby.LD.latency_hist::stdev 33.266069
|
||||
system.ruby.LD.latency_hist | 656 91.75% 91.75% | 50 6.99% 98.74% | 8 1.12% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 715
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 320
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 320
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 395
|
||||
system.ruby.LD.miss_latency_hist::mean 51.858228
|
||||
system.ruby.LD.miss_latency_hist::gmean 47.506026
|
||||
system.ruby.LD.miss_latency_hist::stdev 24.651585
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 50.587342
|
||||
system.ruby.LD.miss_latency_hist::gmean 45.603541
|
||||
system.ruby.LD.miss_latency_hist::stdev 30.035585
|
||||
system.ruby.LD.miss_latency_hist | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 395
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 673
|
||||
system.ruby.ST.latency_hist::mean 18.735513
|
||||
system.ruby.ST.latency_hist::gmean 6.548753
|
||||
system.ruby.ST.latency_hist::stdev 31.370836
|
||||
system.ruby.ST.latency_hist | 639 94.95% 94.95% | 25 3.71% 98.66% | 8 1.19% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 16.656761
|
||||
system.ruby.ST.latency_hist::gmean 2.888882
|
||||
system.ruby.ST.latency_hist::stdev 31.530024
|
||||
system.ruby.ST.latency_hist | 494 73.40% 73.40% | 146 21.69% 95.10% | 26 3.86% 98.96% | 0 0.00% 98.96% | 4 0.59% 99.55% | 0 0.00% 99.55% | 1 0.15% 99.70% | 0 0.00% 99.70% | 1 0.15% 99.85% | 1 0.15% 100.00%
|
||||
system.ruby.ST.latency_hist::total 673
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 494
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 494
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 179
|
||||
system.ruby.ST.miss_latency_hist::mean 62.162011
|
||||
system.ruby.ST.miss_latency_hist::gmean 56.471067
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.641225
|
||||
system.ruby.ST.miss_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 59.865922
|
||||
system.ruby.ST.miss_latency_hist::gmean 53.981018
|
||||
system.ruby.ST.miss_latency_hist::stdev 34.573548
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 179
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 5370
|
||||
system.ruby.IFETCH.latency_hist::mean 10.135940
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.369076
|
||||
system.ruby.IFETCH.latency_hist::stdev 22.541685
|
||||
system.ruby.IFETCH.latency_hist | 5260 97.95% 97.95% | 88 1.64% 99.59% | 11 0.20% 99.80% | 4 0.07% 99.87% | 3 0.06% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.088082
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.676829
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.661449
|
||||
system.ruby.IFETCH.latency_hist | 5255 97.86% 97.86% | 93 1.73% 99.59% | 16 0.30% 99.89% | 1 0.02% 99.91% | 3 0.06% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 5370
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 4655
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 4655
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 715
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 56.594406
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 50.506398
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 36.435131
|
||||
system.ruby.IFETCH.miss_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 54.234965
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 48.531211
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 32.684395
|
||||
system.ruby.IFETCH.miss_latency_hist | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 715
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1289
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 55.916214
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 50.341721
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 32.999000
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 53.899147
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 48.323546
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 32.275754
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1289
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -546,29 +547,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.858228
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.506026
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.651585
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.587342
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.603541
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.035585
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.162011
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 56.471067
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.641225
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 59.865922
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 53.981018
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 34.573548
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.594406
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.506398
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.435131
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 54.234965
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 48.531211
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.684395
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715
|
||||
system.ruby.Directory_Controller.GETX 1289 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,8 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
|
|
|
|||
|
|
@ -1,13 +1,12 @@
|
|||
Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout
|
||||
Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Feb 15 2014 16:30:59
|
||||
gem5 started Feb 15 2014 16:34:58
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
|
||||
gem5 compiled Aug 13 2015 19:59:06
|
||||
gem5 started Aug 13 2015 20:18:58
|
||||
gem5 executing on artery
|
||||
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 121759 because target called exit()
|
||||
Exiting @ tick 87948 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000107 # Number of seconds simulated
|
||||
sim_ticks 107256 # Number of ticks simulated
|
||||
final_tick 107256 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000088 # Number of seconds simulated
|
||||
sim_ticks 87948 # Number of ticks simulated
|
||||
final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57113 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 103447 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1138055 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 467864 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 39587 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71707 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 646904 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 417864 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 #
|
|||
system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 821660327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 821660327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 819273514 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 819273514 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1640933841 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1640933841 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1002046664 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1002046664 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 999135853 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 999135853 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2001182517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 2001182517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1377 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1373 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 43264 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 44864 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 43264 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadDRAM 40320 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 47808 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 39936 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 674 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 722 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::0 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 54 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 56 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 124 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 9 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 55 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 119 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 121 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 34 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 54 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 54 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 41 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 129 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 50 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 36 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 25 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 120 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 125 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 36 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 107152 # Total gap between requests
|
||||
system.mem_ctrls.totGap 87868 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
|
|||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 676 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::0 630 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,93 +184,93 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 276 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 306.782609 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 194.488181 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 303.473845 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 80 28.99% 28.99% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 80 28.99% 57.97% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 33 11.96% 69.93% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 22 7.97% 77.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 18 6.52% 84.42% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 7 2.54% 86.96% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7 2.54% 89.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 4 1.45% 90.94% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 25 9.06% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 276 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.243902 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.023325 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.314970 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 1 2.44% 2.44% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 16 39.02% 41.46% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 85.37% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 5 12.20% 97.56% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.487805 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.459950 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.003044 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 32 78.05% 78.05% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 2 4.88% 82.93% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 3 7.32% 90.24% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 4 9.76% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 9573 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 22417 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3380 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 14.16 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 271 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 293.313653 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 193.377642 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 283.497497 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 72 26.57% 26.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 83 30.63% 57.20% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 37 13.65% 70.85% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 23 8.49% 79.34% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 21 7.75% 87.08% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 1.85% 88.93% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7 2.58% 91.51% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 1.11% 92.62% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 20 7.38% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 271 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.289474 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.048466 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.463383 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 1 2.63% 2.63% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 15 39.47% 42.11% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 16 42.11% 84.21% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 10.53% 94.74% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 1 2.63% 97.37% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.63% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.421053 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.397539 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.919212 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 31 81.58% 81.58% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 5 13.16% 94.74% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 9303 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 21273 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3150 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 14.77 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 33.16 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 403.37 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 403.37 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 821.66 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 819.27 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 33.77 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 458.45 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 454.09 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1002.05 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 999.14 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 6.30 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.15 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.15 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.busUtil 7.13 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.58 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.88 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 443 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 65.53 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 88.98 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 38.96 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 390600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 3319680 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 2685312 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 57105108 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 10794600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 81609660 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 804.210371 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 17627 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls.avgWrQLen 25.04 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 420 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 556 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 66.67 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 85.41 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 31.95 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 76.19 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 657720 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 365400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 3407040 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 51093432 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 6724800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 70465656 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 820.264661 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 10886 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 80485 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 72174 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1292760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 718200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 4630080 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 3805056 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 62793936 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 5804400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 85655712 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 844.081594 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 9408 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 1368360 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 760200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 4268160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 3680640 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 54919728 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 3368400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 73959648 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 860.936931 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 5575 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 88844 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 16 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 107256 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 87948 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
|
|
@ -290,10 +290,10 @@ system.cpu.num_cc_register_writes 3536 # nu
|
|||
system.cpu.num_mem_refs 1988 # number of memory refs
|
||||
system.cpu.num_load_insts 1053 # Number of load instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.999991 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 107255.000009 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000009 # Percentage of idle cycles
|
||||
system.cpu.num_idle_cycles 0.999989 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 87947.000011 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000011 # Percentage of idle cycles
|
||||
system.cpu.Branches 1208 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction
|
||||
|
|
@ -346,32 +346,32 @@ system.ruby.outstanding_req_hist::total 8852
|
|||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8852
|
||||
system.ruby.latency_hist::mean 11.116584
|
||||
system.ruby.latency_hist::gmean 4.640695
|
||||
system.ruby.latency_hist::stdev 22.790037
|
||||
system.ruby.latency_hist | 8597 97.12% 97.12% | 214 2.42% 99.54% | 29 0.33% 99.86% | 4 0.05% 99.91% | 5 0.06% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 8.935382
|
||||
system.ruby.latency_hist::gmean 1.815175
|
||||
system.ruby.latency_hist::stdev 22.675647
|
||||
system.ruby.latency_hist | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8852
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 7475
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 1
|
||||
system.ruby.hit_latency_hist::gmean 1
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7475
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1377
|
||||
system.ruby.miss_latency_hist::mean 55.177197
|
||||
system.ruby.miss_latency_hist::gmean 49.553011
|
||||
system.ruby.miss_latency_hist::stdev 32.253276
|
||||
system.ruby.miss_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 52.012346
|
||||
system.ruby.miss_latency_hist::gmean 46.179478
|
||||
system.ruby.miss_latency_hist::stdev 33.292581
|
||||
system.ruby.miss_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1377
|
||||
system.ruby.Directory.incomplete_times 1376
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.409898
|
||||
system.ruby.network.routers0.percent_links_utilized 7.817119
|
||||
system.ruby.network.routers0.msg_count.Control::2 1377
|
||||
system.ruby.network.routers0.msg_count.Data::2 1373
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1377
|
||||
|
|
@ -380,7 +380,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers1.percent_links_utilized 6.409898
|
||||
system.ruby.network.routers1.percent_links_utilized 7.817119
|
||||
system.ruby.network.routers1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1377
|
||||
|
|
@ -389,7 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.percent_links_utilized 6.409898
|
||||
system.ruby.network.routers2.percent_links_utilized 7.817119
|
||||
system.ruby.network.routers2.msg_count.Control::2 1377
|
||||
system.ruby.network.routers2.msg_count.Data::2 1373
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1377
|
||||
|
|
@ -406,32 +406,32 @@ system.ruby.network.msg_byte.Control 33048
|
|||
system.ruby.network.msg_byte.Data 296568
|
||||
system.ruby.network.msg_byte.Response_Data 297432
|
||||
system.ruby.network.msg_byte.Writeback_Control 32952
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.417357
|
||||
system.ruby.network.routers0.throttle0.link_utilization 7.826215
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.402439
|
||||
system.ruby.network.routers0.throttle1.link_utilization 7.808023
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.402439
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.808023
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1377
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1373
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.417357
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.826215
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.417357
|
||||
system.ruby.network.routers2.throttle0.link_utilization 7.826215
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.402439
|
||||
system.ruby.network.routers2.throttle1.link_utilization 7.808023
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016
|
||||
|
|
@ -446,105 +446,105 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 1045
|
||||
system.ruby.LD.latency_hist::mean 24.565550
|
||||
system.ruby.LD.latency_hist::gmean 10.818925
|
||||
system.ruby.LD.latency_hist::stdev 28.664875
|
||||
system.ruby.LD.latency_hist | 965 92.34% 92.34% | 74 7.08% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 22.607656
|
||||
system.ruby.LD.latency_hist::gmean 5.952637
|
||||
system.ruby.LD.latency_hist::stdev 28.358291
|
||||
system.ruby.LD.latency_hist | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1045
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 546
|
||||
system.ruby.LD.hit_latency_hist::mean 3
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 1
|
||||
system.ruby.LD.hit_latency_hist::gmean 1
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 546
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 499
|
||||
system.ruby.LD.miss_latency_hist::mean 48.162325
|
||||
system.ruby.LD.miss_latency_hist::gmean 44.026667
|
||||
system.ruby.LD.miss_latency_hist::stdev 25.587548
|
||||
system.ruby.LD.miss_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 46.250501
|
||||
system.ruby.LD.miss_latency_hist::gmean 41.916728
|
||||
system.ruby.LD.miss_latency_hist::stdev 24.776985
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 499
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 935
|
||||
system.ruby.ST.latency_hist::mean 16.914439
|
||||
system.ruby.ST.latency_hist::gmean 6.394076
|
||||
system.ruby.ST.latency_hist::stdev 28.735394
|
||||
system.ruby.ST.latency_hist | 895 95.72% 95.72% | 33 3.53% 99.25% | 3 0.32% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 15.124064
|
||||
system.ruby.ST.latency_hist::gmean 2.829099
|
||||
system.ruby.ST.latency_hist::stdev 31.003309
|
||||
system.ruby.ST.latency_hist | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 935
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 681
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::mean 1
|
||||
system.ruby.ST.hit_latency_hist::gmean 1
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 681
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 254
|
||||
system.ruby.ST.miss_latency_hist::mean 54.220472
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.633946
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.614512
|
||||
system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 52.992126
|
||||
system.ruby.ST.miss_latency_hist::gmean 45.979346
|
||||
system.ruby.ST.miss_latency_hist::stdev 39.646660
|
||||
system.ruby.ST.miss_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 254
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6864
|
||||
system.ruby.IFETCH.latency_hist::mean 8.284237
|
||||
system.ruby.IFETCH.latency_hist::gmean 3.905930
|
||||
system.ruby.IFETCH.latency_hist::stdev 19.803554
|
||||
system.ruby.IFETCH.latency_hist | 6729 98.03% 98.03% | 107 1.56% 99.59% | 22 0.32% 99.91% | 1 0.01% 99.93% | 4 0.06% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 6.015589
|
||||
system.ruby.IFETCH.latency_hist::gmean 1.426336
|
||||
system.ruby.IFETCH.latency_hist::stdev 19.173758
|
||||
system.ruby.IFETCH.latency_hist | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6864
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 6241
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 6241
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 623
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 61.219904
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 54.926300
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 35.218812
|
||||
system.ruby.IFETCH.miss_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 56.260032
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 50.022291
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 35.712767
|
||||
system.ruby.IFETCH.miss_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 623
|
||||
system.ruby.RMW_Read.latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.latency_hist::samples 8
|
||||
system.ruby.RMW_Read.latency_hist::mean 6.875000
|
||||
system.ruby.RMW_Read.latency_hist::gmean 4.063647
|
||||
system.ruby.RMW_Read.latency_hist::mean 4.875000
|
||||
system.ruby.RMW_Read.latency_hist::gmean 1.542211
|
||||
system.ruby.RMW_Read.latency_hist::stdev 10.960155
|
||||
system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.latency_hist::total 8
|
||||
system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
|
||||
system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
|
||||
system.ruby.RMW_Read.hit_latency_hist::samples 7
|
||||
system.ruby.RMW_Read.hit_latency_hist::mean 3
|
||||
system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.hit_latency_hist::mean 1
|
||||
system.ruby.RMW_Read.hit_latency_hist::gmean 1
|
||||
system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.hit_latency_hist::total 7
|
||||
system.ruby.RMW_Read.miss_latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.miss_latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.miss_latency_hist::samples 1
|
||||
system.ruby.RMW_Read.miss_latency_hist::mean 34
|
||||
system.ruby.RMW_Read.miss_latency_hist::gmean 34.000000
|
||||
system.ruby.RMW_Read.miss_latency_hist::mean 32
|
||||
system.ruby.RMW_Read.miss_latency_hist::gmean 32
|
||||
system.ruby.RMW_Read.miss_latency_hist::stdev nan
|
||||
system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.miss_latency_hist::total 1
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1377
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 55.177197
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 49.553011
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 32.253276
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 52.012346
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 46.179478
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 33.292581
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1377
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -572,35 +572,35 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.162325
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.026667
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.587548
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 46.250501
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 41.916728
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.776985
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 54.220472
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.633946
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.614512
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.992126
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 45.979346
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 39.646660
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.219904
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.926300
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.218812
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.260032
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.022291
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.712767
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 34
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 32
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 32
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
|
|
@ -5,76 +5,76 @@ warn: rounding error > tolerance
|
|||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
system.cpu0: completed 10000 read, 5514 write accesses @985789
|
||||
system.cpu5: completed 10000 read, 5507 write accesses @985919
|
||||
system.cpu6: completed 10000 read, 5525 write accesses @1001074
|
||||
system.cpu2: completed 10000 read, 5599 write accesses @1007601
|
||||
system.cpu7: completed 10000 read, 5498 write accesses @1017943
|
||||
system.cpu4: completed 10000 read, 5572 write accesses @1024769
|
||||
system.cpu3: completed 10000 read, 5732 write accesses @1028309
|
||||
system.cpu1: completed 10000 read, 5598 write accesses @1041015
|
||||
system.cpu6: completed 20000 read, 11013 write accesses @1989998
|
||||
system.cpu0: completed 20000 read, 11024 write accesses @2017508
|
||||
system.cpu5: completed 20000 read, 11122 write accesses @2018515
|
||||
system.cpu2: completed 20000 read, 11126 write accesses @2025419
|
||||
system.cpu7: completed 20000 read, 11093 write accesses @2029349
|
||||
system.cpu3: completed 20000 read, 11390 write accesses @2036754
|
||||
system.cpu4: completed 20000 read, 11097 write accesses @2052341
|
||||
system.cpu1: completed 20000 read, 11255 write accesses @2071888
|
||||
system.cpu6: completed 30000 read, 16509 write accesses @3011316
|
||||
system.cpu2: completed 30000 read, 16563 write accesses @3015985
|
||||
system.cpu5: completed 30000 read, 16732 write accesses @3020048
|
||||
system.cpu7: completed 30000 read, 16594 write accesses @3039745
|
||||
system.cpu0: completed 30000 read, 16606 write accesses @3046317
|
||||
system.cpu4: completed 30000 read, 16705 write accesses @3051495
|
||||
system.cpu3: completed 30000 read, 17008 write accesses @3067438
|
||||
system.cpu1: completed 30000 read, 16891 write accesses @3109610
|
||||
system.cpu6: completed 40000 read, 22039 write accesses @4020333
|
||||
system.cpu5: completed 40000 read, 22236 write accesses @4027724
|
||||
system.cpu0: completed 40000 read, 22043 write accesses @4029762
|
||||
system.cpu2: completed 40000 read, 22161 write accesses @4031183
|
||||
system.cpu7: completed 40000 read, 22213 write accesses @4045977
|
||||
system.cpu4: completed 40000 read, 22298 write accesses @4082210
|
||||
system.cpu1: completed 40000 read, 22453 write accesses @4117416
|
||||
system.cpu3: completed 40000 read, 22664 write accesses @4121694
|
||||
system.cpu0: completed 50000 read, 27441 write accesses @5028972
|
||||
system.cpu6: completed 50000 read, 27572 write accesses @5030451
|
||||
system.cpu2: completed 50000 read, 27699 write accesses @5051990
|
||||
system.cpu5: completed 50000 read, 27966 write accesses @5054641
|
||||
system.cpu7: completed 50000 read, 27735 write accesses @5066083
|
||||
system.cpu4: completed 50000 read, 27771 write accesses @5088978
|
||||
system.cpu1: completed 50000 read, 28051 write accesses @5134928
|
||||
system.cpu3: completed 50000 read, 28027 write accesses @5145143
|
||||
system.cpu0: completed 60000 read, 32887 write accesses @6041088
|
||||
system.cpu6: completed 60000 read, 33047 write accesses @6052178
|
||||
system.cpu2: completed 60000 read, 33145 write accesses @6054126
|
||||
system.cpu5: completed 60000 read, 33467 write accesses @6058058
|
||||
system.cpu7: completed 60000 read, 33424 write accesses @6096363
|
||||
system.cpu4: completed 60000 read, 33328 write accesses @6102072
|
||||
system.cpu1: completed 60000 read, 33536 write accesses @6144667
|
||||
system.cpu3: completed 60000 read, 33718 write accesses @6194345
|
||||
system.cpu0: completed 70000 read, 38267 write accesses @7037253
|
||||
system.cpu6: completed 70000 read, 38604 write accesses @7069613
|
||||
system.cpu2: completed 70000 read, 38746 write accesses @7078099
|
||||
system.cpu5: completed 70000 read, 38936 write accesses @7088735
|
||||
system.cpu7: completed 70000 read, 39098 write accesses @7112647
|
||||
system.cpu4: completed 70000 read, 38903 write accesses @7119773
|
||||
system.cpu1: completed 70000 read, 39029 write accesses @7174150
|
||||
system.cpu3: completed 70000 read, 39351 write accesses @7212543
|
||||
system.cpu0: completed 80000 read, 43876 write accesses @8054755
|
||||
system.cpu6: completed 80000 read, 44096 write accesses @8081739
|
||||
system.cpu2: completed 80000 read, 44227 write accesses @8083983
|
||||
system.cpu5: completed 80000 read, 44434 write accesses @8095705
|
||||
system.cpu4: completed 80000 read, 44434 write accesses @8124001
|
||||
system.cpu7: completed 80000 read, 44724 write accesses @8128965
|
||||
system.cpu1: completed 80000 read, 44680 write accesses @8204951
|
||||
system.cpu3: completed 80000 read, 44871 write accesses @8248185
|
||||
system.cpu0: completed 90000 read, 49513 write accesses @9064097
|
||||
system.cpu2: completed 90000 read, 49820 write accesses @9098554
|
||||
system.cpu6: completed 90000 read, 49787 write accesses @9103948
|
||||
system.cpu5: completed 90000 read, 49985 write accesses @9122270
|
||||
system.cpu4: completed 90000 read, 50071 write accesses @9151457
|
||||
system.cpu7: completed 90000 read, 50244 write accesses @9162765
|
||||
system.cpu1: completed 90000 read, 50351 write accesses @9237663
|
||||
system.cpu3: completed 90000 read, 50544 write accesses @9266852
|
||||
system.cpu0: completed 100000 read, 54903 write accesses @10084846
|
||||
system.cpu3: completed 10000 read, 5348 write accesses @992702
|
||||
system.cpu6: completed 10000 read, 5382 write accesses @999346
|
||||
system.cpu1: completed 10000 read, 5624 write accesses @1005749
|
||||
system.cpu7: completed 10000 read, 5532 write accesses @1010533
|
||||
system.cpu2: completed 10000 read, 5663 write accesses @1013622
|
||||
system.cpu0: completed 10000 read, 5506 write accesses @1016642
|
||||
system.cpu4: completed 10000 read, 5607 write accesses @1016852
|
||||
system.cpu5: completed 10000 read, 5639 write accesses @1018259
|
||||
system.cpu6: completed 20000 read, 10715 write accesses @1997205
|
||||
system.cpu3: completed 20000 read, 10977 write accesses @1998029
|
||||
system.cpu0: completed 20000 read, 11023 write accesses @2011456
|
||||
system.cpu1: completed 20000 read, 11145 write accesses @2015637
|
||||
system.cpu5: completed 20000 read, 11208 write accesses @2025366
|
||||
system.cpu2: completed 20000 read, 11366 write accesses @2025566
|
||||
system.cpu4: completed 20000 read, 11146 write accesses @2028120
|
||||
system.cpu7: completed 20000 read, 11121 write accesses @2045222
|
||||
system.cpu6: completed 30000 read, 16197 write accesses @2978950
|
||||
system.cpu3: completed 30000 read, 16504 write accesses @2996143
|
||||
system.cpu5: completed 30000 read, 16638 write accesses @3014669
|
||||
system.cpu2: completed 30000 read, 16960 write accesses @3020410
|
||||
system.cpu1: completed 30000 read, 16646 write accesses @3022510
|
||||
system.cpu0: completed 30000 read, 16578 write accesses @3036538
|
||||
system.cpu4: completed 30000 read, 16862 write accesses @3064327
|
||||
system.cpu7: completed 30000 read, 16883 write accesses @3094105
|
||||
system.cpu6: completed 40000 read, 21871 write accesses @3965015
|
||||
system.cpu3: completed 40000 read, 22121 write accesses @4005328
|
||||
system.cpu1: completed 40000 read, 22099 write accesses @4020080
|
||||
system.cpu0: completed 40000 read, 21993 write accesses @4023329
|
||||
system.cpu5: completed 40000 read, 22121 write accesses @4034804
|
||||
system.cpu2: completed 40000 read, 22585 write accesses @4048347
|
||||
system.cpu4: completed 40000 read, 22400 write accesses @4056884
|
||||
system.cpu7: completed 40000 read, 22529 write accesses @4115622
|
||||
system.cpu6: completed 50000 read, 27583 write accesses @4990697
|
||||
system.cpu3: completed 50000 read, 27753 write accesses @5007438
|
||||
system.cpu0: completed 50000 read, 27487 write accesses @5025428
|
||||
system.cpu5: completed 50000 read, 27656 write accesses @5027517
|
||||
system.cpu1: completed 50000 read, 27616 write accesses @5030165
|
||||
system.cpu2: completed 50000 read, 28090 write accesses @5055177
|
||||
system.cpu4: completed 50000 read, 27929 write accesses @5090891
|
||||
system.cpu7: completed 50000 read, 27992 write accesses @5110188
|
||||
system.cpu6: completed 60000 read, 32899 write accesses @5986136
|
||||
system.cpu3: completed 60000 read, 33406 write accesses @6022857
|
||||
system.cpu0: completed 60000 read, 33044 write accesses @6031653
|
||||
system.cpu1: completed 60000 read, 33212 write accesses @6041161
|
||||
system.cpu5: completed 60000 read, 33442 write accesses @6056413
|
||||
system.cpu2: completed 60000 read, 33657 write accesses @6078013
|
||||
system.cpu4: completed 60000 read, 33587 write accesses @6112419
|
||||
system.cpu7: completed 60000 read, 33576 write accesses @6115149
|
||||
system.cpu6: completed 70000 read, 38416 write accesses @6987907
|
||||
system.cpu3: completed 70000 read, 38845 write accesses @7046740
|
||||
system.cpu1: completed 70000 read, 38729 write accesses @7054748
|
||||
system.cpu0: completed 70000 read, 38718 write accesses @7054971
|
||||
system.cpu5: completed 70000 read, 39001 write accesses @7079629
|
||||
system.cpu2: completed 70000 read, 39269 write accesses @7096675
|
||||
system.cpu7: completed 70000 read, 39115 write accesses @7118065
|
||||
system.cpu4: completed 70000 read, 39088 write accesses @7118300
|
||||
system.cpu6: completed 80000 read, 43855 write accesses @7989172
|
||||
system.cpu3: completed 80000 read, 44347 write accesses @8044375
|
||||
system.cpu1: completed 80000 read, 44281 write accesses @8052426
|
||||
system.cpu0: completed 80000 read, 44306 write accesses @8066104
|
||||
system.cpu5: completed 80000 read, 44603 write accesses @8080810
|
||||
system.cpu7: completed 80000 read, 44480 write accesses @8104479
|
||||
system.cpu4: completed 80000 read, 44600 write accesses @8110552
|
||||
system.cpu2: completed 80000 read, 44822 write accesses @8120410
|
||||
system.cpu6: completed 90000 read, 49504 write accesses @8982438
|
||||
system.cpu3: completed 90000 read, 49941 write accesses @9055578
|
||||
system.cpu0: completed 90000 read, 49850 write accesses @9059967
|
||||
system.cpu1: completed 90000 read, 49940 write accesses @9064061
|
||||
system.cpu5: completed 90000 read, 50040 write accesses @9082907
|
||||
system.cpu4: completed 90000 read, 50137 write accesses @9101079
|
||||
system.cpu7: completed 90000 read, 50039 write accesses @9112455
|
||||
system.cpu2: completed 90000 read, 50353 write accesses @9135660
|
||||
system.cpu6: completed 100000 read, 55063 write accesses @9995319
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 28 2014 02:49:35
|
||||
gem5 started Aug 28 2014 02:49:48
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
|
||||
gem5 compiled Aug 13 2015 19:16:05
|
||||
gem5 started Aug 13 2015 20:15:43
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 7259586 because maximum number of loads reached
|
||||
Exiting @ tick 9995319 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
|
|
@ -1,85 +1,80 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu6: completed 10000 read, 5503 write accesses @757269
|
||||
system.cpu4: completed 10000 read, 5478 write accesses @761080
|
||||
system.cpu2: completed 10000 read, 5550 write accesses @763319
|
||||
system.cpu1: completed 10000 read, 5614 write accesses @768345
|
||||
system.cpu0: completed 10000 read, 5587 write accesses @769447
|
||||
system.cpu7: completed 10000 read, 5757 write accesses @772728
|
||||
system.cpu5: completed 10000 read, 5702 write accesses @774176
|
||||
system.cpu3: completed 10000 read, 5518 write accesses @779096
|
||||
system.cpu7: completed 20000 read, 10973 write accesses @1520367
|
||||
system.cpu4: completed 20000 read, 10979 write accesses @1526709
|
||||
system.cpu6: completed 20000 read, 11106 write accesses @1529725
|
||||
system.cpu2: completed 20000 read, 10993 write accesses @1531224
|
||||
system.cpu1: completed 20000 read, 11181 write accesses @1533339
|
||||
system.cpu5: completed 20000 read, 11353 write accesses @1534479
|
||||
system.cpu0: completed 20000 read, 11156 write accesses @1538403
|
||||
system.cpu3: completed 20000 read, 11059 write accesses @1546200
|
||||
system.cpu7: completed 30000 read, 16565 write accesses @2285511
|
||||
system.cpu5: completed 30000 read, 16777 write accesses @2288641
|
||||
system.cpu2: completed 30000 read, 16597 write accesses @2294136
|
||||
system.cpu4: completed 30000 read, 16631 write accesses @2299512
|
||||
system.cpu0: completed 30000 read, 16690 write accesses @2299577
|
||||
system.cpu1: completed 30000 read, 16784 write accesses @2300367
|
||||
system.cpu3: completed 30000 read, 16611 write accesses @2300731
|
||||
system.cpu6: completed 30000 read, 16728 write accesses @2302250
|
||||
system.cpu4: completed 40000 read, 22149 write accesses @3049466
|
||||
system.cpu6: completed 40000 read, 22257 write accesses @3061175
|
||||
system.cpu7: completed 40000 read, 22207 write accesses @3063273
|
||||
system.cpu5: completed 40000 read, 22390 write accesses @3065947
|
||||
system.cpu2: completed 40000 read, 22266 write accesses @3066692
|
||||
system.cpu3: completed 40000 read, 22073 write accesses @3067947
|
||||
system.cpu0: completed 40000 read, 22351 write accesses @3070634
|
||||
system.cpu1: completed 40000 read, 22419 write accesses @3080538
|
||||
system.cpu4: completed 50000 read, 27758 write accesses @3814226
|
||||
system.cpu5: completed 50000 read, 27788 write accesses @3821800
|
||||
system.cpu2: completed 50000 read, 27879 write accesses @3832783
|
||||
system.cpu6: completed 50000 read, 27794 write accesses @3833668
|
||||
system.cpu7: completed 50000 read, 27831 write accesses @3833943
|
||||
system.cpu3: completed 50000 read, 27630 write accesses @3836295
|
||||
system.cpu1: completed 50000 read, 28014 write accesses @3838264
|
||||
system.cpu0: completed 50000 read, 27900 write accesses @3845606
|
||||
system.cpu4: completed 60000 read, 33195 write accesses @4581871
|
||||
system.cpu6: completed 60000 read, 33436 write accesses @4591130
|
||||
system.cpu5: completed 60000 read, 33441 write accesses @4592195
|
||||
system.cpu2: completed 60000 read, 33425 write accesses @4596449
|
||||
system.cpu7: completed 60000 read, 33475 write accesses @4602310
|
||||
system.cpu1: completed 60000 read, 33528 write accesses @4604165
|
||||
system.cpu3: completed 60000 read, 33269 write accesses @4608944
|
||||
system.cpu0: completed 60000 read, 33561 write accesses @4617814
|
||||
system.cpu4: completed 70000 read, 38745 write accesses @5357021
|
||||
system.cpu1: completed 70000 read, 39092 write accesses @5358188
|
||||
system.cpu7: completed 70000 read, 39078 write accesses @5359639
|
||||
system.cpu6: completed 70000 read, 39017 write accesses @5360015
|
||||
system.cpu5: completed 70000 read, 39077 write accesses @5360709
|
||||
system.cpu2: completed 70000 read, 39142 write accesses @5362206
|
||||
system.cpu3: completed 70000 read, 38953 write accesses @5383557
|
||||
system.cpu0: completed 70000 read, 39148 write accesses @5384346
|
||||
system.cpu1: completed 80000 read, 44697 write accesses @6109229
|
||||
system.cpu4: completed 80000 read, 44391 write accesses @6113222
|
||||
system.cpu6: completed 80000 read, 44634 write accesses @6116932
|
||||
system.cpu2: completed 80000 read, 44686 write accesses @6124384
|
||||
system.cpu7: completed 80000 read, 44658 write accesses @6130030
|
||||
system.cpu5: completed 80000 read, 44817 write accesses @6133468
|
||||
system.cpu0: completed 80000 read, 44666 write accesses @6150195
|
||||
system.cpu3: completed 80000 read, 44619 write accesses @6165694
|
||||
system.cpu1: completed 90000 read, 50286 write accesses @6886139
|
||||
system.cpu5: completed 90000 read, 50291 write accesses @6887562
|
||||
system.cpu6: completed 90000 read, 50249 write accesses @6888221
|
||||
system.cpu4: completed 90000 read, 50068 write accesses @6890175
|
||||
system.cpu2: completed 90000 read, 50264 write accesses @6897909
|
||||
system.cpu7: completed 90000 read, 50336 write accesses @6907186
|
||||
system.cpu3: completed 90000 read, 50220 write accesses @6927421
|
||||
system.cpu0: completed 90000 read, 50337 write accesses @6930851
|
||||
system.cpu5: completed 100000 read, 55860 write accesses @7645897
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
system.cpu6: completed 10000 read, 5570 write accesses @748299
|
||||
system.cpu5: completed 10000 read, 5647 write accesses @748339
|
||||
system.cpu7: completed 10000 read, 5495 write accesses @748944
|
||||
system.cpu1: completed 10000 read, 5568 write accesses @750499
|
||||
system.cpu0: completed 10000 read, 5483 write accesses @751080
|
||||
system.cpu3: completed 10000 read, 5619 write accesses @755896
|
||||
system.cpu4: completed 10000 read, 5746 write accesses @761190
|
||||
system.cpu2: completed 10000 read, 5739 write accesses @761633
|
||||
system.cpu7: completed 20000 read, 11020 write accesses @1491203
|
||||
system.cpu1: completed 20000 read, 11119 write accesses @1491567
|
||||
system.cpu0: completed 20000 read, 11060 write accesses @1496113
|
||||
system.cpu5: completed 20000 read, 11192 write accesses @1498026
|
||||
system.cpu2: completed 20000 read, 11268 write accesses @1499402
|
||||
system.cpu6: completed 20000 read, 11125 write accesses @1500210
|
||||
system.cpu4: completed 20000 read, 11177 write accesses @1507742
|
||||
system.cpu3: completed 20000 read, 11198 write accesses @1508349
|
||||
system.cpu1: completed 30000 read, 16685 write accesses @2235920
|
||||
system.cpu7: completed 30000 read, 16570 write accesses @2243071
|
||||
system.cpu3: completed 30000 read, 16661 write accesses @2246169
|
||||
system.cpu5: completed 30000 read, 16817 write accesses @2247226
|
||||
system.cpu6: completed 30000 read, 16630 write accesses @2251239
|
||||
system.cpu2: completed 30000 read, 17073 write accesses @2253746
|
||||
system.cpu0: completed 30000 read, 16607 write accesses @2257900
|
||||
system.cpu4: completed 30000 read, 16751 write accesses @2259082
|
||||
system.cpu1: completed 40000 read, 22443 write accesses @2985201
|
||||
system.cpu6: completed 40000 read, 22171 write accesses @2988819
|
||||
system.cpu5: completed 40000 read, 22360 write accesses @2994816
|
||||
system.cpu3: completed 40000 read, 22299 write accesses @2995156
|
||||
system.cpu2: completed 40000 read, 22516 write accesses @2995179
|
||||
system.cpu0: completed 40000 read, 22114 write accesses @2997980
|
||||
system.cpu4: completed 40000 read, 22133 write accesses @3004731
|
||||
system.cpu7: completed 40000 read, 22279 write accesses @3009795
|
||||
system.cpu1: completed 50000 read, 27939 write accesses @3723980
|
||||
system.cpu5: completed 50000 read, 27866 write accesses @3732543
|
||||
system.cpu2: completed 50000 read, 28007 write accesses @3736276
|
||||
system.cpu0: completed 50000 read, 27557 write accesses @3741693
|
||||
system.cpu6: completed 50000 read, 27758 write accesses @3746907
|
||||
system.cpu3: completed 50000 read, 28063 write accesses @3754651
|
||||
system.cpu4: completed 50000 read, 27711 write accesses @3755367
|
||||
system.cpu7: completed 50000 read, 27794 write accesses @3759179
|
||||
system.cpu1: completed 60000 read, 33413 write accesses @4481770
|
||||
system.cpu2: completed 60000 read, 33545 write accesses @4483814
|
||||
system.cpu5: completed 60000 read, 33400 write accesses @4486225
|
||||
system.cpu6: completed 60000 read, 33358 write accesses @4489305
|
||||
system.cpu0: completed 60000 read, 33272 write accesses @4495744
|
||||
system.cpu7: completed 60000 read, 33388 write accesses @4502600
|
||||
system.cpu3: completed 60000 read, 33518 write accesses @4505507
|
||||
system.cpu4: completed 60000 read, 33246 write accesses @4507884
|
||||
system.cpu6: completed 70000 read, 38763 write accesses @5228140
|
||||
system.cpu1: completed 70000 read, 38950 write accesses @5234719
|
||||
system.cpu5: completed 70000 read, 39075 write accesses @5237913
|
||||
system.cpu7: completed 70000 read, 38837 write accesses @5239204
|
||||
system.cpu2: completed 70000 read, 39142 write accesses @5242564
|
||||
system.cpu3: completed 70000 read, 39128 write accesses @5249855
|
||||
system.cpu0: completed 70000 read, 38875 write accesses @5253251
|
||||
system.cpu4: completed 70000 read, 38862 write accesses @5255205
|
||||
system.cpu6: completed 80000 read, 44316 write accesses @5978847
|
||||
system.cpu1: completed 80000 read, 44524 write accesses @5980771
|
||||
system.cpu5: completed 80000 read, 44534 write accesses @5982466
|
||||
system.cpu7: completed 80000 read, 44358 write accesses @5986610
|
||||
system.cpu0: completed 80000 read, 44270 write accesses @5996151
|
||||
system.cpu2: completed 80000 read, 44750 write accesses @6000893
|
||||
system.cpu3: completed 80000 read, 44691 write accesses @6004535
|
||||
system.cpu4: completed 80000 read, 44602 write accesses @6010875
|
||||
system.cpu6: completed 90000 read, 49845 write accesses @6717920
|
||||
system.cpu7: completed 90000 read, 50000 write accesses @6722062
|
||||
system.cpu1: completed 90000 read, 50241 write accesses @6726859
|
||||
system.cpu5: completed 90000 read, 50114 write accesses @6731510
|
||||
system.cpu0: completed 90000 read, 49747 write accesses @6741713
|
||||
system.cpu2: completed 90000 read, 50307 write accesses @6746697
|
||||
system.cpu3: completed 90000 read, 50421 write accesses @6748141
|
||||
system.cpu4: completed 90000 read, 50184 write accesses @6762059
|
||||
system.cpu1: completed 100000 read, 56005 write accesses @7477743
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:42:56
|
||||
gem5 started Jan 22 2014 17:26:44
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
gem5 compiled Aug 13 2015 19:22:33
|
||||
gem5 started Aug 13 2015 20:16:16
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 7481441 because maximum number of loads reached
|
||||
Exiting @ tick 7477743 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
|
|
@ -1,85 +1,80 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu5: completed 10000 read, 5530 write accesses @619922
|
||||
system.cpu6: completed 10000 read, 5474 write accesses @621650
|
||||
system.cpu7: completed 10000 read, 5669 write accesses @623678
|
||||
system.cpu2: completed 10000 read, 5566 write accesses @627878
|
||||
system.cpu4: completed 10000 read, 5488 write accesses @628250
|
||||
system.cpu1: completed 10000 read, 5485 write accesses @629308
|
||||
system.cpu3: completed 10000 read, 5616 write accesses @630755
|
||||
system.cpu0: completed 10000 read, 5556 write accesses @631832
|
||||
system.cpu0: completed 20000 read, 11113 write accesses @1242739
|
||||
system.cpu2: completed 20000 read, 11184 write accesses @1249193
|
||||
system.cpu5: completed 20000 read, 11055 write accesses @1252676
|
||||
system.cpu1: completed 20000 read, 11025 write accesses @1255481
|
||||
system.cpu6: completed 20000 read, 10958 write accesses @1259795
|
||||
system.cpu3: completed 20000 read, 11192 write accesses @1262410
|
||||
system.cpu4: completed 20000 read, 11069 write accesses @1265165
|
||||
system.cpu7: completed 20000 read, 11154 write accesses @1271872
|
||||
system.cpu2: completed 30000 read, 16789 write accesses @1882328
|
||||
system.cpu5: completed 30000 read, 16628 write accesses @1882366
|
||||
system.cpu4: completed 30000 read, 16634 write accesses @1884079
|
||||
system.cpu0: completed 30000 read, 16724 write accesses @1885096
|
||||
system.cpu1: completed 30000 read, 16623 write accesses @1888139
|
||||
system.cpu3: completed 30000 read, 16738 write accesses @1892924
|
||||
system.cpu6: completed 30000 read, 16532 write accesses @1894586
|
||||
system.cpu7: completed 30000 read, 16931 write accesses @1919912
|
||||
system.cpu0: completed 40000 read, 22182 write accesses @2505116
|
||||
system.cpu4: completed 40000 read, 22117 write accesses @2510993
|
||||
system.cpu1: completed 40000 read, 22260 write accesses @2513447
|
||||
system.cpu5: completed 40000 read, 22212 write accesses @2514125
|
||||
system.cpu3: completed 40000 read, 22396 write accesses @2516765
|
||||
system.cpu2: completed 40000 read, 22468 write accesses @2519189
|
||||
system.cpu6: completed 40000 read, 22230 write accesses @2538281
|
||||
system.cpu7: completed 40000 read, 22488 write accesses @2557526
|
||||
system.cpu0: completed 50000 read, 27789 write accesses @3133555
|
||||
system.cpu2: completed 50000 read, 28077 write accesses @3139915
|
||||
system.cpu4: completed 50000 read, 27742 write accesses @3146518
|
||||
system.cpu1: completed 50000 read, 27886 write accesses @3150027
|
||||
system.cpu5: completed 50000 read, 27798 write accesses @3154334
|
||||
system.cpu3: completed 50000 read, 28034 write accesses @3161717
|
||||
system.cpu6: completed 50000 read, 27710 write accesses @3168082
|
||||
system.cpu7: completed 50000 read, 28032 write accesses @3187555
|
||||
system.cpu0: completed 60000 read, 33311 write accesses @3767660
|
||||
system.cpu4: completed 60000 read, 33304 write accesses @3772541
|
||||
system.cpu1: completed 60000 read, 33446 write accesses @3773198
|
||||
system.cpu2: completed 60000 read, 33652 write accesses @3776350
|
||||
system.cpu5: completed 60000 read, 33271 write accesses @3781457
|
||||
system.cpu6: completed 60000 read, 33278 write accesses @3794854
|
||||
system.cpu3: completed 60000 read, 33612 write accesses @3795827
|
||||
system.cpu7: completed 60000 read, 33548 write accesses @3811016
|
||||
system.cpu0: completed 70000 read, 38763 write accesses @4391942
|
||||
system.cpu5: completed 70000 read, 38783 write accesses @4406065
|
||||
system.cpu4: completed 70000 read, 38931 write accesses @4406093
|
||||
system.cpu1: completed 70000 read, 39120 write accesses @4408424
|
||||
system.cpu2: completed 70000 read, 39282 write accesses @4411507
|
||||
system.cpu6: completed 70000 read, 38935 write accesses @4431425
|
||||
system.cpu3: completed 70000 read, 39112 write accesses @4436411
|
||||
system.cpu7: completed 70000 read, 39053 write accesses @4450257
|
||||
system.cpu4: completed 80000 read, 44397 write accesses @5015840
|
||||
system.cpu0: completed 80000 read, 44355 write accesses @5031328
|
||||
system.cpu1: completed 80000 read, 44681 write accesses @5033509
|
||||
system.cpu5: completed 80000 read, 44411 write accesses @5035544
|
||||
system.cpu2: completed 80000 read, 44867 write accesses @5051495
|
||||
system.cpu6: completed 80000 read, 44501 write accesses @5065596
|
||||
system.cpu3: completed 80000 read, 44674 write accesses @5067973
|
||||
system.cpu7: completed 80000 read, 44457 write accesses @5071578
|
||||
system.cpu5: completed 90000 read, 50018 write accesses @5653124
|
||||
system.cpu4: completed 90000 read, 50091 write accesses @5657891
|
||||
system.cpu0: completed 90000 read, 50057 write accesses @5659483
|
||||
system.cpu1: completed 90000 read, 50245 write accesses @5662169
|
||||
system.cpu2: completed 90000 read, 50468 write accesses @5689246
|
||||
system.cpu7: completed 90000 read, 50055 write accesses @5700359
|
||||
system.cpu6: completed 90000 read, 50091 write accesses @5701022
|
||||
system.cpu3: completed 90000 read, 50159 write accesses @5709281
|
||||
system.cpu0: completed 100000 read, 55570 write accesses @6284915
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
system.cpu0: completed 10000 read, 5438 write accesses @570769
|
||||
system.cpu3: completed 10000 read, 5486 write accesses @571889
|
||||
system.cpu7: completed 10000 read, 5573 write accesses @579188
|
||||
system.cpu1: completed 10000 read, 5608 write accesses @581011
|
||||
system.cpu6: completed 10000 read, 5567 write accesses @582686
|
||||
system.cpu4: completed 10000 read, 5591 write accesses @584722
|
||||
system.cpu2: completed 10000 read, 5557 write accesses @586208
|
||||
system.cpu5: completed 10000 read, 5736 write accesses @589352
|
||||
system.cpu0: completed 20000 read, 11059 write accesses @1157243
|
||||
system.cpu6: completed 20000 read, 11078 write accesses @1162403
|
||||
system.cpu3: completed 20000 read, 10981 write accesses @1164669
|
||||
system.cpu1: completed 20000 read, 11264 write accesses @1166168
|
||||
system.cpu7: completed 20000 read, 11196 write accesses @1167284
|
||||
system.cpu4: completed 20000 read, 11109 write accesses @1177371
|
||||
system.cpu2: completed 20000 read, 11057 write accesses @1180619
|
||||
system.cpu5: completed 20000 read, 11381 write accesses @1181888
|
||||
system.cpu3: completed 30000 read, 16437 write accesses @1737096
|
||||
system.cpu6: completed 30000 read, 16668 write accesses @1737657
|
||||
system.cpu0: completed 30000 read, 16583 write accesses @1744758
|
||||
system.cpu7: completed 30000 read, 16677 write accesses @1750821
|
||||
system.cpu1: completed 30000 read, 16900 write accesses @1758970
|
||||
system.cpu4: completed 30000 read, 16637 write accesses @1759061
|
||||
system.cpu2: completed 30000 read, 16692 write accesses @1764462
|
||||
system.cpu5: completed 30000 read, 17012 write accesses @1766901
|
||||
system.cpu3: completed 40000 read, 21900 write accesses @2318433
|
||||
system.cpu6: completed 40000 read, 22213 write accesses @2326183
|
||||
system.cpu0: completed 40000 read, 22100 write accesses @2330415
|
||||
system.cpu7: completed 40000 read, 22210 write accesses @2340974
|
||||
system.cpu1: completed 40000 read, 22520 write accesses @2342642
|
||||
system.cpu4: completed 40000 read, 22243 write accesses @2344379
|
||||
system.cpu2: completed 40000 read, 22366 write accesses @2353655
|
||||
system.cpu5: completed 40000 read, 22618 write accesses @2355311
|
||||
system.cpu3: completed 50000 read, 27430 write accesses @2905853
|
||||
system.cpu0: completed 50000 read, 27644 write accesses @2909589
|
||||
system.cpu6: completed 50000 read, 27833 write accesses @2914500
|
||||
system.cpu1: completed 50000 read, 28151 write accesses @2927131
|
||||
system.cpu7: completed 50000 read, 27858 write accesses @2932955
|
||||
system.cpu5: completed 50000 read, 28068 write accesses @2933318
|
||||
system.cpu4: completed 50000 read, 27863 write accesses @2935763
|
||||
system.cpu2: completed 50000 read, 27944 write accesses @2939029
|
||||
system.cpu3: completed 60000 read, 33085 write accesses @3485958
|
||||
system.cpu0: completed 60000 read, 33127 write accesses @3493381
|
||||
system.cpu6: completed 60000 read, 33377 write accesses @3507979
|
||||
system.cpu2: completed 60000 read, 33438 write accesses @3515468
|
||||
system.cpu4: completed 60000 read, 33417 write accesses @3516729
|
||||
system.cpu1: completed 60000 read, 33739 write accesses @3518747
|
||||
system.cpu5: completed 60000 read, 33740 write accesses @3526984
|
||||
system.cpu7: completed 60000 read, 33559 write accesses @3532034
|
||||
system.cpu3: completed 70000 read, 38725 write accesses @4062982
|
||||
system.cpu0: completed 70000 read, 38646 write accesses @4078763
|
||||
system.cpu2: completed 70000 read, 39080 write accesses @4090901
|
||||
system.cpu6: completed 70000 read, 38952 write accesses @4094520
|
||||
system.cpu5: completed 70000 read, 39225 write accesses @4095937
|
||||
system.cpu4: completed 70000 read, 39045 write accesses @4099573
|
||||
system.cpu1: completed 70000 read, 39252 write accesses @4107563
|
||||
system.cpu7: completed 70000 read, 39300 write accesses @4124546
|
||||
system.cpu3: completed 80000 read, 44295 write accesses @4644973
|
||||
system.cpu0: completed 80000 read, 44378 write accesses @4658860
|
||||
system.cpu6: completed 80000 read, 44423 write accesses @4666482
|
||||
system.cpu2: completed 80000 read, 44600 write accesses @4677073
|
||||
system.cpu5: completed 80000 read, 44978 write accesses @4678763
|
||||
system.cpu4: completed 80000 read, 44603 write accesses @4687972
|
||||
system.cpu1: completed 80000 read, 44846 write accesses @4689031
|
||||
system.cpu7: completed 80000 read, 44628 write accesses @4707929
|
||||
system.cpu3: completed 90000 read, 49800 write accesses @5223450
|
||||
system.cpu6: completed 90000 read, 49915 write accesses @5243962
|
||||
system.cpu0: completed 90000 read, 50068 write accesses @5252685
|
||||
system.cpu2: completed 90000 read, 50165 write accesses @5258561
|
||||
system.cpu5: completed 90000 read, 50552 write accesses @5261845
|
||||
system.cpu1: completed 90000 read, 50370 write accesses @5279905
|
||||
system.cpu4: completed 90000 read, 50291 write accesses @5283589
|
||||
system.cpu7: completed 90000 read, 50405 write accesses @5296282
|
||||
system.cpu3: completed 100000 read, 55379 write accesses @5815635
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:47:59
|
||||
gem5 started Jan 22 2014 17:27:37
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
gem5 compiled Aug 13 2015 19:28:58
|
||||
gem5 started Aug 13 2015 20:16:58
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 6151475 because maximum number of loads reached
|
||||
Exiting @ tick 5815635 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
|
|
@ -1,85 +1,80 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu4: completed 10000 read, 5516 write accesses @584228
|
||||
system.cpu5: completed 10000 read, 5515 write accesses @587183
|
||||
system.cpu1: completed 10000 read, 5491 write accesses @591446
|
||||
system.cpu7: completed 10000 read, 5626 write accesses @595409
|
||||
system.cpu2: completed 10000 read, 5637 write accesses @596437
|
||||
system.cpu6: completed 10000 read, 5437 write accesses @597608
|
||||
system.cpu3: completed 10000 read, 5738 write accesses @597986
|
||||
system.cpu0: completed 10000 read, 5730 write accesses @601184
|
||||
system.cpu4: completed 20000 read, 11120 write accesses @1170250
|
||||
system.cpu6: completed 20000 read, 10900 write accesses @1171579
|
||||
system.cpu3: completed 20000 read, 11193 write accesses @1184267
|
||||
system.cpu1: completed 20000 read, 11047 write accesses @1190135
|
||||
system.cpu5: completed 20000 read, 11070 write accesses @1191953
|
||||
system.cpu7: completed 20000 read, 11317 write accesses @1192073
|
||||
system.cpu2: completed 20000 read, 11059 write accesses @1192934
|
||||
system.cpu0: completed 20000 read, 11218 write accesses @1196582
|
||||
system.cpu6: completed 30000 read, 16404 write accesses @1756097
|
||||
system.cpu4: completed 30000 read, 16698 write accesses @1768219
|
||||
system.cpu7: completed 30000 read, 16835 write accesses @1769427
|
||||
system.cpu3: completed 30000 read, 16672 write accesses @1773026
|
||||
system.cpu1: completed 30000 read, 16602 write accesses @1773962
|
||||
system.cpu0: completed 30000 read, 16781 write accesses @1777262
|
||||
system.cpu5: completed 30000 read, 16565 write accesses @1782900
|
||||
system.cpu2: completed 30000 read, 16614 write accesses @1785263
|
||||
system.cpu6: completed 40000 read, 22003 write accesses @2340507
|
||||
system.cpu1: completed 40000 read, 22145 write accesses @2358116
|
||||
system.cpu0: completed 40000 read, 22355 write accesses @2364775
|
||||
system.cpu7: completed 40000 read, 22565 write accesses @2374538
|
||||
system.cpu2: completed 40000 read, 22222 write accesses @2375711
|
||||
system.cpu4: completed 40000 read, 22294 write accesses @2376781
|
||||
system.cpu3: completed 40000 read, 22360 write accesses @2377205
|
||||
system.cpu5: completed 40000 read, 22099 write accesses @2379118
|
||||
system.cpu6: completed 50000 read, 27600 write accesses @2941333
|
||||
system.cpu1: completed 50000 read, 27821 write accesses @2946145
|
||||
system.cpu0: completed 50000 read, 27935 write accesses @2959151
|
||||
system.cpu2: completed 50000 read, 27794 write accesses @2968804
|
||||
system.cpu3: completed 50000 read, 27849 write accesses @2971166
|
||||
system.cpu5: completed 50000 read, 27657 write accesses @2977357
|
||||
system.cpu4: completed 50000 read, 27828 write accesses @2978259
|
||||
system.cpu7: completed 50000 read, 28284 write accesses @2978857
|
||||
system.cpu6: completed 60000 read, 33178 write accesses @3536924
|
||||
system.cpu1: completed 60000 read, 33394 write accesses @3543961
|
||||
system.cpu2: completed 60000 read, 33230 write accesses @3549333
|
||||
system.cpu0: completed 60000 read, 33564 write accesses @3564287
|
||||
system.cpu3: completed 60000 read, 33336 write accesses @3569137
|
||||
system.cpu4: completed 60000 read, 33587 write accesses @3570593
|
||||
system.cpu5: completed 60000 read, 33166 write accesses @3576647
|
||||
system.cpu7: completed 60000 read, 33832 write accesses @3577075
|
||||
system.cpu6: completed 70000 read, 38652 write accesses @4137461
|
||||
system.cpu2: completed 70000 read, 38824 write accesses @4141010
|
||||
system.cpu1: completed 70000 read, 39043 write accesses @4142171
|
||||
system.cpu4: completed 70000 read, 39136 write accesses @4148986
|
||||
system.cpu5: completed 70000 read, 38716 write accesses @4161730
|
||||
system.cpu0: completed 70000 read, 39119 write accesses @4165271
|
||||
system.cpu3: completed 70000 read, 38875 write accesses @4169555
|
||||
system.cpu7: completed 70000 read, 39501 write accesses @4176068
|
||||
system.cpu6: completed 80000 read, 44287 write accesses @4740297
|
||||
system.cpu2: completed 80000 read, 44433 write accesses @4742323
|
||||
system.cpu4: completed 80000 read, 44799 write accesses @4743294
|
||||
system.cpu0: completed 80000 read, 44555 write accesses @4750388
|
||||
system.cpu1: completed 80000 read, 44835 write accesses @4751884
|
||||
system.cpu5: completed 80000 read, 44235 write accesses @4755731
|
||||
system.cpu3: completed 80000 read, 44536 write accesses @4756531
|
||||
system.cpu7: completed 80000 read, 45051 write accesses @4789789
|
||||
system.cpu2: completed 90000 read, 50085 write accesses @5331779
|
||||
system.cpu1: completed 90000 read, 50520 write accesses @5335067
|
||||
system.cpu6: completed 90000 read, 50077 write accesses @5343428
|
||||
system.cpu4: completed 90000 read, 50348 write accesses @5344112
|
||||
system.cpu5: completed 90000 read, 49814 write accesses @5348125
|
||||
system.cpu3: completed 90000 read, 50170 write accesses @5349617
|
||||
system.cpu0: completed 90000 read, 50102 write accesses @5350612
|
||||
system.cpu7: completed 90000 read, 50733 write accesses @5394074
|
||||
system.cpu1: completed 100000 read, 56034 write accesses @5920895
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
system.cpu2: completed 10000 read, 5682 write accesses @468618
|
||||
system.cpu0: completed 10000 read, 5397 write accesses @470518
|
||||
system.cpu4: completed 10000 read, 5666 write accesses @470555
|
||||
system.cpu7: completed 10000 read, 5549 write accesses @473660
|
||||
system.cpu1: completed 10000 read, 5645 write accesses @474596
|
||||
system.cpu6: completed 10000 read, 5628 write accesses @480303
|
||||
system.cpu5: completed 10000 read, 5664 write accesses @480328
|
||||
system.cpu3: completed 10000 read, 5553 write accesses @482516
|
||||
system.cpu1: completed 20000 read, 11276 write accesses @941108
|
||||
system.cpu0: completed 20000 read, 10999 write accesses @944640
|
||||
system.cpu2: completed 20000 read, 11272 write accesses @946991
|
||||
system.cpu7: completed 20000 read, 10999 write accesses @947826
|
||||
system.cpu4: completed 20000 read, 11411 write accesses @948779
|
||||
system.cpu6: completed 20000 read, 11144 write accesses @953193
|
||||
system.cpu5: completed 20000 read, 11173 write accesses @954235
|
||||
system.cpu3: completed 20000 read, 11228 write accesses @961631
|
||||
system.cpu1: completed 30000 read, 16818 write accesses @1419188
|
||||
system.cpu0: completed 30000 read, 16479 write accesses @1420336
|
||||
system.cpu5: completed 30000 read, 16548 write accesses @1421142
|
||||
system.cpu2: completed 30000 read, 16790 write accesses @1421818
|
||||
system.cpu7: completed 30000 read, 16464 write accesses @1422123
|
||||
system.cpu4: completed 30000 read, 17005 write accesses @1422259
|
||||
system.cpu6: completed 30000 read, 16812 write accesses @1431146
|
||||
system.cpu3: completed 30000 read, 16876 write accesses @1437656
|
||||
system.cpu2: completed 40000 read, 22285 write accesses @1891081
|
||||
system.cpu5: completed 40000 read, 22160 write accesses @1896261
|
||||
system.cpu7: completed 40000 read, 21953 write accesses @1897179
|
||||
system.cpu1: completed 40000 read, 22536 write accesses @1897207
|
||||
system.cpu0: completed 40000 read, 21989 write accesses @1898643
|
||||
system.cpu6: completed 40000 read, 22334 write accesses @1898811
|
||||
system.cpu4: completed 40000 read, 22788 write accesses @1906823
|
||||
system.cpu3: completed 40000 read, 22523 write accesses @1907448
|
||||
system.cpu2: completed 50000 read, 27730 write accesses @2357928
|
||||
system.cpu5: completed 50000 read, 27750 write accesses @2363043
|
||||
system.cpu1: completed 50000 read, 28041 write accesses @2368230
|
||||
system.cpu6: completed 50000 read, 27966 write accesses @2376268
|
||||
system.cpu0: completed 50000 read, 27789 write accesses @2380452
|
||||
system.cpu3: completed 50000 read, 27901 write accesses @2382173
|
||||
system.cpu7: completed 50000 read, 27437 write accesses @2383988
|
||||
system.cpu4: completed 50000 read, 28553 write accesses @2384309
|
||||
system.cpu2: completed 60000 read, 33436 write accesses @2836829
|
||||
system.cpu5: completed 60000 read, 33223 write accesses @2839619
|
||||
system.cpu6: completed 60000 read, 33442 write accesses @2843227
|
||||
system.cpu1: completed 60000 read, 33632 write accesses @2850331
|
||||
system.cpu3: completed 60000 read, 33335 write accesses @2850932
|
||||
system.cpu0: completed 60000 read, 33499 write accesses @2853510
|
||||
system.cpu7: completed 60000 read, 33083 write accesses @2863799
|
||||
system.cpu4: completed 60000 read, 34211 write accesses @2865957
|
||||
system.cpu5: completed 70000 read, 38796 write accesses @3309970
|
||||
system.cpu2: completed 70000 read, 39076 write accesses @3312829
|
||||
system.cpu6: completed 70000 read, 38982 write accesses @3317982
|
||||
system.cpu3: completed 70000 read, 38893 write accesses @3320658
|
||||
system.cpu1: completed 70000 read, 39042 write accesses @3326984
|
||||
system.cpu0: completed 70000 read, 39160 write accesses @3330466
|
||||
system.cpu4: completed 70000 read, 39705 write accesses @3336097
|
||||
system.cpu7: completed 70000 read, 38681 write accesses @3351133
|
||||
system.cpu2: completed 80000 read, 44448 write accesses @3784665
|
||||
system.cpu5: completed 80000 read, 44282 write accesses @3786578
|
||||
system.cpu6: completed 80000 read, 44649 write accesses @3794509
|
||||
system.cpu3: completed 80000 read, 44408 write accesses @3795252
|
||||
system.cpu1: completed 80000 read, 44488 write accesses @3798206
|
||||
system.cpu0: completed 80000 read, 44824 write accesses @3800842
|
||||
system.cpu4: completed 80000 read, 45327 write accesses @3814610
|
||||
system.cpu7: completed 80000 read, 44370 write accesses @3836498
|
||||
system.cpu2: completed 90000 read, 50112 write accesses @4258356
|
||||
system.cpu5: completed 90000 read, 49726 write accesses @4263981
|
||||
system.cpu1: completed 90000 read, 49878 write accesses @4270068
|
||||
system.cpu6: completed 90000 read, 50189 write accesses @4270506
|
||||
system.cpu3: completed 90000 read, 50062 write accesses @4274971
|
||||
system.cpu0: completed 90000 read, 50500 write accesses @4278576
|
||||
system.cpu4: completed 90000 read, 51009 write accesses @4290694
|
||||
system.cpu7: completed 90000 read, 50035 write accesses @4314863
|
||||
system.cpu5: completed 100000 read, 55296 write accesses @4735173
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:32:54
|
||||
gem5 started Jan 22 2014 17:25:37
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
gem5 compiled Aug 13 2015 19:09:46
|
||||
gem5 started Aug 13 2015 20:15:24
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5795833 because maximum number of loads reached
|
||||
Exiting @ tick 4735173 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because one or more lines are too long
|
|
@ -1,85 +1,80 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu0: completed 10000 read, 5556 write accesses @879323
|
||||
system.cpu7: completed 10000 read, 5668 write accesses @879866
|
||||
system.cpu4: completed 10000 read, 5446 write accesses @880130
|
||||
system.cpu2: completed 10000 read, 5618 write accesses @882610
|
||||
system.cpu3: completed 10000 read, 5567 write accesses @889766
|
||||
system.cpu5: completed 10000 read, 5601 write accesses @889804
|
||||
system.cpu6: completed 10000 read, 5691 write accesses @907393
|
||||
system.cpu1: completed 10000 read, 5703 write accesses @911150
|
||||
system.cpu0: completed 20000 read, 11066 write accesses @1759277
|
||||
system.cpu7: completed 20000 read, 11260 write accesses @1770595
|
||||
system.cpu4: completed 20000 read, 11011 write accesses @1777119
|
||||
system.cpu2: completed 20000 read, 11410 write accesses @1779287
|
||||
system.cpu3: completed 20000 read, 11162 write accesses @1783007
|
||||
system.cpu5: completed 20000 read, 11166 write accesses @1789252
|
||||
system.cpu6: completed 20000 read, 11205 write accesses @1795677
|
||||
system.cpu1: completed 20000 read, 11246 write accesses @1799288
|
||||
system.cpu0: completed 30000 read, 16538 write accesses @2628765
|
||||
system.cpu4: completed 30000 read, 16331 write accesses @2649038
|
||||
system.cpu3: completed 30000 read, 16729 write accesses @2656841
|
||||
system.cpu7: completed 30000 read, 16821 write accesses @2657779
|
||||
system.cpu2: completed 30000 read, 16942 write accesses @2665738
|
||||
system.cpu6: completed 30000 read, 16767 write accesses @2683028
|
||||
system.cpu5: completed 30000 read, 16740 write accesses @2683223
|
||||
system.cpu1: completed 30000 read, 16843 write accesses @2687354
|
||||
system.cpu0: completed 40000 read, 21978 write accesses @3518323
|
||||
system.cpu4: completed 40000 read, 21923 write accesses @3532643
|
||||
system.cpu2: completed 40000 read, 22312 write accesses @3539629
|
||||
system.cpu7: completed 40000 read, 22397 write accesses @3540563
|
||||
system.cpu3: completed 40000 read, 22394 write accesses @3545743
|
||||
system.cpu1: completed 40000 read, 22522 write accesses @3569491
|
||||
system.cpu6: completed 40000 read, 22217 write accesses @3571115
|
||||
system.cpu5: completed 40000 read, 22361 write accesses @3575245
|
||||
system.cpu0: completed 50000 read, 27412 write accesses @4395937
|
||||
system.cpu4: completed 50000 read, 27504 write accesses @4402816
|
||||
system.cpu2: completed 50000 read, 27861 write accesses @4421377
|
||||
system.cpu7: completed 50000 read, 28050 write accesses @4432946
|
||||
system.cpu3: completed 50000 read, 28057 write accesses @4453484
|
||||
system.cpu5: completed 50000 read, 28091 write accesses @4459262
|
||||
system.cpu6: completed 50000 read, 27767 write accesses @4466993
|
||||
system.cpu1: completed 50000 read, 28057 write accesses @4473556
|
||||
system.cpu0: completed 60000 read, 33045 write accesses @5302811
|
||||
system.cpu2: completed 60000 read, 33521 write accesses @5307713
|
||||
system.cpu4: completed 60000 read, 33106 write accesses @5309735
|
||||
system.cpu3: completed 60000 read, 33613 write accesses @5326889
|
||||
system.cpu7: completed 60000 read, 33738 write accesses @5327419
|
||||
system.cpu1: completed 60000 read, 33648 write accesses @5345018
|
||||
system.cpu6: completed 60000 read, 33262 write accesses @5350442
|
||||
system.cpu5: completed 60000 read, 33765 write accesses @5365882
|
||||
system.cpu4: completed 70000 read, 38688 write accesses @6177299
|
||||
system.cpu0: completed 70000 read, 38751 write accesses @6203477
|
||||
system.cpu2: completed 70000 read, 39098 write accesses @6206063
|
||||
system.cpu3: completed 70000 read, 39126 write accesses @6219412
|
||||
system.cpu1: completed 70000 read, 39169 write accesses @6222370
|
||||
system.cpu6: completed 70000 read, 38802 write accesses @6223076
|
||||
system.cpu7: completed 70000 read, 39595 write accesses @6226670
|
||||
system.cpu5: completed 70000 read, 39326 write accesses @6257626
|
||||
system.cpu4: completed 80000 read, 44383 write accesses @7068978
|
||||
system.cpu2: completed 80000 read, 44769 write accesses @7095466
|
||||
system.cpu3: completed 80000 read, 44569 write accesses @7095782
|
||||
system.cpu0: completed 80000 read, 44509 write accesses @7100023
|
||||
system.cpu6: completed 80000 read, 44542 write accesses @7108504
|
||||
system.cpu1: completed 80000 read, 44592 write accesses @7113439
|
||||
system.cpu7: completed 80000 read, 45281 write accesses @7113500
|
||||
system.cpu5: completed 80000 read, 44911 write accesses @7150684
|
||||
system.cpu4: completed 90000 read, 50048 write accesses @7961758
|
||||
system.cpu0: completed 90000 read, 49958 write accesses @7968130
|
||||
system.cpu2: completed 90000 read, 50371 write accesses @7973060
|
||||
system.cpu3: completed 90000 read, 50104 write accesses @7976843
|
||||
system.cpu7: completed 90000 read, 50805 write accesses @7986452
|
||||
system.cpu6: completed 90000 read, 50102 write accesses @7998542
|
||||
system.cpu1: completed 90000 read, 50241 write accesses @7999593
|
||||
system.cpu5: completed 90000 read, 50481 write accesses @8039612
|
||||
system.cpu7: completed 100000 read, 56250 write accesses @8851106
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
system.cpu3: completed 10000 read, 5525 write accesses @760625
|
||||
system.cpu5: completed 10000 read, 5663 write accesses @765664
|
||||
system.cpu1: completed 10000 read, 5656 write accesses @767292
|
||||
system.cpu4: completed 10000 read, 5509 write accesses @775011
|
||||
system.cpu6: completed 10000 read, 5563 write accesses @775672
|
||||
system.cpu0: completed 10000 read, 5617 write accesses @776185
|
||||
system.cpu2: completed 10000 read, 5515 write accesses @776720
|
||||
system.cpu7: completed 10000 read, 5487 write accesses @777568
|
||||
system.cpu3: completed 20000 read, 11028 write accesses @1517020
|
||||
system.cpu4: completed 20000 read, 10944 write accesses @1530984
|
||||
system.cpu6: completed 20000 read, 11090 write accesses @1531354
|
||||
system.cpu1: completed 20000 read, 11154 write accesses @1539725
|
||||
system.cpu2: completed 20000 read, 10831 write accesses @1540287
|
||||
system.cpu7: completed 20000 read, 11114 write accesses @1543700
|
||||
system.cpu5: completed 20000 read, 11175 write accesses @1554030
|
||||
system.cpu0: completed 20000 read, 11186 write accesses @1559187
|
||||
system.cpu3: completed 30000 read, 16598 write accesses @2283007
|
||||
system.cpu1: completed 30000 read, 16605 write accesses @2291164
|
||||
system.cpu4: completed 30000 read, 16704 write accesses @2303776
|
||||
system.cpu6: completed 30000 read, 16727 write accesses @2310983
|
||||
system.cpu5: completed 30000 read, 16800 write accesses @2319374
|
||||
system.cpu0: completed 30000 read, 16827 write accesses @2322838
|
||||
system.cpu2: completed 30000 read, 16435 write accesses @2325373
|
||||
system.cpu7: completed 30000 read, 16664 write accesses @2329585
|
||||
system.cpu3: completed 40000 read, 22203 write accesses @3054702
|
||||
system.cpu1: completed 40000 read, 22271 write accesses @3064092
|
||||
system.cpu4: completed 40000 read, 22104 write accesses @3064313
|
||||
system.cpu0: completed 40000 read, 22287 write accesses @3078243
|
||||
system.cpu2: completed 40000 read, 22034 write accesses @3081341
|
||||
system.cpu6: completed 40000 read, 22288 write accesses @3087106
|
||||
system.cpu7: completed 40000 read, 22139 write accesses @3090483
|
||||
system.cpu5: completed 40000 read, 22456 write accesses @3115167
|
||||
system.cpu3: completed 50000 read, 27685 write accesses @3816500
|
||||
system.cpu0: completed 50000 read, 27819 write accesses @3832053
|
||||
system.cpu4: completed 50000 read, 27741 write accesses @3843043
|
||||
system.cpu6: completed 50000 read, 27737 write accesses @3846249
|
||||
system.cpu1: completed 50000 read, 27853 write accesses @3847483
|
||||
system.cpu2: completed 50000 read, 27474 write accesses @3847984
|
||||
system.cpu7: completed 50000 read, 27784 write accesses @3859638
|
||||
system.cpu5: completed 50000 read, 27985 write accesses @3881373
|
||||
system.cpu3: completed 60000 read, 33240 write accesses @4586843
|
||||
system.cpu0: completed 60000 read, 33283 write accesses @4597223
|
||||
system.cpu4: completed 60000 read, 33280 write accesses @4612495
|
||||
system.cpu6: completed 60000 read, 33333 write accesses @4617744
|
||||
system.cpu7: completed 60000 read, 33161 write accesses @4621422
|
||||
system.cpu1: completed 60000 read, 33491 write accesses @4624484
|
||||
system.cpu2: completed 60000 read, 33073 write accesses @4629780
|
||||
system.cpu5: completed 60000 read, 33544 write accesses @4644282
|
||||
system.cpu4: completed 70000 read, 38779 write accesses @5369467
|
||||
system.cpu0: completed 70000 read, 38963 write accesses @5378485
|
||||
system.cpu3: completed 70000 read, 38978 write accesses @5379251
|
||||
system.cpu6: completed 70000 read, 38932 write accesses @5401655
|
||||
system.cpu1: completed 70000 read, 39086 write accesses @5406571
|
||||
system.cpu2: completed 70000 read, 38592 write accesses @5406836
|
||||
system.cpu5: completed 70000 read, 39048 write accesses @5413732
|
||||
system.cpu7: completed 70000 read, 38996 write accesses @5416693
|
||||
system.cpu4: completed 80000 read, 44330 write accesses @6131353
|
||||
system.cpu3: completed 80000 read, 44590 write accesses @6147147
|
||||
system.cpu0: completed 80000 read, 44469 write accesses @6155707
|
||||
system.cpu2: completed 80000 read, 44132 write accesses @6161312
|
||||
system.cpu1: completed 80000 read, 44704 write accesses @6173967
|
||||
system.cpu6: completed 80000 read, 44443 write accesses @6181977
|
||||
system.cpu5: completed 80000 read, 44606 write accesses @6182931
|
||||
system.cpu7: completed 80000 read, 44440 write accesses @6186571
|
||||
system.cpu4: completed 90000 read, 49946 write accesses @6904148
|
||||
system.cpu3: completed 90000 read, 50248 write accesses @6916525
|
||||
system.cpu0: completed 90000 read, 49962 write accesses @6927054
|
||||
system.cpu2: completed 90000 read, 49754 write accesses @6935410
|
||||
system.cpu6: completed 90000 read, 49929 write accesses @6947145
|
||||
system.cpu1: completed 90000 read, 50385 write accesses @6951341
|
||||
system.cpu5: completed 90000 read, 50139 write accesses @6962538
|
||||
system.cpu7: completed 90000 read, 50280 write accesses @6972720
|
||||
system.cpu4: completed 100000 read, 55350 write accesses @7662866
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:32
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
gem5 compiled Aug 13 2015 19:05:56
|
||||
gem5 started Aug 13 2015 20:15:04
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 8664886 because maximum number of loads reached
|
||||
Exiting @ tick 7662866 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,7 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
|
|
|
|||
|
|
@ -1,12 +1,11 @@
|
|||
Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
|
||||
Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Aug 28 2014 02:49:35
|
||||
gem5 started Aug 28 2014 02:49:49
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
|
||||
gem5 compiled Aug 13 2015 19:16:05
|
||||
gem5 started Aug 13 2015 20:15:53
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 312261 because Ruby Tester completed
|
||||
Exiting @ tick 42571 because Ruby Tester completed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,7 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:42:56
|
||||
gem5 started Jan 22 2014 17:27:15
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
gem5 compiled Aug 13 2015 19:22:33
|
||||
gem5 started Aug 13 2015 20:16:24
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 327361 because Ruby Tester completed
|
||||
Exiting @ tick 54131 because Ruby Tester completed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,7 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:47:59
|
||||
gem5 started Jan 22 2014 17:27:41
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
gem5 compiled Aug 13 2015 19:28:58
|
||||
gem5 started Aug 13 2015 20:17:44
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 225141 because Ruby Tester completed
|
||||
Exiting @ tick 50521 because Ruby Tester completed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,7 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:32:54
|
||||
gem5 started Jan 22 2014 17:25:38
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
gem5 compiled Aug 13 2015 19:09:46
|
||||
gem5 started Aug 13 2015 20:15:31
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 172201 because Ruby Tester completed
|
||||
Exiting @ tick 28761 because Ruby Tester completed
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,4 +1,7 @@
|
|||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
1.250000 rounded to 1
|
||||
warn: rounding error > tolerance
|
||||
1.250000 rounded to 1
|
||||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
|
||||
|
|
|
|||
|
|
@ -1,10 +1,11 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jan 22 2014 16:27:55
|
||||
gem5 started Jan 22 2014 17:24:37
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
|
||||
gem5 compiled Aug 13 2015 19:05:56
|
||||
gem5 started Aug 13 2015 20:15:05
|
||||
gem5 executing on artery
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /home/joel/research/gem5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
|
||||
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 221941 because Ruby Tester completed
|
||||
Exiting @ tick 37801 because Ruby Tester completed
|
||||
|
|
|
|||
|
|
@ -1,44 +1,44 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000233 # Number of seconds simulated
|
||||
sim_ticks 233251 # Number of ticks simulated
|
||||
final_tick 233251 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000038 # Number of seconds simulated
|
||||
sim_ticks 37801 # Number of ticks simulated
|
||||
final_tick 37801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 4652644 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 446260 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 411997 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 398128 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 58944 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 58944 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 58752 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 58752 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 921 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 921 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 918 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 918 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 252706312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 252706312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 251883164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 251883164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 504589477 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 504589477 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 921 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 918 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 921 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 918 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 50624 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 61504 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 61504 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 61312 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 61312 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 961 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 961 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 958 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 958 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1627046904 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 1627046904 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 1621967673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 1621967673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 3249014576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 3249014576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 961 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 958 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 961 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 958 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 53184 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 8320 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 49472 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 58944 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 58752 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.bytesWritten 52736 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 61504 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 61312 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 247 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 234 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 258 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::0 284 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 229 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 263 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 55 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
|
||||
|
|
@ -51,10 +51,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe
|
|||
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 237 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 229 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 256 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 279 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 228 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 259 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 58 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
|
|
@ -69,24 +69,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 232954 # Total gap between requests
|
||||
system.mem_ctrls.totGap 37739 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 921 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 961 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 918 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 668 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 123 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.writePktSize::6 958 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 472 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 358 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -131,24 +131,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 44 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 47 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 48 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 53 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 52 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 52 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 54 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 73 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 51 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -180,342 +180,327 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
|
|||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 156 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 632.615385 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 446.819615 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 383.170651 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 20 12.82% 12.82% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 19 12.18% 25.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 11 7.05% 32.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 9 5.77% 37.82% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 10 6.41% 44.23% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 12 7.69% 51.92% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 9 5.77% 57.69% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 10 6.41% 64.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 56 35.90% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 156 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 45 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 17.311111 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 17.138581 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.968181 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 6 13.33% 13.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 18 40.00% 53.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 20 44.44% 97.78% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.22% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 45 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 45 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.177778 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 17.147333 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.028876 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 19 42.22% 42.22% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 25 55.56% 97.78% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 2.22% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 45 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 7966 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 22995 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3955 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 10.07 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 961.174312 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 916.871548 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 196.872813 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 3 2.75% 2.75% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 2 1.83% 4.59% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 1 0.92% 5.50% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 3 2.75% 8.26% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 1.83% 10.09% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 2.75% 12.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 95 87.16% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 51 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.176471 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.043156 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.718131 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 10 19.61% 19.61% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 40 78.43% 98.04% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 1.96% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 51 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 51 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.156863 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.152882 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.367290 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 43 84.31% 84.31% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 8 15.69% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 51 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 10313 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 26102 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4155 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 12.41 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 29.07 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 217.04 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 212.10 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 252.71 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 251.88 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgMemAccLat 31.41 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 1406.95 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 1395.10 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 1627.05 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 1621.97 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 3.35 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 1.70 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 1.66 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.79 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 638 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 766 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.66 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 95.51 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 126.67 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 1171800 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 651000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 9597120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 7848576 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 153780300 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 737400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 188534436 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 834.023888 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 697 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 7540 # Time in different power states
|
||||
system.mem_ctrls.busUtil 21.89 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 10.99 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 10.90 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.72 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.90 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 725 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 817 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 87.24 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 96.57 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 19.67 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 91.95 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_0.readEnergy 8561280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_0.writeEnergy 7039872 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_0.actBackEnergy 21405780 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_0.preBackEnergy 65400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_0.totalEnergy 40188492 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_0.averagePower 1279.725258 # Core power per rank (mW)
|
||||
system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 218097 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT 30367 # Time in different power states
|
||||
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls_1.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 4879656 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 131343600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 150971496 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 667.897257 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 218514 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 7540 # Time in different power states
|
||||
system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls_1.actBackEnergy 673056 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls_1.preBackEnergy 18243600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls_1.totalEnergy 20950896 # Total energy per rank (pJ)
|
||||
system.mem_ctrls_1.averagePower 667.438547 # Core power per rank (mW)
|
||||
system.mem_ctrls_1.memoryStateTime::IDLE 30364 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
|
||||
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 2 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 19 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1839 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.295813 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.367881 # delay histogram for all message
|
||||
system.ruby.delayHist | 1732 94.18% 94.18% | 33 1.79% 95.98% | 21 1.14% 97.12% | 29 1.58% 98.69% | 15 0.82% 99.51% | 5 0.27% 99.78% | 3 0.16% 99.95% | 1 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1839 # delay histogram for all message
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1919 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.195935 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.060802 # delay histogram for all message
|
||||
system.ruby.delayHist | 1855 96.66% 96.66% | 0 0.00% 96.66% | 1 0.05% 96.72% | 0 0.00% 96.72% | 2 0.10% 96.82% | 0 0.00% 96.82% | 61 3.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1919 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 971
|
||||
system.ruby.outstanding_req_hist::mean 15.772400
|
||||
system.ruby.outstanding_req_hist::gmean 15.670098
|
||||
system.ruby.outstanding_req_hist::stdev 1.157985
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 2 0.21% 0.93% | 2 0.21% 1.13% | 2 0.21% 1.34% | 98 10.09% 11.43% | 860 88.57% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 971
|
||||
system.ruby.latency_hist::bucket_size 1024
|
||||
system.ruby.latency_hist::max_bucket 10239
|
||||
system.ruby.latency_hist::samples 956
|
||||
system.ruby.latency_hist::mean 3857.955021
|
||||
system.ruby.latency_hist::gmean 3808.152723
|
||||
system.ruby.latency_hist::stdev 536.282596
|
||||
system.ruby.latency_hist | 4 0.42% 0.42% | 4 0.42% 0.84% | 37 3.87% 4.71% | 609 63.70% 68.41% | 298 31.17% 99.58% | 4 0.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 956
|
||||
system.ruby.hit_latency_hist::bucket_size 512
|
||||
system.ruby.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.hit_latency_hist::samples 35
|
||||
system.ruby.hit_latency_hist::mean 3398.942857
|
||||
system.ruby.hit_latency_hist::gmean 3374.308107
|
||||
system.ruby.hit_latency_hist::stdev 410.898796
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.86% 2.86% | 8 22.86% 25.71% | 11 31.43% 57.14% | 14 40.00% 97.14% | 1 2.86% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 35
|
||||
system.ruby.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.miss_latency_hist::samples 921
|
||||
system.ruby.miss_latency_hist::mean 3875.398480
|
||||
system.ruby.miss_latency_hist::gmean 3825.697233
|
||||
system.ruby.miss_latency_hist::stdev 532.898268
|
||||
system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 921
|
||||
system.ruby.Directory.incomplete_times 921
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 35 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 923 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 958 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 117 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store
|
||||
system.ruby.outstanding_req_hist::samples 1017
|
||||
system.ruby.outstanding_req_hist::mean 15.607670
|
||||
system.ruby.outstanding_req_hist::gmean 15.500838
|
||||
system.ruby.outstanding_req_hist::stdev 1.236128
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 3 0.29% 1.38% | 3 0.29% 1.67% | 233 22.91% 24.58% | 767 75.42% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 1017
|
||||
system.ruby.latency_hist::bucket_size 128
|
||||
system.ruby.latency_hist::max_bucket 1279
|
||||
system.ruby.latency_hist::samples 1003
|
||||
system.ruby.latency_hist::mean 586.918245
|
||||
system.ruby.latency_hist::gmean 576.888257
|
||||
system.ruby.latency_hist::stdev 98.601394
|
||||
system.ruby.latency_hist | 2 0.20% 0.20% | 9 0.90% 1.10% | 6 0.60% 1.69% | 138 13.76% 15.45% | 667 66.50% 81.95% | 127 12.66% 94.62% | 42 4.19% 98.80% | 12 1.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 1003
|
||||
system.ruby.hit_latency_hist::bucket_size 128
|
||||
system.ruby.hit_latency_hist::max_bucket 1279
|
||||
system.ruby.hit_latency_hist::samples 42
|
||||
system.ruby.hit_latency_hist::mean 502
|
||||
system.ruby.hit_latency_hist::gmean 497.343988
|
||||
system.ruby.hit_latency_hist::stdev 68.792371
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.38% 2.38% | 20 47.62% 50.00% | 20 47.62% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 42
|
||||
system.ruby.miss_latency_hist::bucket_size 128
|
||||
system.ruby.miss_latency_hist::max_bucket 1279
|
||||
system.ruby.miss_latency_hist::samples 961
|
||||
system.ruby.miss_latency_hist::mean 590.629553
|
||||
system.ruby.miss_latency_hist::gmean 580.641121
|
||||
system.ruby.miss_latency_hist::stdev 98.062205
|
||||
system.ruby.miss_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 961
|
||||
system.ruby.Directory.incomplete_times 961
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 963 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 1005 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 127 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 1.971696
|
||||
system.ruby.network.routers0.msg_count.Control::2 921
|
||||
system.ruby.network.routers0.msg_count.Data::2 919
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 66168
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers1.percent_links_utilized 1.971053
|
||||
system.ruby.network.routers1.msg_count.Control::2 921
|
||||
system.ruby.network.routers1.msg_count.Data::2 918
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.percent_links_utilized 1.971053
|
||||
system.ruby.network.routers2.msg_count.Control::2 921
|
||||
system.ruby.network.routers2.msg_count.Data::2 918
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.msg_count.Control 2763
|
||||
system.ruby.network.msg_count.Data 2755
|
||||
system.ruby.network.msg_count.Response_Data 2763
|
||||
system.ruby.network.msg_count.Writeback_Control 2754
|
||||
system.ruby.network.msg_byte.Control 22104
|
||||
system.ruby.network.msg_byte.Data 198360
|
||||
system.ruby.network.msg_byte.Response_Data 198936
|
||||
system.ruby.network.msg_byte.Writeback_Control 22032
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.973625
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers0.throttle1.link_utilization 1.969766
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 921
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 919
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 66168
|
||||
system.ruby.network.routers1.throttle0.link_utilization 1.968480
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 921
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 918
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers1.throttle1.link_utilization 1.973625
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.973625
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.968480
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 921
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 918
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 66096
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 921 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.408252 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 1.494373 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 839 91.10% 91.10% | 28 3.04% 94.14% | 20 2.17% 96.31% | 21 2.28% 98.59% | 9 0.98% 99.57% | 3 0.33% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 921 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 2 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 19 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 918 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.183007 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 1.218386 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 893 97.28% 97.28% | 5 0.54% 97.82% | 1 0.11% 97.93% | 8 0.87% 98.80% | 6 0.65% 99.46% | 2 0.22% 99.67% | 2 0.22% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 918 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 512
|
||||
system.ruby.LD.latency_hist::max_bucket 5119
|
||||
system.ruby.LD.latency_hist::samples 46
|
||||
system.ruby.LD.latency_hist::mean 3901.739130
|
||||
system.ruby.LD.latency_hist::gmean 3880.241355
|
||||
system.ruby.LD.latency_hist::stdev 413.461724
|
||||
system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.17% 2.17% | 11 23.91% 26.09% | 18 39.13% 65.22% | 14 30.43% 95.65% | 2 4.35% 100.00%
|
||||
system.ruby.LD.latency_hist::total 46
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 512
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.network.routers0.percent_links_utilized 12.694109
|
||||
system.ruby.network.routers0.msg_count.Control::2 961
|
||||
system.ruby.network.routers0.msg_count.Data::2 959
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 69048
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.routers1.percent_links_utilized 12.691463
|
||||
system.ruby.network.routers1.msg_count.Control::2 961
|
||||
system.ruby.network.routers1.msg_count.Data::2 958
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 68976
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.routers2.percent_links_utilized 12.691463
|
||||
system.ruby.network.routers2.msg_count.Control::2 961
|
||||
system.ruby.network.routers2.msg_count.Data::2 958
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 68976
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.msg_count.Control 2883
|
||||
system.ruby.network.msg_count.Data 2875
|
||||
system.ruby.network.msg_count.Response_Data 2883
|
||||
system.ruby.network.msg_count.Writeback_Control 2874
|
||||
system.ruby.network.msg_byte.Control 23064
|
||||
system.ruby.network.msg_byte.Data 207000
|
||||
system.ruby.network.msg_byte.Response_Data 207576
|
||||
system.ruby.network.msg_byte.Writeback_Control 22992
|
||||
system.ruby.network.routers0.throttle0.link_utilization 12.707336
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.routers0.throttle1.link_utilization 12.680881
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 961
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 959
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 69048
|
||||
system.ruby.network.routers1.throttle0.link_utilization 12.675591
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 961
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 958
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68976
|
||||
system.ruby.network.routers1.throttle1.link_utilization 12.707336
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.routers2.throttle0.link_utilization 12.707336
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 961
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 958
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 69192
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7664
|
||||
system.ruby.network.routers2.throttle1.link_utilization 12.675591
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 961
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 958
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7688
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68976
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 961 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 961 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 961 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 958 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.392484 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 1.475833 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 894 93.32% 93.32% | 0 0.00% 93.32% | 1 0.10% 93.42% | 0 0.00% 93.42% | 2 0.21% 93.63% | 0 0.00% 93.63% | 61 6.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 958 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 128
|
||||
system.ruby.LD.latency_hist::max_bucket 1279
|
||||
system.ruby.LD.latency_hist::samples 47
|
||||
system.ruby.LD.latency_hist::mean 581.170213
|
||||
system.ruby.LD.latency_hist::gmean 573.743591
|
||||
system.ruby.LD.latency_hist::stdev 97.598850
|
||||
system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 23.40% 23.40% | 29 61.70% 85.11% | 4 8.51% 93.62% | 2 4.26% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 47
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 64
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 639
|
||||
system.ruby.LD.hit_latency_hist::samples 1
|
||||
system.ruby.LD.hit_latency_hist::mean 3037
|
||||
system.ruby.LD.hit_latency_hist::gmean 3037.000000
|
||||
system.ruby.LD.hit_latency_hist::mean 386
|
||||
system.ruby.LD.hit_latency_hist::gmean 386.000000
|
||||
system.ruby.LD.hit_latency_hist::stdev nan
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 1
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 512
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.miss_latency_hist::samples 45
|
||||
system.ruby.LD.miss_latency_hist::mean 3920.955556
|
||||
system.ruby.LD.miss_latency_hist::gmean 3901.427082
|
||||
system.ruby.LD.miss_latency_hist::stdev 396.816477
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 24.44% 24.44% | 18 40.00% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 45
|
||||
system.ruby.ST.latency_hist::bucket_size 1024
|
||||
system.ruby.ST.latency_hist::max_bucket 10239
|
||||
system.ruby.ST.latency_hist::samples 856
|
||||
system.ruby.ST.latency_hist::mean 3853.304907
|
||||
system.ruby.ST.latency_hist::gmean 3800.468487
|
||||
system.ruby.ST.latency_hist::stdev 547.762073
|
||||
system.ruby.ST.latency_hist | 4 0.47% 0.47% | 4 0.47% 0.93% | 35 4.09% 5.02% | 547 63.90% 68.93% | 262 30.61% 99.53% | 4 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 856
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 512
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.ST.hit_latency_hist::samples 33
|
||||
system.ruby.ST.hit_latency_hist::mean 3403.939394
|
||||
system.ruby.ST.hit_latency_hist::gmean 3378.573502
|
||||
system.ruby.ST.hit_latency_hist::stdev 417.201535
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 7 21.21% 24.24% | 11 33.33% 57.58% | 13 39.39% 96.97% | 1 3.03% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 33
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.ST.miss_latency_hist::samples 823
|
||||
system.ruby.ST.miss_latency_hist::mean 3871.323208
|
||||
system.ruby.ST.miss_latency_hist::gmean 3818.442488
|
||||
system.ruby.ST.miss_latency_hist::stdev 544.868028
|
||||
system.ruby.ST.miss_latency_hist | 4 0.49% 0.49% | 4 0.49% 0.97% | 27 3.28% 4.25% | 523 63.55% 67.80% | 261 31.71% 99.51% | 4 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 823
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.latency_hist::samples 54
|
||||
system.ruby.IFETCH.latency_hist::mean 3894.370370
|
||||
system.ruby.IFETCH.latency_hist::gmean 3869.743086
|
||||
system.ruby.IFETCH.latency_hist::stdev 439.746423
|
||||
system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.85% 1.85% | 13 24.07% 25.93% | 20 37.04% 62.96% | 17 31.48% 94.44% | 3 5.56% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 54
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 1
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3596
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3596.000000
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev nan
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 1
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 128
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 1279
|
||||
system.ruby.LD.miss_latency_hist::samples 46
|
||||
system.ruby.LD.miss_latency_hist::mean 585.413043
|
||||
system.ruby.LD.miss_latency_hist::gmean 578.708439
|
||||
system.ruby.LD.miss_latency_hist::stdev 94.193082
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 46
|
||||
system.ruby.ST.latency_hist::bucket_size 128
|
||||
system.ruby.ST.latency_hist::max_bucket 1279
|
||||
system.ruby.ST.latency_hist::samples 903
|
||||
system.ruby.ST.latency_hist::mean 587.266888
|
||||
system.ruby.ST.latency_hist::gmean 576.890095
|
||||
system.ruby.ST.latency_hist::stdev 99.206221
|
||||
system.ruby.ST.latency_hist | 2 0.22% 0.22% | 9 1.00% 1.22% | 6 0.66% 1.88% | 116 12.85% 14.73% | 602 66.67% 81.40% | 120 13.29% 94.68% | 37 4.10% 98.78% | 11 1.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 903
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 128
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 1279
|
||||
system.ruby.ST.hit_latency_hist::samples 41
|
||||
system.ruby.ST.hit_latency_hist::mean 504.829268
|
||||
system.ruby.ST.hit_latency_hist::gmean 500.427879
|
||||
system.ruby.ST.hit_latency_hist::stdev 67.127454
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.44% 2.44% | 19 46.34% 48.78% | 20 48.78% 97.56% | 1 2.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 41
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 128
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 1279
|
||||
system.ruby.ST.miss_latency_hist::samples 862
|
||||
system.ruby.ST.miss_latency_hist::mean 591.187935
|
||||
system.ruby.ST.miss_latency_hist::gmean 580.804835
|
||||
system.ruby.ST.miss_latency_hist::stdev 98.803760
|
||||
system.ruby.ST.miss_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 862
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 128
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 1279
|
||||
system.ruby.IFETCH.latency_hist::samples 53
|
||||
system.ruby.IFETCH.latency_hist::mean 586.075472
|
||||
system.ruby.IFETCH.latency_hist::gmean 579.659874
|
||||
system.ruby.IFETCH.latency_hist::stdev 90.344820
|
||||
system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 53
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 128
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 53
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 3900
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 3875.103542
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 441.985729
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 586.075472
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 579.659874
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 90.344820
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 53
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 921
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 3875.398480
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 3825.697233
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 532.898268
|
||||
system.ruby.Directory.miss_mach_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 921
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 45
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3920.955556
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3901.427082
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 396.816477
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 24.44% 24.44% | 18 40.00% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 45
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 823
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3871.323208
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3818.442488
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 544.868028
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 4 0.49% 0.49% | 4 0.49% 0.97% | 27 3.28% 4.25% | 523 63.55% 67.80% | 261 31.71% 99.51% | 4 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 823
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 128
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 1279
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 961
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 590.629553
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 580.641121
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 98.062205
|
||||
system.ruby.Directory.miss_mach_latency_hist | 2 0.21% 0.21% | 9 0.94% 1.14% | 5 0.52% 1.66% | 118 12.28% 13.94% | 647 67.33% 81.27% | 126 13.11% 94.38% | 42 4.37% 98.75% | 12 1.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 961
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 128
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 1279
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 46
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 585.413043
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 578.708439
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 94.193082
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 21.74% 21.74% | 29 63.04% 84.78% | 4 8.70% 93.48% | 2 4.35% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 46
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 128
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 1279
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 862
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 591.187935
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 580.804835
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 98.803760
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 2 0.23% 0.23% | 9 1.04% 1.28% | 5 0.58% 1.86% | 97 11.25% 13.11% | 582 67.52% 80.63% | 119 13.81% 94.43% | 37 4.29% 98.72% | 11 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 862
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 128
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 1279
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 53
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 3900
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3875.103542
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 441.985729
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 586.075472
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 579.659874
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 90.344820
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 20.75% 20.75% | 36 67.92% 88.68% | 3 5.66% 94.34% | 3 5.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53
|
||||
system.ruby.Directory_Controller.GETX 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Load 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 857 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 921 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Replacement 920 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 918 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 45 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 54 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 824 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 961 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 958 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 961 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 958 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 961 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 958 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 961 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 958 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Load 47 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 53 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 905 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 961 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Replacement 960 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 958 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 53 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 864 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement 920 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 918 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 98 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data 823 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 41 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement 960 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 958 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 99 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data 862 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue