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ruby: Protocol changes for SimObject MessageBuffers

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This commit is contained in:
Joel Hestness 2015-08-14 00:19:45 -05:00
parent 581bae9ecb
commit 905c0b347c
29 changed files with 386 additions and 233 deletions
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64
configs/ruby/MESI_Three_Level.py
View file

@ -127,16 +127,24 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L0 and L1 controllers
l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
l0_cntrl.mandatoryQueue = MessageBuffer()
l0_cntrl.bufferToL1 = MessageBuffer(ordered = True)
l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1
l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True)
l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1
# Connect the L1 controllers and the network
l1_cntrl.requestToL2 = ruby_system.network.slave
l1_cntrl.responseToL2 = ruby_system.network.slave
l1_cntrl.unblockToL2 = ruby_system.network.slave
l1_cntrl.requestToL2 = MessageBuffer()
l1_cntrl.requestToL2.master = ruby_system.network.slave
l1_cntrl.responseToL2 = MessageBuffer()
l1_cntrl.responseToL2.master = ruby_system.network.slave
l1_cntrl.unblockToL2 = MessageBuffer()
l1_cntrl.unblockToL2.master = ruby_system.network.slave
l1_cntrl.requestFromL2 = ruby_system.network.master
l1_cntrl.responseFromL2 = ruby_system.network.master
l1_cntrl.requestFromL2 = MessageBuffer()
l1_cntrl.requestFromL2.slave = ruby_system.network.master
l1_cntrl.responseFromL2 = MessageBuffer()
l1_cntrl.responseFromL2.slave = ruby_system.network.master
for j in xrange(num_l2caches_per_cluster):
@ -155,13 +163,19 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l2_cntrl_nodes.append(l2_cntrl)
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = ruby_system.network.slave
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.unblockToL2Cache = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
l2_cntrl.responseToL2Cache = ruby_system.network.master
l2_cntrl.unblockToL2Cache = MessageBuffer()
l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
@ -191,9 +205,13 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
#
@ -212,8 +230,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.requestToDir = ruby_system.network.slave
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
all_cntrls = l0_cntrl_nodes + \
l1_cntrl_nodes + \
@ -231,8 +252,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.requestToDir = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
all_cntrls = all_cntrls + [io_controller]

60
configs/ruby/MESI_Two_Level.py
View file

@ -107,12 +107,20 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L1 controllers and the network
l1_cntrl.requestFromL1Cache = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = ruby_system.network.slave
l1_cntrl.unblockFromL1Cache = ruby_system.network.slave
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.unblockFromL1Cache = MessageBuffer()
l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestToL1Cache = ruby_system.network.master
l1_cntrl.responseToL1Cache = ruby_system.network.master
l1_cntrl.optionalQueue = MessageBuffer()
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l2_index_start = block_size_bits + l2_bits
@ -134,13 +142,19 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l2_cntrl_nodes.append(l2_cntrl)
# Connect the L2 controllers and the network
l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = ruby_system.network.slave
l2_cntrl.DirRequestFromL2Cache = MessageBuffer()
l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.unblockToL2Cache = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
l2_cntrl.responseToL2Cache = ruby_system.network.master
l2_cntrl.unblockToL2Cache = MessageBuffer()
l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
@ -169,9 +183,13 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
@ -189,8 +207,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.requestToDir = ruby_system.network.slave
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
@ -207,8 +228,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.requestToDir = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
all_cntrls = all_cntrls + [io_controller]

44
configs/ruby/MI_example.py
View file

@ -98,11 +98,15 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L1 controllers and the network
l1_cntrl.requestFromCache = ruby_system.network.slave
l1_cntrl.responseFromCache = ruby_system.network.slave
l1_cntrl.forwardToCache = ruby_system.network.master
l1_cntrl.responseToCache = ruby_system.network.master
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
l1_cntrl.requestFromCache.master = ruby_system.network.slave
l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
l1_cntrl.responseFromCache.master = ruby_system.network.slave
l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
l1_cntrl.forwardToCache.slave = ruby_system.network.master
l1_cntrl.responseToCache = MessageBuffer(ordered = True)
l1_cntrl.responseToCache.slave = ruby_system.network.master
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
@ -128,12 +132,18 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.dmaRequestToDir = ruby_system.network.master
dir_cntrl.requestToDir = MessageBuffer(ordered = True)
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
dir_cntrl.forwardFromDir = ruby_system.network.slave
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
@ -153,8 +163,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl_nodes.append(dma_cntrl)
# Connect the directory controllers and the network
dma_cntrl.requestToDir = ruby_system.network.slave
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
@ -168,8 +181,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.requestToDir = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
all_cntrls = all_cntrls + [io_controller]

68
configs/ruby/MOESI_CMP_directory.py
View file

@ -103,10 +103,16 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L1 controllers and the network
l1_cntrl.requestFromL1Cache = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = ruby_system.network.slave
l1_cntrl.requestToL1Cache = ruby_system.network.master
l1_cntrl.responseToL1Cache = ruby_system.network.master
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.triggerQueue = MessageBuffer(ordered = True)
l2_index_start = block_size_bits + l2_bits
@ -128,13 +134,20 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l2_cntrl_nodes.append(l2_cntrl)
# Connect the L2 controllers and the network
l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = ruby_system.network.slave
l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
l2_cntrl.responseToL2Cache = ruby_system.network.master
l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.triggerQueue = MessageBuffer(ordered = True)
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
@ -163,10 +176,15 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.forwardFromDir = ruby_system.network.slave
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
@ -186,9 +204,14 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.reqToDir = ruby_system.network.slave
dma_cntrl.respToDir = ruby_system.network.slave
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer()
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.reqToDir = MessageBuffer()
dma_cntrl.reqToDir.master = ruby_system.network.slave
dma_cntrl.respToDir = MessageBuffer()
dma_cntrl.respToDir.master = ruby_system.network.slave
dma_cntrl.triggerQueue = MessageBuffer(ordered = True)
all_cntrls = l1_cntrl_nodes + \
@ -206,9 +229,14 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.reqToDir = ruby_system.network.slave
io_controller.respToDir = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer()
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.reqToDir = MessageBuffer()
io_controller.reqToDir.master = ruby_system.network.slave
io_controller.respToDir = MessageBuffer()
io_controller.respToDir.master = ruby_system.network.slave
io_controller.triggerQueue = MessageBuffer(ordered = True)
all_cntrls = all_cntrls + [io_controller]

79
configs/ruby/MOESI_CMP_token.py
View file

@ -123,13 +123,20 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L1 controllers and the network
l1_cntrl.requestFromL1Cache = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = ruby_system.network.slave
l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
l1_cntrl.requestFromL1Cache = MessageBuffer()
l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
l1_cntrl.responseFromL1Cache = MessageBuffer()
l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
l1_cntrl.requestToL1Cache = ruby_system.network.master
l1_cntrl.responseToL1Cache = ruby_system.network.master
l1_cntrl.persistentToL1Cache = ruby_system.network.master
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestToL1Cache = MessageBuffer()
l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
l1_cntrl.responseToL1Cache = MessageBuffer()
l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
l2_index_start = block_size_bits + l2_bits
@ -152,14 +159,21 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l2_cntrl_nodes.append(l2_cntrl)
# Connect the L2 controllers and the network
l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = ruby_system.network.slave
l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
l2_cntrl.responseFromL2Cache = MessageBuffer()
l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
l2_cntrl.responseToL2Cache = ruby_system.network.master
l2_cntrl.persistentToL2Cache = ruby_system.network.master
l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.L1RequestToL2Cache = MessageBuffer()
l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
l2_cntrl.responseToL2Cache = MessageBuffer()
l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
@ -188,15 +202,24 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.persistentToDir = ruby_system.network.master
dir_cntrl.dmaRequestToDir = ruby_system.network.master
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
dir_cntrl.persistentToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.requestFromDir = ruby_system.network.slave
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.persistentFromDir = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
dir_cntrl.requestFromDir = MessageBuffer()
dir_cntrl.requestFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
dir_cntrl.persistentFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
@ -216,8 +239,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.reqToDirectory = ruby_system.network.slave
dma_cntrl.mandatoryQueue = MessageBuffer()
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.reqToDirectory = MessageBuffer()
dma_cntrl.reqToDirectory.master = ruby_system.network.slave
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
@ -234,8 +260,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.reqToDirectory = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.reqToDirectory = MessageBuffer()
io_controller.reqToDirectory.master = ruby_system.network.slave
all_cntrls = all_cntrls + [io_controller]

56
configs/ruby/MOESI_hammer.py
View file

@ -118,13 +118,21 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
# Connect the L1 controller and the network
# Connect the buffers from the controller to network
l1_cntrl.requestFromCache = ruby_system.network.slave
l1_cntrl.responseFromCache = ruby_system.network.slave
l1_cntrl.unblockFromCache = ruby_system.network.slave
l1_cntrl.requestFromCache = MessageBuffer()
l1_cntrl.requestFromCache.master = ruby_system.network.slave
l1_cntrl.responseFromCache = MessageBuffer()
l1_cntrl.responseFromCache.master = ruby_system.network.slave
l1_cntrl.unblockFromCache = MessageBuffer()
l1_cntrl.unblockFromCache.master = ruby_system.network.slave
l1_cntrl.triggerQueue = MessageBuffer()
# Connect the buffers from the network to the controller
l1_cntrl.forwardToCache = ruby_system.network.master
l1_cntrl.responseToCache = ruby_system.network.master
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.forwardToCache = MessageBuffer()
l1_cntrl.forwardToCache.slave = ruby_system.network.master
l1_cntrl.responseToCache = MessageBuffer()
l1_cntrl.responseToCache.slave = ruby_system.network.master
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
@ -184,14 +192,24 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controller to the network
dir_cntrl.forwardFromDir = ruby_system.network.slave
dir_cntrl.responseFromDir = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
dir_cntrl.forwardFromDir = MessageBuffer()
dir_cntrl.forwardFromDir.master = ruby_system.network.slave
dir_cntrl.responseFromDir = MessageBuffer()
dir_cntrl.responseFromDir.master = ruby_system.network.slave
dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
dir_cntrl.unblockToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.dmaRequestToDir = ruby_system.network.master
dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
dir_cntrl.unblockToDir = MessageBuffer()
dir_cntrl.unblockToDir.slave = ruby_system.network.master
dir_cntrl.responseToDir = MessageBuffer()
dir_cntrl.responseToDir.slave = ruby_system.network.master
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.requestToDir.slave = ruby_system.network.master
dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
dir_cntrl.responseFromMemory = MessageBuffer()
for i, dma_port in enumerate(dma_ports):
@ -214,8 +232,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dma_cntrl.recycle_latency = options.recycle_latency
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.requestToDir = ruby_system.network.slave
dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
dma_cntrl.responseFromDir.slave = ruby_system.network.master
dma_cntrl.requestToDir = MessageBuffer()
dma_cntrl.requestToDir.master = ruby_system.network.slave
dma_cntrl.mandatoryQueue = MessageBuffer()
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
@ -229,8 +250,11 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
ruby_system.io_controller = io_controller
# Connect the dma controller to the network
io_controller.responseFromDir = ruby_system.network.master
io_controller.requestToDir = ruby_system.network.slave
io_controller.responseFromDir = MessageBuffer(ordered = True)
io_controller.responseFromDir.slave = ruby_system.network.master
io_controller.requestToDir = MessageBuffer()
io_controller.requestToDir.master = ruby_system.network.slave
io_controller.mandatoryQueue = MessageBuffer()
all_cntrls = all_cntrls + [io_controller]

13
configs/ruby/Network_test.py
View file

@ -95,9 +95,10 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L1 controllers and the network
l1_cntrl.requestFromCache = ruby_system.network.slave
l1_cntrl.responseFromCache = ruby_system.network.slave
l1_cntrl.forwardFromCache = ruby_system.network.slave
l1_cntrl.mandatoryQueue = MessageBuffer()
l1_cntrl.requestFromCache = MessageBuffer()
l1_cntrl.responseFromCache = MessageBuffer()
l1_cntrl.forwardFromCache = MessageBuffer()
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
@ -118,9 +119,9 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
dir_cntrl_nodes.append(dir_cntrl)
# Connect the directory controllers and the network
dir_cntrl.requestToDir = ruby_system.network.master
dir_cntrl.forwardToDir = ruby_system.network.master
dir_cntrl.responseToDir = ruby_system.network.master
dir_cntrl.requestToDir = MessageBuffer()
dir_cntrl.forwardToDir = MessageBuffer()
dir_cntrl.responseToDir = MessageBuffer()
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes

6
src/mem/protocol/MESI_Three_Level-L0cache.sm
View file

@ -35,13 +35,13 @@ machine(L0Cache, "MESI Directory L0 Cache")
bool send_evictions;
// From this node's L0 cache to the network
MessageBuffer * bufferToL1, network="To", ordered="true";
MessageBuffer * bufferToL1, network="To";
// To this node's L0 cache FROM the network
MessageBuffer * bufferFromL1, network="From", ordered="true";
MessageBuffer * bufferFromL1, network="From";
{
// Message queue between this controller and the processor
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
// STATES
state_declaration(State, desc="Cache states", default="L0Cache_State_I") {

14
src/mem/protocol/MESI_Three_Level-L1cache.sm
View file

@ -35,25 +35,25 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// Message Buffers between the L1 and the L0 Cache
// From the L1 cache to the L0 cache
MessageBuffer * bufferToL0, network="To", ordered="true";
MessageBuffer * bufferToL0, network="To";
// From the L0 cache to the L1 cache
MessageBuffer * bufferFromL0, network="From", ordered="true";
MessageBuffer * bufferFromL0, network="From";
// Message queue from this L1 cache TO the network / L2
MessageBuffer * requestToL2, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * responseToL2, network="To", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * unblockToL2, network="To", virtual_network="2",
ordered="false", vnet_type="unblock";
vnet_type="unblock";
// To this L1 cache FROM the network / L2
MessageBuffer * requestFromL2, network="From", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * responseFromL2, network="From", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
{
// STATES

14
src/mem/protocol/MESI_Two_Level-L1cache.sm
View file

@ -43,27 +43,27 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer * requestFromL1Cache, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
// a local L1 -> this L2 bank
MessageBuffer * responseFromL1Cache, network="To", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * unblockFromL1Cache, network="To", virtual_network="2",
ordered="false", vnet_type="unblock";
vnet_type="unblock";
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer * requestToL1Cache, network="From", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
// a L2 bank -> this L1
MessageBuffer * responseToL1Cache, network="From", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
{
// Request Buffer for prefetches
MessageBuffer optionalQueue, ordered="false";
MessageBuffer optionalQueue;
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@ -151,7 +151,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

12
src/mem/protocol/MESI_Two_Level-L2cache.sm
View file

@ -35,23 +35,23 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
// Message Queues
// From local bank of L2 cache TO the network
MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0",
ordered="false", vnet_type="request"; // this L2 bank -> Memory
vnet_type="request"; // this L2 bank -> Memory
MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2",
ordered="false", vnet_type="request"; // this L2 bank -> a local L1
vnet_type="request"; // this L2 bank -> a local L1
MessageBuffer * responseFromL2Cache, network="To", virtual_network="1",
ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory
vnet_type="response"; // this L2 bank -> a local L1 || Memory
// FROM the network to this local bank of L2 cache
MessageBuffer * unblockToL2Cache, network="From", virtual_network="2",
ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
ordered="false", vnet_type="request"; // a local L1 -> this L2 bank
vnet_type="request"; // a local L1 -> this L2 bank
MessageBuffer * responseToL2Cache, network="From", virtual_network="1",
ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank
vnet_type="response"; // a local L1 || Memory -> this L2 bank
{
// STATES
state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {

7
src/mem/protocol/MESI_Two_Level-dir.sm
View file

@ -32,11 +32,11 @@ machine(Directory, "MESI Two Level directory protocol")
Cycles directory_latency := 6;
MessageBuffer * requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * responseToDir, network="From", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * responseFromDir, network="To", virtual_network="1",
ordered="false", vnet_type="response";
vnet_type="response";
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
@ -182,6 +182,7 @@ machine(Directory, "MESI Two Level directory protocol")
(type == CoherenceRequestType:GETX);
}
MessageBuffer responseFromMemory;
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);

6
src/mem/protocol/MESI_Two_Level-dma.sm
View file

@ -32,9 +32,9 @@ machine(DMA, "DMA Controller")
Cycles request_latency := 6;
MessageBuffer * responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@ -49,7 +49,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
State cur_state;
State getState(Address addr) {

10
src/mem/protocol/MI_example-cache.sm
View file

@ -36,14 +36,14 @@ machine(L1Cache, "MI Example L1 Cache")
// NETWORK BUFFERS
MessageBuffer * requestFromCache, network="To", virtual_network="2",
ordered="true", vnet_type="request";
vnet_type="request";
MessageBuffer * responseFromCache, network="To", virtual_network="4",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * forwardToCache, network="From", virtual_network="3",
ordered="true", vnet_type="forward";
vnet_type="forward";
MessageBuffer * responseToCache, network="From", virtual_network="4",
ordered="true", vnet_type="response";
vnet_type="response";
{
// STATES
state_declaration(State, desc="Cache states") {
@ -77,7 +77,7 @@ machine(L1Cache, "MI Example L1 Cache")
// STRUCTURE DEFINITIONS
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
// CacheEntry
structure(Entry, desc="...", interface="AbstractCacheEntry") {

12
src/mem/protocol/MI_example-dir.sm
View file

@ -33,16 +33,16 @@ machine(Directory, "Directory protocol")
Cycles to_memory_controller_latency := 1;
MessageBuffer * forwardFromDir, network="To", virtual_network="3",
ordered="false", vnet_type="forward";
vnet_type="forward";
MessageBuffer * responseFromDir, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * requestToDir, network="From", virtual_network="2",
ordered="true", vnet_type="request";
vnet_type="request";
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
ordered="true", vnet_type="request";
vnet_type="request";
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {
@ -195,6 +195,8 @@ machine(Directory, "Directory protocol")
return num_functional_writes;
}
MessageBuffer responseFromMemory;
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
out_port(responseNetwork_out, ResponseMsg, responseFromDir);

6
src/mem/protocol/MI_example-dma.sm
View file

@ -32,9 +32,9 @@ machine(DMA, "DMA Controller")
Cycles request_latency := 6;
MessageBuffer * responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@ -49,7 +49,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
State cur_state;
State getState(Address addr) {

12
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View file

@ -39,18 +39,18 @@ machine(L1Cache, "Directory protocol")
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer * requestFromL1Cache, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
// a local L1 -> this L2 bank
MessageBuffer * responseFromL1Cache, network="To", virtual_network="2",
ordered="false", vnet_type="response";
vnet_type="response";
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer * requestToL1Cache, network="From", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
// a L2 bank -> this L1
MessageBuffer * responseToL1Cache, network="From", virtual_network="2",
ordered="false", vnet_type="response";
vnet_type="response";
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@ -134,7 +134,7 @@ machine(L1Cache, "Directory protocol")
void set_tbe(TBE b);
void unset_tbe();
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
MessageBuffer mandatoryQueue, abstract_chip_ptr="true";
TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
TimerTable useTimerTable;
@ -254,7 +254,7 @@ machine(L1Cache, "Directory protocol")
}
}
MessageBuffer triggerQueue, ordered="true";
MessageBuffer triggerQueue;
// ** OUT_PORTS **

14
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
View file

@ -34,19 +34,19 @@ machine(L2Cache, "Token protocol")
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="0",
ordered="false", vnet_type="request"; // this L2 bank -> a local L1
vnet_type="request"; // this L2 bank -> a local L1
MessageBuffer * GlobalRequestFromL2Cache, network="To", virtual_network="1",
ordered="false", vnet_type="request"; // this L2 bank -> mod-directory
vnet_type="request"; // this L2 bank -> mod-directory
MessageBuffer * responseFromL2Cache, network="To", virtual_network="2",
ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || mod-directory
vnet_type="response"; // this L2 bank -> a local L1 || mod-directory
// FROM the network to this local bank of L2 cache
MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0",
ordered="false", vnet_type="request"; // a local L1 -> this L2 bank, Lets try this???
vnet_type="request"; // a local L1 -> this L2 bank, Lets try this???
MessageBuffer * GlobalRequestToL2Cache, network="From", virtual_network="1",
ordered="false", vnet_type="request"; // mod-directory -> this L2 bank
vnet_type="request"; // mod-directory -> this L2 bank
MessageBuffer * responseToL2Cache, network="From", virtual_network="2",
ordered="false", vnet_type="response"; // a local L1 || mod-directory -> this L2 bank
vnet_type="response"; // a local L1 || mod-directory -> this L2 bank
{
// STATES
@ -565,7 +565,7 @@ machine(L2Cache, "Token protocol")
return num_functional_writes;
}
MessageBuffer triggerQueue, ordered="true";
MessageBuffer triggerQueue;
out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache);
out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache);

9
src/mem/protocol/MOESI_CMP_directory-dir.sm
View file

@ -33,14 +33,14 @@ machine(Directory, "Directory protocol")
// Message Queues
MessageBuffer * requestToDir, network="From", virtual_network="1",
ordered="false", vnet_type="request"; // a mod-L2 bank -> this Dir
vnet_type="request"; // a mod-L2 bank -> this Dir
MessageBuffer * responseToDir, network="From", virtual_network="2",
ordered="false", vnet_type="response"; // a mod-L2 bank -> this Dir
vnet_type="response"; // a mod-L2 bank -> this Dir
MessageBuffer * forwardFromDir, network="To", virtual_network="1",
ordered="false", vnet_type="forward";
vnet_type="forward";
MessageBuffer * responseFromDir, network="To", virtual_network="2",
ordered="false", vnet_type="response"; // Dir -> mod-L2 bank
vnet_type="response"; // Dir -> mod-L2 bank
{
// STATES
@ -220,6 +220,7 @@ machine(Directory, "Directory protocol")
return false;
}
MessageBuffer responseFromMemory;
// ** OUT_PORTS **
out_port(forwardNetwork_out, RequestMsg, forwardFromDir);

10
src/mem/protocol/MOESI_CMP_directory-dma.sm
View file

@ -33,12 +33,12 @@ machine(DMA, "DMA Controller")
Cycles response_latency := 14;
MessageBuffer * responseFromDir, network="From", virtual_network="2",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * reqToDir, network="To", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * respToDir, network="To", virtual_network="2",
ordered="false", vnet_type="dmaresponse";
vnet_type="dmaresponse";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
@ -69,8 +69,8 @@ machine(DMA, "DMA Controller")
bool isPresent(Address);
}
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer triggerQueue, ordered="true";
MessageBuffer mandatoryQueue;
MessageBuffer triggerQueue;
TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
State cur_state;

14
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -54,24 +54,24 @@ machine(L1Cache, "Token protocol")
// a local L1 -> this L2 bank
MessageBuffer * responseFromL1Cache, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * persistentFromL1Cache, network="To", virtual_network="3",
ordered="true", vnet_type="persistent";
vnet_type="persistent";
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
MessageBuffer * requestFromL1Cache, network="To", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer * responseToL1Cache, network="From", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * persistentToL1Cache, network="From", virtual_network="3",
ordered="true", vnet_type="persistent";
vnet_type="persistent";
// a L2 bank -> this L1
MessageBuffer * requestToL1Cache, network="From", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
{
// STATES
@ -194,7 +194,7 @@ machine(L1Cache, "Token protocol")
TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
MessageBuffer mandatoryQueue, abstract_chip_ptr="true";
bool starving, default="false";
int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

14
src/mem/protocol/MOESI_CMP_token-L2cache.sm
View file

@ -38,28 +38,28 @@ machine(L2Cache, "Token protocol")
// this L2 bank -> a local L1 || mod-directory
MessageBuffer * responseFromL2Cache, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
// this L2 bank -> mod-directory
MessageBuffer * GlobalRequestFromL2Cache, network="To", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
// this L2 bank -> a local L1
MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
// FROM the network to this local bank of L2 cache
// a local L1 || mod-directory -> this L2 bank
MessageBuffer * responseToL2Cache, network="From", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * persistentToL2Cache, network="From", virtual_network="3",
ordered="true", vnet_type="persistent";
vnet_type="persistent";
// mod-directory -> this L2 bank
MessageBuffer * GlobalRequestToL2Cache, network="From", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
// a local L1 -> this L2 bank
MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
{
// STATES

18
src/mem/protocol/MOESI_CMP_token-dir.sm
View file

@ -37,29 +37,29 @@ machine(Directory, "Token protocol")
// Message Queues from dir to other controllers / network
MessageBuffer * dmaResponseFromDir, network="To", virtual_network="5",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * responseFromDir, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * persistentFromDir, network="To", virtual_network="3",
ordered="true", vnet_type="persistent";
vnet_type="persistent";
MessageBuffer * requestFromDir, network="To", virtual_network="1",
ordered="false", vnet_type="request";
vnet_type="request";
// Message Queues to dir from other controllers / network
MessageBuffer * responseToDir, network="From", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * persistentToDir, network="From", virtual_network="3",
ordered="true", vnet_type="persistent";
vnet_type="persistent";
MessageBuffer * requestToDir, network="From", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
ordered="true", vnet_type="request";
vnet_type="request";
{
// STATES
@ -266,6 +266,8 @@ machine(Directory, "Token protocol")
return num_functional_writes;
}
MessageBuffer responseFromMemory;
// ** OUT_PORTS **
out_port(responseNetwork_out, ResponseMsg, responseFromDir);
out_port(persistentNetwork_out, PersistentMsg, persistentFromDir);

6
src/mem/protocol/MOESI_CMP_token-dma.sm
View file

@ -33,9 +33,9 @@ machine(DMA, "DMA Controller")
// Messsage Queues
MessageBuffer * responseFromDir, network="From", virtual_network="5",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * reqToDirectory, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
@ -51,7 +51,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
State cur_state;
State getState(Address addr) {

14
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -46,16 +46,16 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
// NETWORK BUFFERS
MessageBuffer * requestFromCache, network="To", virtual_network="2",
ordered="false", vnet_type="request";
vnet_type="request";
MessageBuffer * responseFromCache, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * unblockFromCache, network="To", virtual_network="5",
ordered="false", vnet_type="unblock";
vnet_type="unblock";
MessageBuffer * forwardToCache, network="From", virtual_network="3",
ordered="false", vnet_type="forward";
vnet_type="forward";
MessageBuffer * responseToCache, network="From", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@ -143,7 +143,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
// STRUCTURE DEFINITIONS
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
// CacheEntry
structure(Entry, desc="...", interface="AbstractCacheEntry") {
@ -320,7 +320,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
return cache_entry.AtomicAccessed;
}
MessageBuffer triggerQueue, ordered="false";
MessageBuffer triggerQueue;
// ** OUT_PORTS **

17
src/mem/protocol/MOESI_hammer-dir.sm
View file

@ -42,28 +42,28 @@ machine(Directory, "AMD Hammer-like protocol")
bool full_bit_dir_enabled := "False";
MessageBuffer * forwardFromDir, network="To", virtual_network="3",
ordered="false", vnet_type="forward";
vnet_type="forward";
MessageBuffer * responseFromDir, network="To", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
// For a finite buffered network, note that the DMA response network only
// works at this relatively lower numbered (lower priority) virtual network
// because the trigger queue decouples cache responses from DMA responses.
MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * unblockToDir, network="From", virtual_network="5",
ordered="false", vnet_type="unblock";
vnet_type="unblock";
MessageBuffer * responseToDir, network="From", virtual_network="4",
ordered="false", vnet_type="response";
vnet_type="response";
MessageBuffer * requestToDir, network="From", virtual_network="2",
ordered="false", vnet_type="request", recycle_latency="1";
vnet_type="request";
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
ordered="true", vnet_type="request";
vnet_type="request";
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_E") {
@ -300,7 +300,8 @@ machine(Directory, "AMD Hammer-like protocol")
}
}
MessageBuffer triggerQueue, ordered="true";
MessageBuffer triggerQueue;
MessageBuffer responseFromMemory;
// ** OUT_PORTS **
out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests

6
src/mem/protocol/MOESI_hammer-dma.sm
View file

@ -32,9 +32,9 @@ machine(DMA, "DMA Controller")
Cycles request_latency := 6;
MessageBuffer * responseFromDir, network="From", virtual_network="1",
ordered="true", vnet_type="response";
vnet_type="response";
MessageBuffer * requestToDir, network="To", virtual_network="0",
ordered="false", vnet_type="request";
vnet_type="request";
{
state_declaration(State, desc="DMA states", default="DMA_State_READY") {
READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@ -49,7 +49,7 @@ machine(DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
State cur_state;
State getState(Address addr) {

8
src/mem/protocol/Network_test-cache.sm
View file

@ -37,11 +37,11 @@ machine(L1Cache, "Network_test L1 Cache")
// NETWORK BUFFERS
MessageBuffer * requestFromCache, network="To", virtual_network="0",
ordered="false", vnet_type = "request";
vnet_type = "request";
MessageBuffer * forwardFromCache, network="To", virtual_network="1",
ordered="false", vnet_type = "forward";
vnet_type = "forward";
MessageBuffer * responseFromCache, network="To", virtual_network="2",
ordered="false", vnet_type = "response";
vnet_type = "response";
{
// STATES
state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
@ -58,7 +58,7 @@ machine(L1Cache, "Network_test L1 Cache")
// STRUCTURE DEFINITIONS
MessageBuffer mandatoryQueue, ordered="false";
MessageBuffer mandatoryQueue;
DataBlock dummyData;

6
src/mem/protocol/Network_test-dir.sm
View file

@ -33,11 +33,11 @@
machine(Directory, "Network_test Directory")
: MessageBuffer * requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type = "request";
vnet_type = "request";
MessageBuffer * forwardToDir, network="From", virtual_network="1",
ordered="false", vnet_type = "forward";
vnet_type = "forward";
MessageBuffer * responseToDir, network="From", virtual_network="2",
ordered="false", vnet_type = "response";
vnet_type = "response";
{
// STATES
state_declaration(State, desc="Directory states", default="Directory_State_I") {