stats: updates due to changes to ruby
This commit is contained in:
Nilay Vaish
parent
0811f21f67
commit
a75e27b4a6
50 changed files with 17303 additions and 10779 deletions
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@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
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[system]
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type=LinuxX86System
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children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus pc physmem ruby smbios_table sys_port_proxy voltage_domain
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children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus mem_ctrls pc ruby smbios_table sys_port_proxy voltage_domain
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acpi_description_table_pointer=system.acpi_description_table_pointer
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boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
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cache_line_size=64
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@ -26,7 +26,7 @@ load_addr_mask=18446744073709551615
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load_offset=0
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mem_mode=timing
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mem_ranges=0:134217727
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memories=system.physmem
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memories=system.mem_ctrls
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num_work_ids=16
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readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
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smbios_table=system.smbios_table
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@ -705,9 +705,86 @@ header_cycles=1
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use_default_range=false
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width=8
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default=system.pc.pciconfig.pio
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master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.physmem.port
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master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
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slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
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[system.mem_ctrls]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaChCo
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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clk_domain=system.clk_domain
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conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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device_size=536870912
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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page_policy=open_adaptive
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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port=system.ruby.dir_cntrl0.memory
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[system.pc]
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type=Pc
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children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
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@ -982,7 +1059,7 @@ pio_latency=30000
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platform=system.pc
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system=system
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config=system.iobus.master[3]
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dma=system.ruby.dma_cntrl0.dma_sequencer.slave[0]
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dma=system.ruby.dma_cntrl0.dma_sequencer.slave
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pio=system.iobus.master[2]
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[system.pc.south_bridge.ide.disks0]
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@ -1216,93 +1293,17 @@ pio_latency=100000
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system=system
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pio=system.iobus.master[8]
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[system.physmem]
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type=DRAMCtrl
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IDD0=0.075000
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IDD02=0.000000
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IDD2N=0.050000
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IDD2N2=0.000000
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IDD2P0=0.000000
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IDD2P02=0.000000
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IDD2P1=0.000000
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IDD2P12=0.000000
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IDD3N=0.057000
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IDD3N2=0.000000
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IDD3P0=0.000000
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IDD3P02=0.000000
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IDD3P1=0.000000
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IDD3P12=0.000000
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IDD4R=0.187000
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IDD4R2=0.000000
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IDD4W=0.165000
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IDD4W2=0.000000
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IDD5=0.220000
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IDD52=0.000000
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IDD6=0.000000
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IDD62=0.000000
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VDD=1.500000
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VDD2=0.000000
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activation_limit=4
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addr_mapping=RoRaBaChCo
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bank_groups_per_rank=0
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banks_per_rank=8
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burst_length=8
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channels=1
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clk_domain=system.clk_domain
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conf_table_reported=true
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device_bus_width=8
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device_rowbuffer_size=1024
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devices_per_rank=8
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dll=true
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eventq_index=0
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in_addr_map=true
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max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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page_policy=open_adaptive
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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static_backend_latency=10000
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static_frontend_latency=10000
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tBURST=5000
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tCCD_L=0
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tCK=1250
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tCL=13750
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tCS=2500
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tRAS=35000
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tRCD=13750
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tREFI=7800000
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tRFC=260000
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tRP=13750
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tRRD=6000
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tRRD_L=0
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tRTP=7500
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tRTW=2500
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tWR=15000
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tWTR=7500
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tXAW=30000
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tXP=0
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tXPDLL=0
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tXS=0
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tXSDLL=0
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write_buffer_size=64
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write_high_thresh_perc=85
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write_low_thresh_perc=50
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port=system.iobus.master[19]
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[system.ruby]
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type=RubySystem
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children=clk_domain dir_cntrl0 dma_cntrl0 l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network
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children=clk_domain dir_cntrl0 dma_cntrl0 io_controller l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network
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all_instructions=false
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block_size_bytes=64
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clk_domain=system.ruby.clk_domain
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eventq_index=0
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hot_lines=false
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mem_size=134217728
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no_mem_vec=false
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memory_size_bits=48
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num_of_sequencers=2
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phys_mem=Null
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random_seed=1234
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randomization=false
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@ -1316,21 +1317,21 @@ voltage_domain=system.voltage_domain
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[system.ruby.dir_cntrl0]
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type=Directory_Controller
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children=directory memBuffer
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children=directory
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buffer_size=0
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clk_domain=system.ruby.clk_domain
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cluster_id=0
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directory=system.ruby.dir_cntrl0.directory
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directory_latency=6
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eventq_index=0
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memBuffer=system.ruby.dir_cntrl0.memBuffer
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number_of_TBEs=256
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peer=Null
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recycle_latency=10
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ruby_system=system.ruby
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system=system
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to_mem_ctrl_latency=1
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transitions_per_cycle=4
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version=0
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memory=system.mem_ctrls.port
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requestToDir=system.ruby.network.master[7]
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responseFromDir=system.ruby.network.slave[9]
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responseToDir=system.ruby.network.master[8]
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@ -1338,33 +1339,8 @@ responseToDir=system.ruby.network.master[8]
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[system.ruby.dir_cntrl0.directory]
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type=RubyDirectoryMemory
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eventq_index=0
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map_levels=4
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numa_high_bit=5
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size=134217728
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use_map=false
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version=0
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[system.ruby.dir_cntrl0.memBuffer]
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type=RubyMemoryControl
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bank_bit_0=8
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bank_busy_time=11
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bank_queue_size=12
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banks_per_rank=8
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basic_bus_busy_time=2
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clk_domain=system.ruby.memctrl_clk_domain
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dimm_bit_0=12
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dimms_per_channel=2
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eventq_index=0
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mem_ctl_latency=12
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mem_fixed_delay=0
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mem_random_arbitrate=0
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rank_bit_0=11
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rank_rank_delay=1
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ranks_per_dimm=2
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read_write_delay=2
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refresh_period=1560
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ruby_system=system.ruby
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tFaw=0
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version=0
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[system.ruby.dma_cntrl0]
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@ -1376,10 +1352,10 @@ cluster_id=0
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dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
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eventq_index=0
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number_of_TBEs=256
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peer=Null
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recycle_latency=10
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request_latency=6
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ruby_system=system.ruby
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system=system
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transitions_per_cycle=4
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version=0
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requestToDir=system.ruby.network.slave[10]
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@ -1387,17 +1363,42 @@ responseFromDir=system.ruby.network.master[9]
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[system.ruby.dma_cntrl0.dma_sequencer]
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type=DMASequencer
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access_phys_mem=true
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clk_domain=system.ruby.clk_domain
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eventq_index=0
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ruby_system=system.ruby
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support_data_reqs=true
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support_inst_reqs=true
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system=system
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using_ruby_tester=false
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version=0
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slave=system.pc.south_bridge.ide.dma
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[system.ruby.io_controller]
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type=DMA_Controller
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children=dma_sequencer
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buffer_size=0
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clk_domain=system.ruby.clk_domain
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cluster_id=0
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dma_sequencer=system.ruby.io_controller.dma_sequencer
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eventq_index=0
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number_of_TBEs=256
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recycle_latency=10
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request_latency=6
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ruby_system=system.ruby
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system=system
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transitions_per_cycle=32
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version=1
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requestToDir=system.ruby.network.slave[11]
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responseFromDir=system.ruby.network.master[10]
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[system.ruby.io_controller.dma_sequencer]
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type=DMASequencer
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clk_domain=system.ruby.clk_domain
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eventq_index=0
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ruby_system=system.ruby
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system=system
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using_ruby_tester=false
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version=1
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slave=system.iobus.master[19]
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[system.ruby.l1_cntrl0]
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type=L1Cache_Controller
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children=L1Dcache L1Icache prefetcher sequencer
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@ -1412,12 +1413,12 @@ l1_request_latency=2
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l1_response_latency=2
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l2_select_num_bits=0
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number_of_TBEs=256
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peer=Null
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prefetcher=system.ruby.l1_cntrl0.prefetcher
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.ruby.l1_cntrl0.sequencer
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system=system
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to_l2_latency=1
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transitions_per_cycle=4
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version=0
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@ -1465,12 +1466,13 @@ nonunit_filter=8
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num_startup_pfs=1
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num_streams=4
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pf_per_stream=1
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sys=system
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train_misses=4
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unit_filter=8
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[system.ruby.l1_cntrl0.sequencer]
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type=RubySequencer
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access_phys_mem=true
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access_backing_store=false
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clk_domain=system.cpu_clk_domain
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dcache=system.ruby.l1_cntrl0.L1Dcache
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deadlock_threshold=500000
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@ -1504,12 +1506,12 @@ l1_request_latency=2
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l1_response_latency=2
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l2_select_num_bits=0
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number_of_TBEs=256
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peer=Null
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prefetcher=system.ruby.l1_cntrl1.prefetcher
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recycle_latency=10
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ruby_system=system.ruby
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send_evictions=false
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sequencer=system.ruby.l1_cntrl1.sequencer
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system=system
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to_l2_latency=1
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transitions_per_cycle=4
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version=1
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@ -1557,12 +1559,13 @@ nonunit_filter=8
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num_startup_pfs=1
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num_streams=4
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pf_per_stream=1
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sys=system
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train_misses=4
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unit_filter=8
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[system.ruby.l1_cntrl1.sequencer]
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type=RubySequencer
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access_phys_mem=true
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access_backing_store=false
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clk_domain=system.cpu_clk_domain
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dcache=system.ruby.l1_cntrl1.L1Dcache
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deadlock_threshold=500000
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@ -1593,9 +1596,9 @@ eventq_index=0
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l2_request_latency=2
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l2_response_latency=2
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number_of_TBEs=256
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peer=Null
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recycle_latency=10
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ruby_system=system.ruby
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system=system
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to_l1_latency=1
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transitions_per_cycle=4
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version=0
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@ -1629,22 +1632,22 @@ eventq_index=0
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[system.ruby.network]
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type=SimpleNetwork
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children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5
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children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 routers4 routers5 routers6
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adaptive_routing=false
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buffer_size=0
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clk_domain=system.ruby.clk_domain
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control_msg_size=8
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endpoint_bandwidth=1000
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eventq_index=0
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ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4
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int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4
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ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5
|
||||
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
|
||||
netifs=
|
||||
number_of_virtual_networks=10
|
||||
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5
|
||||
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5 system.ruby.network.routers6
|
||||
ruby_system=system.ruby
|
||||
topology=Crossbar
|
||||
master=system.ruby.l1_cntrl0.requestToL1Cache system.ruby.l1_cntrl0.responseToL1Cache system.ruby.l1_cntrl1.requestToL1Cache system.ruby.l1_cntrl1.responseToL1Cache system.ruby.l2_cntrl0.unblockToL2Cache system.ruby.l2_cntrl0.L1RequestToL2Cache system.ruby.l2_cntrl0.responseToL2Cache system.ruby.dir_cntrl0.requestToDir system.ruby.dir_cntrl0.responseToDir system.ruby.dma_cntrl0.responseFromDir
|
||||
slave=system.ruby.l1_cntrl0.requestFromL1Cache system.ruby.l1_cntrl0.responseFromL1Cache system.ruby.l1_cntrl0.unblockFromL1Cache system.ruby.l1_cntrl1.requestFromL1Cache system.ruby.l1_cntrl1.responseFromL1Cache system.ruby.l1_cntrl1.unblockFromL1Cache system.ruby.l2_cntrl0.DirRequestFromL2Cache system.ruby.l2_cntrl0.L1RequestFromL2Cache system.ruby.l2_cntrl0.responseFromL2Cache system.ruby.dir_cntrl0.responseFromDir system.ruby.dma_cntrl0.requestToDir
|
||||
master=system.ruby.l1_cntrl0.requestToL1Cache system.ruby.l1_cntrl0.responseToL1Cache system.ruby.l1_cntrl1.requestToL1Cache system.ruby.l1_cntrl1.responseToL1Cache system.ruby.l2_cntrl0.unblockToL2Cache system.ruby.l2_cntrl0.L1RequestToL2Cache system.ruby.l2_cntrl0.responseToL2Cache system.ruby.dir_cntrl0.requestToDir system.ruby.dir_cntrl0.responseToDir system.ruby.dma_cntrl0.responseFromDir system.ruby.io_controller.responseFromDir
|
||||
slave=system.ruby.l1_cntrl0.requestFromL1Cache system.ruby.l1_cntrl0.responseFromL1Cache system.ruby.l1_cntrl0.unblockFromL1Cache system.ruby.l1_cntrl1.requestFromL1Cache system.ruby.l1_cntrl1.responseFromL1Cache system.ruby.l1_cntrl1.unblockFromL1Cache system.ruby.l2_cntrl0.DirRequestFromL2Cache system.ruby.l2_cntrl0.L1RequestFromL2Cache system.ruby.l2_cntrl0.responseFromL2Cache system.ruby.dir_cntrl0.responseFromDir system.ruby.dma_cntrl0.requestToDir system.ruby.io_controller.requestToDir
|
||||
|
||||
[system.ruby.network.ext_links0]
|
||||
type=SimpleExtLink
|
||||
|
|
@ -1696,14 +1699,24 @@ latency=1
|
|||
link_id=4
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.ext_links5]
|
||||
type=SimpleExtLink
|
||||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
ext_node=system.ruby.io_controller
|
||||
int_node=system.ruby.network.routers5
|
||||
latency=1
|
||||
link_id=5
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links0]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=5
|
||||
link_id=6
|
||||
node_a=system.ruby.network.routers0
|
||||
node_b=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links1]
|
||||
|
|
@ -1711,9 +1724,9 @@ type=SimpleIntLink
|
|||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=6
|
||||
link_id=7
|
||||
node_a=system.ruby.network.routers1
|
||||
node_b=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links2]
|
||||
|
|
@ -1721,9 +1734,9 @@ type=SimpleIntLink
|
|||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=7
|
||||
link_id=8
|
||||
node_a=system.ruby.network.routers2
|
||||
node_b=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links3]
|
||||
|
|
@ -1731,9 +1744,9 @@ type=SimpleIntLink
|
|||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=8
|
||||
link_id=9
|
||||
node_a=system.ruby.network.routers3
|
||||
node_b=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links4]
|
||||
|
|
@ -1741,9 +1754,19 @@ type=SimpleIntLink
|
|||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=9
|
||||
link_id=10
|
||||
node_a=system.ruby.network.routers4
|
||||
node_b=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.int_links5]
|
||||
type=SimpleIntLink
|
||||
bandwidth_factor=16
|
||||
eventq_index=0
|
||||
latency=1
|
||||
link_id=11
|
||||
node_a=system.ruby.network.routers5
|
||||
node_b=system.ruby.network.routers6
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.routers0]
|
||||
|
|
@ -1788,6 +1811,13 @@ eventq_index=0
|
|||
router_id=5
|
||||
virt_nets=10
|
||||
|
||||
[system.ruby.network.routers6]
|
||||
type=Switch
|
||||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
router_id=6
|
||||
virt_nets=10
|
||||
|
||||
[system.smbios_table]
|
||||
type=X86SMBiosSMBiosTable
|
||||
children=structures
|
||||
|
|
@ -1813,7 +1843,7 @@ version=
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -30,7 +30,7 @@ Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
|||
Initializing CPU#0
|
||||
PID hash table entries: 512 (order: 9, 4096 bytes)
|
||||
Marking TSC unstable due to TSCs unsynchronized
|
||||
time.c: Detected 2000.000 MHz processor.
|
||||
time.c: Detected 2000.001 MHz processor.
|
||||
Console: colour dummy device 80x25
|
||||
console handover: boot [earlyser0] -> real [ttyS0]
|
||||
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
|
||||
|
|
@ -43,7 +43,7 @@ CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
|
|||
CPU: L2 Cache: 1024K (64 bytes/line)
|
||||
Freeing SMP alternatives: 34k freed
|
||||
Using local APIC timer interrupts.
|
||||
result 7812510
|
||||
result 7812509
|
||||
Detected 7.812 MHz APIC timer.
|
||||
Booting processor 1/2 APIC 0x1
|
||||
Initializing CPU#1
|
||||
|
|
@ -131,8 +131,8 @@ TCP cubic registered
|
|||
NET: Registered protocol family 1
|
||||
NET: Registered protocol family 10
|
||||
IPv6 over IPv4 tunneling driver
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
NET: Registered protocol family 17
|
||||
input: PS/2 Generic Mouse as /class/input/input1
|
||||
EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended
|
||||
VFS: Mounted root (ext2 filesystem).
|
||||
Freeing unused kernel memory: 248k freed
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,21 +237,21 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[6]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -194,33 +259,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -237,12 +277,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl0.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
|
|
@ -290,12 +330,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -322,9 +363,9 @@ eventq_index=0
|
|||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
|
|
@ -465,7 +506,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,25 +1,272 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000139 # Number of seconds simulated
|
||||
sim_ticks 138616 # Number of ticks simulated
|
||||
final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 138637 # Number of ticks simulated
|
||||
final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 36011 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 36008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 781041 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 161164 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_inst_rate 12523 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12523 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 271684 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436940 # Number of bytes of host memory used
|
||||
host_seconds 0.51 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93440 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 93440 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 673990349 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 673990349 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 127873511 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 127873511 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 801863860 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 801863860 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1460 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 277 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 74880 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 18560 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 290 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 155 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 103 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 396 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 19 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 138534 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1460 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 1170 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 224 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 353.142857 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 223.489977 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 324.415911 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 59 26.34% 26.34% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 55 24.55% 50.89% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 31 13.84% 64.73% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 15 6.70% 71.43% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 13 5.80% 77.23% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 14 6.25% 83.48% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7 3.12% 86.61% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 9 4.02% 90.62% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 21 9.38% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 224 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 178 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 127.889331 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 115.157284 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::192-207 2 33.33% 66.67% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::336-351 1 16.67% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 7999 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 30229 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5850 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.84 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.84 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 540.12 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 46.16 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 673.99 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 127.87 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.58 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.22 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.36 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 23.33 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 948 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 81.03 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 79.75 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 211 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 4420 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 128005 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 559440 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 1103760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 310800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 613200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 5828160 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 8112000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 362880 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 673920 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 8645520 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 8645520 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 75333024 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 89081424 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 13491600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 1431600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 104531424 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 109661424 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 788.190677 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 826.872042 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 9645 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.120270 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 0.973545 # delay histogram for all message
|
||||
system.ruby.delayHist | 9500 98.50% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.162779 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.010338 # delay histogram for all message
|
||||
system.ruby.delayHist | 9295 96.37% 96.37% | 0 0.00% 96.37% | 205 2.13% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 9645 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -28,13 +275,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 8449
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 15.408144
|
||||
system.ruby.latency_hist::gmean 5.259469
|
||||
system.ruby.latency_hist::stdev 27.065221
|
||||
system.ruby.latency_hist | 6958 82.36% 82.36% | 30 0.36% 82.72% | 0 0.00% 82.72% | 0 0.00% 82.72% | 1354 16.03% 98.75% | 93 1.10% 99.85% | 12 0.14% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 15.410630
|
||||
system.ruby.latency_hist::gmean 5.220511
|
||||
system.ruby.latency_hist::stdev 29.550250
|
||||
system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -43,13 +290,13 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6958
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1490
|
||||
system.ruby.miss_latency_hist::mean 73.351678
|
||||
system.ruby.miss_latency_hist::gmean 72.366127
|
||||
system.ruby.miss_latency_hist::stdev 8.741329
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 30 2.01% 2.01% | 0 0.00% 2.01% | 0 0.00% 2.01% | 1354 90.87% 92.89% | 93 6.24% 99.13% | 12 0.81% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 73.365772
|
||||
system.ruby.miss_latency_hist::gmean 69.379008
|
||||
system.ruby.miss_latency_hist::stdev 29.545012
|
||||
system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1490
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
|
||||
|
|
@ -57,6 +304,7 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
|
|
@ -66,7 +314,7 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.network.routers0.percent_links_utilized 3.776801
|
||||
system.ruby.network.routers0.percent_links_utilized 3.776229
|
||||
system.ruby.network.routers0.msg_count.Control::0 1490
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 1490
|
||||
|
|
@ -86,7 +334,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 7.333389
|
||||
system.ruby.network.routers1.percent_links_utilized 7.332278
|
||||
system.ruby.network.routers1.msg_count.Control::0 2950
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 3227
|
||||
|
|
@ -103,28 +351,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 343 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 343 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.197467 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 149 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 3.556588
|
||||
system.ruby.network.routers2.percent_links_utilized 3.556049
|
||||
system.ruby.network.routers2.msg_count.Control::0 1460
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 1737
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 2627
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 11680
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
|
||||
system.ruby.network.routers3.percent_links_utilized 4.888926
|
||||
system.ruby.network.routers3.percent_links_utilized 4.888185
|
||||
system.ruby.network.routers3.msg_count.Control::0 2950
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 3227
|
||||
|
|
@ -153,7 +387,7 @@ system.ruby.network.msg_byte.Response_Data 697032
|
|||
system.ruby.network.msg_byte.Response_Control 114288
|
||||
system.ruby.network.msg_byte.Writeback_Data 61776
|
||||
system.ruby.network.msg_byte.Writeback_Control 6984
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -187,7 +421,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 138616 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 138637 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -206,7 +440,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 138616 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 138637 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -245,14 +479,14 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.369871
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.369057
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.183731
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.183400
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
|
||||
|
|
@ -265,7 +499,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.447192
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.446064
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
|
||||
|
|
@ -280,7 +514,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.219585
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.218491
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
|
||||
|
|
@ -289,26 +523,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.849714
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.849434
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.263462
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.262664
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.369871
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.369057
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.447192
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.446064
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
|
||||
|
|
@ -323,7 +557,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 639
|
|||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.849714
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.849434
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
|
||||
|
|
@ -340,20 +574,22 @@ system.ruby.delayVCHist.vnet_0::total 2725 # de
|
|||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 5879 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.069740 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.366932 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 5674 96.51% 96.51% | 0 0.00% 96.51% | 205 3.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 37.688926
|
||||
system.ruby.LD.latency_hist::gmean 14.394335
|
||||
system.ruby.LD.latency_hist::stdev 35.806227
|
||||
system.ruby.LD.latency_hist | 600 50.72% 50.72% | 13 1.10% 51.82% | 0 0.00% 51.82% | 0 0.00% 51.82% | 529 44.72% 96.53% | 34 2.87% 99.41% | 6 0.51% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 35.343195
|
||||
system.ruby.LD.latency_hist::gmean 13.647233
|
||||
system.ruby.LD.latency_hist::stdev 36.940945
|
||||
system.ruby.LD.latency_hist | 797 67.37% 67.37% | 383 32.38% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -362,21 +598,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 600
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 583
|
||||
system.ruby.LD.miss_latency_hist::mean 73.389365
|
||||
system.ruby.LD.miss_latency_hist::gmean 72.297225
|
||||
system.ruby.LD.miss_latency_hist::stdev 9.304565
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 13 2.23% 2.23% | 0 0.00% 2.23% | 0 0.00% 2.23% | 529 90.74% 92.97% | 34 5.83% 98.80% | 6 1.03% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 68.629503
|
||||
system.ruby.LD.miss_latency_hist::gmean 64.886248
|
||||
system.ruby.LD.miss_latency_hist::stdev 24.148594
|
||||
system.ruby.LD.miss_latency_hist | 197 33.79% 33.79% | 383 65.69% 99.49% | 1 0.17% 99.66% | 0 0.00% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 583
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 20.523699
|
||||
system.ruby.ST.latency_hist::gmean 6.599297
|
||||
system.ruby.ST.latency_hist::stdev 31.233065
|
||||
system.ruby.ST.latency_hist | 649 75.03% 75.03% | 12 1.39% 76.42% | 0 0.00% 76.42% | 0 0.00% 76.42% | 161 18.61% 95.03% | 39 4.51% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 17.899422
|
||||
system.ruby.ST.latency_hist::gmean 6.261931
|
||||
system.ruby.ST.latency_hist::stdev 30.808929
|
||||
system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -385,21 +621,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 649
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 216
|
||||
system.ruby.ST.miss_latency_hist::mean 73.175926
|
||||
system.ruby.ST.miss_latency_hist::gmean 70.503717
|
||||
system.ruby.ST.miss_latency_hist::stdev 14.424352
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 12 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 161 74.54% 80.09% | 39 18.06% 98.15% | 4 1.85% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 62.666667
|
||||
system.ruby.ST.miss_latency_hist::gmean 57.141141
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.628615
|
||||
system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 216
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 10.598281
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.234466
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.908503
|
||||
system.ruby.IFETCH.latency_hist | 5709 89.20% 89.20% | 5 0.08% 89.28% | 0 0.00% 89.28% | 0 0.00% 89.28% | 664 10.38% 99.66% | 20 0.31% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 11.389844
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.264766
|
||||
system.ruby.IFETCH.latency_hist::stdev 26.115167
|
||||
system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -408,13 +644,13 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5709
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 691
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 73.374819
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 73.016992
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 5.198651
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 5 0.72% 0.72% | 0 0.00% 0.72% | 0 0.00% 0.72% | 664 96.09% 96.82% | 20 2.89% 99.71% | 2 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 80.706223
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 78.001693
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 30.507480
|
||||
system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 691
|
||||
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,21 +237,22 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardFromDir=system.ruby.network.slave[6]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[5]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -194,33 +260,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -234,12 +275,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -280,7 +321,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -305,11 +346,11 @@ clk_domain=system.ruby.clk_domain
|
|||
cluster_id=0
|
||||
eventq_index=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[2]
|
||||
|
|
@ -449,7 +490,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,265 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000118 # Number of seconds simulated
|
||||
sim_ticks 117611 # Number of ticks simulated
|
||||
final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000126 # Number of seconds simulated
|
||||
sim_ticks 126195 # Number of ticks simulated
|
||||
final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31716 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31714 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 583663 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 164416 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
host_inst_rate 17040 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17039 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 336486 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 440076 # Number of bytes of host memory used
|
||||
host_seconds 0.38 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75648 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 75648 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 599453227 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 599453227 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 98387416 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 98387416 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 697840643 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 697840643 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1182 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 11072 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 83 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 91 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 71 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 126127 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1182 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 211 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 327.582938 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 201.542711 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 321.278601 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 66 31.28% 31.28% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 57 27.01% 58.29% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 21 9.95% 68.25% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 10 4.74% 72.99% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 14 6.64% 79.62% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 12 5.69% 85.31% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 5 2.37% 87.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 23 10.90% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 211 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 141 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 106.525720 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 81.341871 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 7775 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 26946 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 7.71 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 26.71 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 511.72 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 41.59 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 599.45 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 98.39 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.32 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 91.66 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 232 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 4160 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 120458 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 551880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 1035720 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 306600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 575400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 4992000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 7450560 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 186624 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 8136960 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 8136960 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 64157832 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 84064968 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 18622800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 1160400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 96954696 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 103087560 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 776.656541 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 825.783908 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -21,129 +268,110 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 8449
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 12.921757
|
||||
system.ruby.latency_hist::gmean 4.838617
|
||||
system.ruby.latency_hist::stdev 24.260990
|
||||
system.ruby.latency_hist | 7086 83.88% 83.88% | 253 2.99% 86.87% | 0 0.00% 86.87% | 0 0.00% 86.87% | 1066 12.62% 99.49% | 38 0.45% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.937855
|
||||
system.ruby.latency_hist::gmean 4.957822
|
||||
system.ruby.latency_hist::stdev 28.418252
|
||||
system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 7086
|
||||
system.ruby.hit_latency_hist::samples 7027
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7086
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::samples 1362
|
||||
system.ruby.miss_latency_hist::mean 64.541116
|
||||
system.ruby.miss_latency_hist::gmean 58.182197
|
||||
system.ruby.miss_latency_hist::stdev 21.772726
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 253 18.58% 18.58% | 0 0.00% 18.58% | 0 0.00% 18.58% | 1066 78.27% 96.84% | 38 2.79% 99.63% | 4 0.29% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1362
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7027
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1421
|
||||
system.ruby.miss_latency_hist::mean 68.026742
|
||||
system.ruby.miss_latency_hist::gmean 59.451623
|
||||
system.ruby.miss_latency_hist::stdev 35.838026
|
||||
system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1421
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 6.350596
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 1354
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 1362
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 97488
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 10896
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 253 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1109 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 9.970581
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 2218
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1548
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 2186
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 2471
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 159696
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 111456
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 17488
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 19768
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1303 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1109 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 194 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 817 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 115 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 115 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.088258 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 40 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 55 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 3 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 17 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 74 5.68% 5.68% | 17 1.30% 6.98% | 45 3.45% 10.44% | 40 3.07% 13.51% | 54 4.14% 17.65% | 99 7.60% 25.25% | 29 2.23% 27.48% | 16 1.23% 28.70% | 19 1.46% 30.16% | 22 1.69% 31.85% | 31 2.38% 34.23% | 34 2.61% 36.84% | 52 3.99% 40.83% | 48 3.68% 44.51% | 38 2.92% 47.43% | 30 2.30% 49.73% | 39 2.99% 52.72% | 21 1.61% 54.34% | 21 1.61% 55.95% | 27 2.07% 58.02% | 28 2.15% 60.17% | 37 2.84% 63.01% | 55 4.22% 67.23% | 22 1.69% 68.92% | 31 2.38% 71.30% | 21 1.61% 72.91% | 32 2.46% 75.36% | 69 5.30% 80.66% | 84 6.45% 87.11% | 103 7.90% 95.01% | 13 1.00% 96.01% | 52 3.99% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1303 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 3.619985
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 2186
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 1109
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 17488
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 8872
|
||||
system.ruby.network.routers3.percent_links_utilized 6.647054
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 2218
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1548
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 2186
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 2471
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 159696
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 111456
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 17488
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 19768
|
||||
system.ruby.network.msg_count.Request_Control 7413
|
||||
system.ruby.network.msg_count.Response_Data 6654
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 759
|
||||
system.ruby.network.msg_count.Writeback_Data 4644
|
||||
system.ruby.network.msg_count.Writeback_Control 17379
|
||||
system.ruby.network.msg_count.Unblock_Control 7413
|
||||
system.ruby.network.msg_byte.Request_Control 59304
|
||||
system.ruby.network.msg_byte.Response_Data 479088
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 54648
|
||||
system.ruby.network.msg_byte.Writeback_Data 334368
|
||||
system.ruby.network.msg_byte.Writeback_Control 139032
|
||||
system.ruby.network.msg_byte.Unblock_Control 59304
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.974286
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 1308
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 1467
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 8.972820
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 2364
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1502
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 388
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 2649
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 170208
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192
|
||||
system.ruby.network.routers2.percent_links_utilized 2.998534
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 388
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 1182
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers3.percent_links_utilized 5.981880
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 2364
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1502
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 2708
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 388
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 2649
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 170208
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108144
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21192
|
||||
system.ruby.network.msg_count.Request_Control 7809
|
||||
system.ruby.network.msg_count.Response_Data 7092
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 717
|
||||
system.ruby.network.msg_count.Writeback_Data 4506
|
||||
system.ruby.network.msg_count.Writeback_Control 9288
|
||||
system.ruby.network.msg_count.Unblock_Control 7947
|
||||
system.ruby.network.msg_byte.Request_Control 62472
|
||||
system.ruby.network.msg_byte.Response_Data 510624
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 51624
|
||||
system.ruby.network.msg_byte.Writeback_Data 324432
|
||||
system.ruby.network.msg_byte.Writeback_Control 74304
|
||||
system.ruby.network.msg_byte.Unblock_Control 63576
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -177,7 +405,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 117611 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 126195 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -196,7 +424,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 117611 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 126195 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -235,106 +463,100 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.786874
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.603629
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.914319
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1354
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.344942
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1362
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 97488
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1467
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 10896
|
||||
system.ruby.network.routers1.throttle0.link_utilization 11.622212
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1354
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers1.throttle0.link_utilization 10.636713
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1362
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 97488
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1467
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 10896
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.318950
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.308927
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1109
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1182
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 8872
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.532076
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.705297
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1109
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1182
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 8872
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.707893
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.786874
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 253
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.291771
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.603629
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 18216
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers3.throttle1.link_utilization 11.622212
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1362
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1109
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1354
|
||||
system.ruby.network.routers3.throttle1.link_utilization 10.636713
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1354
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1362
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 10896
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 79848
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 97488
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1467
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11368
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85104
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 10896
|
||||
system.ruby.network.routers3.throttle2.link_utilization 2.532076
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1109
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.705297
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 1093
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 899
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1109
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 8872
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1182
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9456
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 8744
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 7192
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 8872
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 29.472527
|
||||
system.ruby.LD.latency_hist::gmean 10.960479
|
||||
system.ruby.LD.latency_hist::stdev 33.386382
|
||||
system.ruby.LD.latency_hist | 658 55.62% 55.62% | 113 9.55% 65.17% | 0 0.00% 65.17% | 0 0.00% 65.17% | 399 33.73% 98.90% | 10 0.85% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 29.355030
|
||||
system.ruby.LD.latency_hist::gmean 10.774857
|
||||
system.ruby.LD.latency_hist::stdev 36.604149
|
||||
system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -343,44 +565,44 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 658
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 525
|
||||
system.ruby.LD.miss_latency_hist::mean 62.651429
|
||||
system.ruby.LD.miss_latency_hist::gmean 55.602025
|
||||
system.ruby.LD.miss_latency_hist::stdev 23.052099
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 113 21.52% 21.52% | 0 0.00% 21.52% | 0 0.00% 21.52% | 399 76.00% 97.52% | 10 1.90% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 62.386667
|
||||
system.ruby.LD.miss_latency_hist::gmean 53.502649
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.511258
|
||||
system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 525
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 15.258960
|
||||
system.ruby.ST.latency_hist::gmean 5.580517
|
||||
system.ruby.ST.latency_hist::stdev 26.186033
|
||||
system.ruby.ST.latency_hist | 674 77.92% 77.92% | 61 7.05% 84.97% | 0 0.00% 84.97% | 0 0.00% 84.97% | 125 14.45% 99.42% | 5 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 19.187283
|
||||
system.ruby.ST.latency_hist::gmean 6.808148
|
||||
system.ruby.ST.latency_hist::stdev 31.171451
|
||||
system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 674
|
||||
system.ruby.ST.hit_latency_hist::samples 615
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 674
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 191
|
||||
system.ruby.ST.miss_latency_hist::mean 58.518325
|
||||
system.ruby.ST.miss_latency_hist::gmean 49.873811
|
||||
system.ruby.ST.miss_latency_hist::stdev 26.529992
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 61 31.94% 31.94% | 0 0.00% 31.94% | 0 0.00% 31.94% | 125 65.45% 97.38% | 5 2.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 191
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 615
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 250
|
||||
system.ruby.ST.miss_latency_hist::mean 59.008000
|
||||
system.ruby.ST.miss_latency_hist::gmean 51.116604
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.649742
|
||||
system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 2 0.80% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 250
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 9.546563
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.080453
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.389274
|
||||
system.ruby.IFETCH.latency_hist | 5754 89.91% 89.91% | 79 1.23% 91.14% | 0 0.00% 91.14% | 0 0.00% 91.14% | 542 8.47% 99.61% | 23 0.36% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 10.378594
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.114908
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.040800
|
||||
system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -389,90 +611,112 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5754
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 646
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 67.857585
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 63.180784
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 18.346066
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 79 12.23% 12.23% | 0 0.00% 12.23% | 0 0.00% 12.23% | 542 83.90% 96.13% | 23 3.56% 99.69% | 2 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 76.100619
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 68.669414
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 37.537546
|
||||
system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 646
|
||||
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 1379 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 1362 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 1354 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 1361 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 1362 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 1308 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 525 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 3467 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 51 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 1086 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 112 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 2287 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 27 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 17 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 1143 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 234 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 339 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Load 299 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Ifetch 5754 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 1059 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 39 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 45 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 229 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 313 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 7 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 257 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 12 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 283 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 218 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 1171 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 1354 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 1125 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1013 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 1171 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 191 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 1354 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data_Exclusive 979 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1058 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 296 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 1093 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 1362 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 1093 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 979 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 1354 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 192 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 61 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 1093 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 1058 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 296 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data_Exclusive 979 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 979 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 130 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 61 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 192 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 1093 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 130 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 979 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 1093 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 1109 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Clean_Writeback 899 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTS_only 1059 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 1182 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1013 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 1171 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 1193 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 984 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1013 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 906 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1013 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 984 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 984 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 198 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 984 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 1109 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 130 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 979 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 193 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 1093 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Exclusive_Unblock 979 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 979 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 130 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 130 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Clean_Writeback 899 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,7 +237,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
|
|
@ -182,16 +247,17 @@ distributed_persistent=true
|
|||
eventq_index=0
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[10]
|
||||
dmaResponseFromDir=system.ruby.network.slave[9]
|
||||
memory=system.mem_ctrls.port
|
||||
persistentFromDir=system.ruby.network.slave[8]
|
||||
persistentToDir=system.ruby.network.master[9]
|
||||
requestFromDir=system.ruby.network.slave[6]
|
||||
|
|
@ -202,33 +268,8 @@ responseToDir=system.ruby.network.master[8]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -248,13 +289,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -297,7 +338,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -326,9 +367,9 @@ filtering_enabled=true
|
|||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[3]
|
||||
|
|
@ -469,7 +510,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,26 +237,27 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
children=directory probeFilter
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
eventq_index=0
|
||||
from_memory_controller_latency=2
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
probeFilter=system.ruby.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[5]
|
||||
dmaResponseFromDir=system.ruby.network.slave[5]
|
||||
forwardFromDir=system.ruby.network.slave[3]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[4]
|
||||
responseFromDir=system.ruby.network.slave[4]
|
||||
responseToDir=system.ruby.network.master[3]
|
||||
|
|
@ -200,33 +266,8 @@ unblockToDir=system.ruby.network.master[2]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.probeFilter]
|
||||
|
|
@ -259,11 +300,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -319,7 +360,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -423,7 +464,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,266 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000093 # Number of seconds simulated
|
||||
sim_ticks 93341 # Number of ticks simulated
|
||||
final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000096 # Number of seconds simulated
|
||||
sim_ticks 96381 # Number of ticks simulated
|
||||
final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52665 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52659 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 769125 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 161200 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 32379 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32376 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 488288 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436896 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74176 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 74176 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 769612268 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 769612268 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 146086884 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 146086884 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 915699152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 915699152 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1159 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 64192 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 9984 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 5568 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 96 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 96301 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1159 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 1003 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 218.108055 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 333.620332 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 54 27.84% 27.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 51 26.29% 54.12% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 19 9.79% 63.92% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 16 8.25% 72.16% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 5 2.58% 88.14% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 23 11.86% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 194 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 140 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 105.715654 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 81.473922 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.400000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 17.358321 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.341641 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 80.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 20.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 6850 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 25907 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 5015 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.83 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.83 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 666.02 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 57.77 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 769.61 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 146.09 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 5.65 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.25 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 69.83 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 90575 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 476280 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 975240 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 264600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 541800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 5104320 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 7063680 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 238464 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 54836964 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 61829496 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 8112600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 1978800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 75135948 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 79155288 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 801.946249 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 844.845750 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -21,13 +269,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 8449
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 10.048887
|
||||
system.ruby.latency_hist::gmean 3.321275
|
||||
system.ruby.latency_hist::stdev 19.898198
|
||||
system.ruby.latency_hist | 7289 86.28% 86.28% | 0 0.00% 86.28% | 0 0.00% 86.28% | 1098 13.00% 99.28% | 9 0.11% 99.38% | 24 0.28% 99.67% | 0 0.00% 99.67% | 27 0.32% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 10.408736
|
||||
system.ruby.latency_hist::gmean 3.320045
|
||||
system.ruby.latency_hist::stdev 22.997500
|
||||
system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 2
|
||||
system.ruby.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -37,13 +285,13 @@ system.ruby.hit_latency_hist::gmean 2.107025
|
|||
system.ruby.hit_latency_hist::stdev 1.810102
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7289
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1159
|
||||
system.ruby.miss_latency_hist::mean 58.742019
|
||||
system.ruby.miss_latency_hist::gmean 58.108492
|
||||
system.ruby.miss_latency_hist::stdev 10.823033
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1098 94.74% 94.74% | 9 0.78% 95.51% | 24 2.07% 97.58% | 0 0.00% 97.58% | 27 2.33% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 61.364970
|
||||
system.ruby.miss_latency_hist::gmean 57.951867
|
||||
system.ruby.miss_latency_hist::stdev 28.728264
|
||||
system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1159
|
||||
system.ruby.Directory.incomplete_times 1158
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
|
|
@ -56,7 +304,8 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 4.804427
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 4.652888
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
|
||||
|
|
@ -71,24 +320,10 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1379 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1159 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 220 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 649 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 166 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 1 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 167 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.121102 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 114 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 33 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 8 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 11 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 75 5.44% 5.44% | 17 1.23% 6.67% | 45 3.26% 9.93% | 40 2.90% 12.84% | 54 3.92% 16.75% | 101 7.32% 24.08% | 33 2.39% 26.47% | 16 1.16% 27.63% | 20 1.45% 29.08% | 22 1.60% 30.67% | 32 2.32% 32.99% | 34 2.47% 35.46% | 53 3.84% 39.30% | 50 3.63% 42.93% | 39 2.83% 45.76% | 31 2.25% 48.01% | 39 2.83% 50.83% | 22 1.60% 52.43% | 21 1.52% 53.95% | 27 1.96% 55.91% | 28 2.03% 57.94% | 38 2.76% 60.70% | 81 5.87% 66.57% | 22 1.60% 68.17% | 31 2.25% 70.41% | 23 1.67% 72.08% | 32 2.32% 74.40% | 72 5.22% 79.62% | 89 6.45% 86.08% | 126 9.14% 95.21% | 14 1.02% 96.23% | 52 3.77% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1379 # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 4.804427
|
||||
system.ruby.network.routers1.percent_links_utilized 4.652888
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
|
||||
|
|
@ -103,7 +338,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers2.percent_links_utilized 4.804427
|
||||
system.ruby.network.routers2.percent_links_utilized 4.652888
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
|
||||
|
|
@ -128,7 +363,6 @@ system.ruby.network.msg_byte.Response_Data 250344
|
|||
system.ruby.network.msg_byte.Writeback_Data 47520
|
||||
system.ruby.network.msg_byte.Writeback_Control 77016
|
||||
system.ruby.network.msg_byte.Unblock_Control 27816
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -162,7 +396,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 93341 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 96381 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -181,7 +415,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 93341 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 96381 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -220,12 +454,12 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.199848
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.004295
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.409006
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.301481
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143
|
||||
|
|
@ -236,7 +470,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.409006
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.301481
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143
|
||||
|
|
@ -247,17 +481,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.199848
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.004295
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.199848
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.004295
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.409006
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.301481
|
||||
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143
|
||||
|
|
@ -268,13 +502,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
|
|||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 22.775993
|
||||
system.ruby.LD.latency_hist::gmean 7.779006
|
||||
system.ruby.LD.latency_hist::stdev 26.522309
|
||||
system.ruby.LD.latency_hist | 763 64.50% 64.50% | 0 0.00% 64.50% | 0 0.00% 64.50% | 403 34.07% 98.56% | 6 0.51% 99.07% | 7 0.59% 99.66% | 0 0.00% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 22.819949
|
||||
system.ruby.LD.latency_hist::gmean 7.633765
|
||||
system.ruby.LD.latency_hist::stdev 29.454181
|
||||
system.ruby.LD.latency_hist | 845 71.43% 71.43% | 248 20.96% 92.39% | 86 7.27% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 2
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -284,21 +518,21 @@ system.ruby.LD.hit_latency_hist::gmean 2.587610
|
|||
system.ruby.LD.hit_latency_hist::stdev 3.791932
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 763
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 420
|
||||
system.ruby.LD.miss_latency_hist::mean 57.769048
|
||||
system.ruby.LD.miss_latency_hist::gmean 57.456176
|
||||
system.ruby.LD.miss_latency_hist::stdev 7.426103
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 403 95.95% 95.95% | 6 1.43% 97.38% | 7 1.67% 99.05% | 0 0.00% 99.05% | 4 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 57.892857
|
||||
system.ruby.LD.miss_latency_hist::gmean 54.485563
|
||||
system.ruby.LD.miss_latency_hist::stdev 22.570398
|
||||
system.ruby.LD.miss_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 420
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 14.321387
|
||||
system.ruby.ST.latency_hist::gmean 4.046888
|
||||
system.ruby.ST.latency_hist::stdev 27.064708
|
||||
system.ruby.ST.latency_hist | 707 81.73% 81.73% | 0 0.00% 81.73% | 0 0.00% 81.73% | 129 14.91% 96.65% | 1 0.12% 96.76% | 4 0.46% 97.23% | 0 0.00% 97.23% | 23 2.66% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 11.716763
|
||||
system.ruby.ST.latency_hist::gmean 3.868197
|
||||
system.ruby.ST.latency_hist::stdev 20.732802
|
||||
system.ruby.ST.latency_hist | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 74 8.55% 95.38% | 36 4.16% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 2
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -311,18 +545,18 @@ system.ruby.ST.hit_latency_hist::total 707
|
|||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 158
|
||||
system.ruby.ST.miss_latency_hist::mean 67.158228
|
||||
system.ruby.ST.miss_latency_hist::gmean 64.120487
|
||||
system.ruby.ST.miss_latency_hist::stdev 23.863071
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 129 81.65% 81.65% | 1 0.63% 82.28% | 4 2.53% 84.81% | 0 0.00% 84.81% | 23 14.56% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 52.898734
|
||||
system.ruby.ST.miss_latency_hist::gmean 50.075344
|
||||
system.ruby.ST.miss_latency_hist::stdev 15.909453
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 158
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 7.118906
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.763022
|
||||
system.ruby.IFETCH.latency_hist::stdev 15.900341
|
||||
system.ruby.IFETCH.latency_hist | 5819 90.92% 90.92% | 0 0.00% 90.92% | 0 0.00% 90.92% | 566 8.84% 99.77% | 2 0.03% 99.80% | 13 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 7.937812
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.788276
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.096217
|
||||
system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 1 0.02% 99.86% | 4 0.06% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -332,13 +566,13 @@ system.ruby.IFETCH.hit_latency_hist::gmean 2.042257
|
|||
system.ruby.IFETCH.hit_latency_hist::stdev 1.156174
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5819
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 581
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 57.156627
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 57.036946
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 4.170245
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 566 97.42% 97.42% | 2 0.34% 97.76% | 13 2.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 66.177281
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 63.049831
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 34.055805
|
||||
system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 581
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -354,13 +588,13 @@ system.ruby.L2Cache.hit_mach_latency_hist::mean 13
|
|||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 13.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 203
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1159
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 58.742019
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 58.108492
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 10.823033
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1098 94.74% 94.74% | 9 0.78% 95.51% | 24 2.07% 97.58% | 0 0.00% 97.58% | 27 2.33% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 61.364970
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 57.951867
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 28.728264
|
||||
system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1159
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -377,10 +611,10 @@ system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
|
|||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 9
|
||||
|
|
@ -402,13 +636,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 13
|
|||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 13.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 105
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 420
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.769048
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 57.456176
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.426103
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 403 95.95% 95.95% | 6 1.43% 97.38% | 7 1.67% 99.05% | 0 0.00% 99.05% | 4 0.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.892857
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 54.485563
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.570398
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -427,10 +661,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33
|
|||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 67.158228
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 64.120487
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.863071
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 129 81.65% 81.65% | 1 0.63% 82.28% | 4 2.53% 84.81% | 0 0.00% 84.81% | 23 14.56% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.898734
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.075344
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.909453
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -446,13 +680,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 13
|
|||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 13.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 65
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.156627
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 57.036946
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 4.170245
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 566 97.42% 97.42% | 2 0.34% 97.76% | 13 2.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.049831
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.055805
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581
|
||||
system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00%
|
||||
|
|
@ -495,8 +729,8 @@ system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 186 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 1022 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 1020 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUT 1143 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
||||
|
|
@ -512,8 +746,6 @@ system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
|
|||
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETX 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,56 +237,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -235,11 +276,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -264,7 +305,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -368,7 +409,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,266 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000144 # Number of seconds simulated
|
||||
sim_ticks 143853 # Number of ticks simulated
|
||||
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000124 # Number of seconds simulated
|
||||
sim_ticks 123564 # Number of ticks simulated
|
||||
final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 53676 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 53669 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1208067 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 160752 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 34581 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 34578 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 668563 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436724 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1730 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1726 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 123476 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 10464 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 35.73 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
|
|
@ -26,13 +274,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 8449
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8448
|
||||
system.ruby.latency_hist::mean 16.028054
|
||||
system.ruby.latency_hist::gmean 5.654112
|
||||
system.ruby.latency_hist::stdev 25.911348
|
||||
system.ruby.latency_hist | 6718 79.52% 79.52% | 0 0.00% 79.52% | 0 0.00% 79.52% | 336 3.98% 83.50% | 1251 14.81% 98.31% | 136 1.61% 99.92% | 5 0.06% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.626420
|
||||
system.ruby.latency_hist::gmean 5.329740
|
||||
system.ruby.latency_hist::stdev 25.242996
|
||||
system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8448
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -41,20 +289,21 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6718
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1730
|
||||
system.ruby.miss_latency_hist::mean 66.619075
|
||||
system.ruby.miss_latency_hist::gmean 66.251950
|
||||
system.ruby.miss_latency_hist::stdev 7.725779
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 336 19.42% 19.42% | 1251 72.31% 91.73% | 136 7.86% 99.60% | 5 0.29% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 54.891329
|
||||
system.ruby.miss_latency_hist::gmean 49.648144
|
||||
system.ruby.miss_latency_hist::stdev 31.153546
|
||||
system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1730
|
||||
system.ruby.Directory.incomplete_times 1729
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 6.006131
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.992328
|
||||
system.ruby.network.routers0.msg_count.Control::2 1730
|
||||
system.ruby.network.routers0.msg_count.Data::2 1726
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1730
|
||||
|
|
@ -63,21 +312,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13840
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 3456 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1730 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1726 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 999 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 3037 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 11 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 3048 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.881944 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 1500 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1375 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 55 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 107 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 162 4.69% 4.69% | 36 1.04% 5.73% | 92 2.66% 8.39% | 110 3.18% 11.57% | 106 3.07% 14.64% | 362 10.47% 25.12% | 98 2.84% 27.95% | 36 1.04% 28.99% | 32 0.93% 29.92% | 34 0.98% 30.90% | 83 2.40% 33.30% | 92 2.66% 35.97% | 110 3.18% 39.15% | 104 3.01% 42.16% | 84 2.43% 44.59% | 86 2.49% 47.08% | 83 2.40% 49.48% | 53 1.53% 51.01% | 50 1.45% 52.46% | 58 1.68% 54.14% | 64 1.85% 55.99% | 124 3.59% 59.58% | 212 6.13% 65.71% | 72 2.08% 67.80% | 66 1.91% 69.70% | 50 1.45% 71.15% | 122 3.53% 74.68% | 190 5.50% 80.18% | 220 6.37% 86.55% | 325 9.40% 95.95% | 42 1.22% 97.16% | 98 2.84% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 3456 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 6.006131
|
||||
system.ruby.network.routers1.percent_links_utilized 6.992328
|
||||
system.ruby.network.routers1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1730
|
||||
|
|
@ -86,7 +321,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13840
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.percent_links_utilized 6.006131
|
||||
system.ruby.network.routers2.percent_links_utilized 6.992328
|
||||
system.ruby.network.routers2.msg_count.Control::2 1730
|
||||
system.ruby.network.routers2.msg_count.Data::2 1726
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1730
|
||||
|
|
@ -103,7 +338,6 @@ system.ruby.network.msg_byte.Control 41520
|
|||
system.ruby.network.msg_byte.Data 372816
|
||||
system.ruby.network.msg_byte.Response_Data 373680
|
||||
system.ruby.network.msg_byte.Writeback_Control 41424
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -137,7 +371,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 143853 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 123564 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -156,7 +390,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 143853 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 123564 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -195,32 +429,32 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.011692
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.998802
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.000570
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.985853
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.000570
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.985853
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.011692
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.998802
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.011692
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.998802
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.000570
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.985853
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
|
||||
|
|
@ -235,13 +469,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1183
|
||||
system.ruby.LD.latency_hist::mean 41.560440
|
||||
system.ruby.LD.latency_hist::gmean 19.958512
|
||||
system.ruby.LD.latency_hist::stdev 30.922662
|
||||
system.ruby.LD.latency_hist | 456 38.55% 38.55% | 0 0.00% 38.55% | 0 0.00% 38.55% | 118 9.97% 48.52% | 572 48.35% 96.87% | 36 3.04% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 33.711750
|
||||
system.ruby.LD.latency_hist::gmean 16.462445
|
||||
system.ruby.LD.latency_hist::stdev 33.973523
|
||||
system.ruby.LD.latency_hist | 1077 91.04% 91.04% | 86 7.27% 98.31% | 15 1.27% 99.58% | 2 0.17% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1183
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -250,21 +484,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 456
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 727
|
||||
system.ruby.LD.miss_latency_hist::mean 65.746905
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.515952
|
||||
system.ruby.LD.miss_latency_hist::stdev 6.090166
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 118 16.23% 16.23% | 572 78.68% 94.91% | 36 4.95% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 52.975241
|
||||
system.ruby.LD.miss_latency_hist::gmean 47.891138
|
||||
system.ruby.LD.miss_latency_hist::stdev 30.251097
|
||||
system.ruby.LD.miss_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 727
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 865
|
||||
system.ruby.ST.latency_hist::mean 23.805780
|
||||
system.ruby.ST.latency_hist::gmean 8.045280
|
||||
system.ruby.ST.latency_hist::stdev 31.148787
|
||||
system.ruby.ST.latency_hist | 592 68.44% 68.44% | 0 0.00% 68.44% | 0 0.00% 68.44% | 29 3.35% 71.79% | 202 23.35% 95.14% | 42 4.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 18.557225
|
||||
system.ruby.ST.latency_hist::gmean 7.162336
|
||||
system.ruby.ST.latency_hist::stdev 28.547301
|
||||
system.ruby.ST.latency_hist | 834 96.42% 96.42% | 21 2.43% 98.84% | 9 1.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 865
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -273,21 +507,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 592
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 273
|
||||
system.ruby.ST.miss_latency_hist::mean 68.923077
|
||||
system.ruby.ST.miss_latency_hist::gmean 68.323325
|
||||
system.ruby.ST.miss_latency_hist::stdev 9.836417
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 29 10.62% 10.62% | 202 73.99% 84.62% | 42 15.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 52.293040
|
||||
system.ruby.ST.miss_latency_hist::gmean 47.271858
|
||||
system.ruby.ST.miss_latency_hist::stdev 30.324989
|
||||
system.ruby.ST.miss_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 273
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6400
|
||||
system.ruby.IFETCH.latency_hist::mean 10.257344
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.269833
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.411875
|
||||
system.ruby.IFETCH.latency_hist | 5670 88.59% 88.59% | 0 0.00% 88.59% | 0 0.00% 88.59% | 189 2.95% 91.55% | 477 7.45% 99.00% | 58 0.91% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.247344
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.157427
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.515003
|
||||
system.ruby.IFETCH.latency_hist | 6284 98.19% 98.19% | 92 1.44% 99.63% | 19 0.30% 99.92% | 0 0.00% 99.92% | 3 0.05% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6400
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -296,21 +530,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5670
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 730
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 66.626027
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 66.226254
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 8.110427
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 189 25.89% 25.89% | 477 65.34% 91.23% | 58 7.95% 99.18% | 4 0.55% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 57.771233
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 52.414605
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 32.138819
|
||||
system.ruby.IFETCH.miss_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 730
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1730
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 66.619075
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 66.251950
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 7.725779
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 336 19.42% 19.42% | 1251 72.31% 91.73% | 136 7.86% 99.60% | 5 0.29% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 54.891329
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1730
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -333,34 +567,34 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.746905
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.515952
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 6.090166
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 118 16.23% 16.23% | 572 78.68% 94.91% | 36 4.95% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 68.923077
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 68.323325
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 9.836417
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 29 10.62% 10.62% | 202 73.99% 84.62% | 42 15.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.626027
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.226254
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 8.110427
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 189 25.89% 25.89% | 477 65.34% 91.23% | 58 7.95% 99.18% | 4 0.55% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730
|
||||
system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,21 +237,21 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[6]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -194,33 +259,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -237,12 +277,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl0.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
|
|
@ -290,12 +330,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -322,9 +363,9 @@ eventq_index=0
|
|||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
|
|
@ -465,7 +506,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,25 +1,267 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000053 # Number of seconds simulated
|
||||
sim_ticks 52548 # Number of ticks simulated
|
||||
final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000052 # Number of seconds simulated
|
||||
sim_ticks 52301 # Number of ticks simulated
|
||||
final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17447 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 355681 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 176684 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 11256 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 11255 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 228406 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435628 # Number of bytes of host memory used
|
||||
host_seconds 0.23 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 6592 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 669356226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 669356226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 126039655 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 126039655 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 795395882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 795395882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 547 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 103 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 103 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 28032 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 6976 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 35008 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 6592 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 57 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 84 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 64 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 52214 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 547 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 103 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 438 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 334.829268 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 222.665618 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 287.679168 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 22 26.83% 26.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 19 23.17% 50.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 5 6.10% 56.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 17 20.73% 76.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 5 6.10% 82.93% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 4 4.88% 87.80% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 3 3.66% 91.46% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 2 2.44% 93.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 5 6.10% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::256-271 1 100.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2713 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11035 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.19 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.19 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 535.97 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 19.58 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 669.36 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 126.04 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.34 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.19 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.15 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 22.51 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 350 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 14 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 79.91 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 80.33 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 45410 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 393120 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 218400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 1971840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 2907840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 31347036 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 31310100 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 688200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 720600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 37328916 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 38767308 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 794.638028 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 825.257749 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 3612 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.099668 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 0.887483 # delay histogram for all message
|
||||
system.ruby.delayHist | 3567 98.75% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 45 1.25% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.144518 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 0.930805 # delay histogram for all message
|
||||
system.ruby.delayHist | 3486 96.51% 96.51% | 0 0.00% 96.51% | 81 2.24% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 45 1.25% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 3612 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -28,13 +270,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 14.952641
|
||||
system.ruby.latency_hist::gmean 5.183037
|
||||
system.ruby.latency_hist::stdev 26.534204
|
||||
system.ruby.latency_hist | 2722 82.64% 82.64% | 25 0.76% 83.39% | 0 0.00% 83.39% | 0 0.00% 83.39% | 520 15.79% 99.18% | 24 0.73% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 14.877656
|
||||
system.ruby.latency_hist::gmean 5.143561
|
||||
system.ruby.latency_hist::stdev 28.438893
|
||||
system.ruby.latency_hist | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 2 0.06% 99.88% | 3 0.09% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -43,13 +285,13 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2722
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 572
|
||||
system.ruby.miss_latency_hist::mean 71.832168
|
||||
system.ruby.miss_latency_hist::gmean 69.921343
|
||||
system.ruby.miss_latency_hist::stdev 11.764017
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 25 4.37% 4.37% | 0 0.00% 4.37% | 0 0.00% 4.37% | 520 90.91% 95.28% | 24 4.20% 99.48% | 2 0.35% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 71.400350
|
||||
system.ruby.miss_latency_hist::gmean 66.909551
|
||||
system.ruby.miss_latency_hist::stdev 28.130025
|
||||
system.ruby.miss_latency_hist | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 2 0.35% 99.30% | 3 0.52% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 572
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
|
||||
|
|
@ -67,7 +309,7 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
|||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.network.routers0.percent_links_utilized 3.786062
|
||||
system.ruby.network.routers0.percent_links_utilized 3.803943
|
||||
system.ruby.network.routers0.msg_count.Control::0 572
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 572
|
||||
|
|
@ -87,7 +329,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
|
|||
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 7.293332
|
||||
system.ruby.network.routers1.percent_links_utilized 7.327776
|
||||
system.ruby.network.routers1.msg_count.Control::0 1119
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 1222
|
||||
|
|
@ -104,27 +346,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 120 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 120 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.184615 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 61 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 51 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 3.507270
|
||||
system.ruby.network.routers2.percent_links_utilized 3.523833
|
||||
system.ruby.network.routers2.msg_count.Control::0 547
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 650
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 975
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 4376
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
|
||||
system.ruby.network.routers3.percent_links_utilized 4.862221
|
||||
system.ruby.network.routers3.percent_links_utilized 4.885184
|
||||
system.ruby.network.routers3.msg_count.Control::0 1119
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 1222
|
||||
|
|
@ -153,6 +382,7 @@ system.ruby.network.msg_byte.Response_Data 263952
|
|||
system.ruby.network.msg_byte.Response_Control 41760
|
||||
system.ruby.network.msg_byte.Writeback_Data 23112
|
||||
system.ruby.network.msg_byte.Writeback_Control 1896
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -186,7 +416,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 52548 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 52301 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -205,7 +435,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 52548 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 52301 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -244,14 +474,14 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.426467
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.452095
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.145657
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.155791
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 572
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272
|
||||
|
|
@ -264,7 +494,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.342810
|
||||
system.ruby.network.routers1.throttle0.link_utilization 7.377488
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 572
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908
|
||||
|
|
@ -279,7 +509,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.243853
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.278064
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 547
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675
|
||||
|
|
@ -288,26 +518,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.817386
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.825969
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 547
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.197153
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.221697
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.426467
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.452095
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.342810
|
||||
system.ruby.network.routers3.throttle1.link_utilization 7.377488
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 572
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908
|
||||
|
|
@ -322,7 +552,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 217
|
|||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.817386
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.825969
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 547
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436
|
||||
|
|
@ -339,20 +569,22 @@ system.ruby.delayVCHist.vnet_0::total 968 # de
|
|||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 2213 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 2213 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.073204 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.375650 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 2132 96.34% 96.34% | 0 0.00% 96.34% | 81 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 2213 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 36.662651
|
||||
system.ruby.LD.latency_hist::gmean 14.004037
|
||||
system.ruby.LD.latency_hist::stdev 35.611863
|
||||
system.ruby.LD.latency_hist | 211 50.84% 50.84% | 12 2.89% 53.73% | 0 0.00% 53.73% | 0 0.00% 53.73% | 181 43.61% 97.35% | 9 2.17% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 33.351807
|
||||
system.ruby.LD.latency_hist::gmean 13.076698
|
||||
system.ruby.LD.latency_hist::stdev 35.943616
|
||||
system.ruby.LD.latency_hist | 223 53.73% 53.73% | 75 18.07% 71.81% | 105 25.30% 97.11% | 11 2.65% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -361,21 +593,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 211
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 204
|
||||
system.ruby.LD.miss_latency_hist::mean 71.480392
|
||||
system.ruby.LD.miss_latency_hist::gmean 68.920061
|
||||
system.ruby.LD.miss_latency_hist::stdev 13.795288
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 12 5.88% 5.88% | 0 0.00% 5.88% | 0 0.00% 5.88% | 181 88.73% 94.61% | 9 4.41% 99.02% | 1 0.49% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 64.745098
|
||||
system.ruby.LD.miss_latency_hist::gmean 59.953469
|
||||
system.ruby.LD.miss_latency_hist::stdev 26.208218
|
||||
system.ruby.LD.miss_latency_hist | 12 5.88% 5.88% | 75 36.76% 42.65% | 105 51.47% 94.12% | 11 5.39% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 204
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 18.945578
|
||||
system.ruby.ST.latency_hist::gmean 6.204355
|
||||
system.ruby.ST.latency_hist::stdev 29.867576
|
||||
system.ruby.ST.latency_hist | 226 76.87% 76.87% | 4 1.36% 78.23% | 0 0.00% 78.23% | 0 0.00% 78.23% | 59 20.07% 98.30% | 4 1.36% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 16.670068
|
||||
system.ruby.ST.latency_hist::gmean 5.908100
|
||||
system.ruby.ST.latency_hist::stdev 30.631855
|
||||
system.ruby.ST.latency_hist | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -384,21 +616,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 226
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 68
|
||||
system.ruby.ST.miss_latency_hist::mean 71.941176
|
||||
system.ruby.ST.miss_latency_hist::gmean 69.425776
|
||||
system.ruby.ST.miss_latency_hist::stdev 13.893929
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 4 5.88% 5.88% | 0 0.00% 5.88% | 0 0.00% 5.88% | 59 86.76% 92.65% | 4 5.88% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 62.102941
|
||||
system.ruby.ST.miss_latency_hist::gmean 56.188955
|
||||
system.ruby.ST.miss_latency_hist::stdev 37.122283
|
||||
system.ruby.ST.miss_latency_hist | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 68
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 11.013153
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.329120
|
||||
system.ruby.IFETCH.latency_hist::stdev 22.357768
|
||||
system.ruby.IFETCH.latency_hist | 2285 88.39% 88.39% | 9 0.35% 88.74% | 0 0.00% 88.74% | 0 0.00% 88.74% | 280 10.83% 99.57% | 11 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 11.707930
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.358751
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.535583
|
||||
system.ruby.IFETCH.latency_hist | 2294 88.74% 88.74% | 0 0.00% 88.74% | 276 10.68% 99.42% | 10 0.39% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 1 0.04% 99.92% | 1 0.04% 99.96% | 1 0.04% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -407,13 +639,13 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2285
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 300
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 72.046667
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 70.724443
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 9.575496
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 9 3.00% 3.00% | 0 0.00% 3.00% | 0 0.00% 3.00% | 280 93.33% 96.33% | 11 3.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 78.033333
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 75.006009
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 25.337433
|
||||
system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 300
|
||||
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,21 +237,22 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardFromDir=system.ruby.network.slave[6]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[5]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -194,33 +260,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -234,12 +275,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -280,7 +321,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -305,11 +346,11 @@ clk_domain=system.ruby.clk_domain
|
|||
cluster_id=0
|
||||
eventq_index=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[2]
|
||||
|
|
@ -449,7 +490,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,260 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000045 # Number of seconds simulated
|
||||
sim_ticks 44968 # Number of ticks simulated
|
||||
final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000048 # Number of seconds simulated
|
||||
sim_ticks 48283 # Number of ticks simulated
|
||||
final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 32543 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 567670 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 162088 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 12943 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12941 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 242448 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 437744 # Number of bytes of host memory used
|
||||
host_seconds 0.20 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29760 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 29760 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 4992 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 465 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 465 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 616366009 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 616366009 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 103390427 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 103390427 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 719756436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 719756436 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 465 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 78 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 465 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 78 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24640 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 5120 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 29760 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 4992 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 32 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 36 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 69 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 48195 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 465 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 78 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 385 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 305.951220 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 201.196627 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 274.128379 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 25 30.49% 30.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 16 19.51% 50.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 13 15.85% 65.85% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 9 10.98% 76.83% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 8.54% 85.37% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 3 3.66% 89.02% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 4 4.88% 93.90% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 2 2.44% 96.34% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 3 3.66% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 249 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 249.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::248-255 1 100.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2437 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9752 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1925 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.33 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.33 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 510.32 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 21.21 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 616.37 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 103.39 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.15 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.99 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 299 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 77.66 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 88.76 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 76 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 45412 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 446040 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 247800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 1884480 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 2808000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 31539240 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 30693132 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 520800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 1263000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 37266360 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 38675220 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 793.272596 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 823.262378 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -21,129 +263,110 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 12.651488
|
||||
system.ruby.latency_hist::gmean 4.761588
|
||||
system.ruby.latency_hist::stdev 24.047137
|
||||
system.ruby.latency_hist | 2784 84.52% 84.52% | 87 2.64% 87.16% | 0 0.00% 87.16% | 0 0.00% 87.16% | 414 12.57% 99.73% | 3 0.09% 99.82% | 5 0.15% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.657863
|
||||
system.ruby.latency_hist::gmean 4.922626
|
||||
system.ruby.latency_hist::stdev 27.058784
|
||||
system.ruby.latency_hist | 2909 88.31% 88.31% | 378 11.48% 99.79% | 3 0.09% 99.88% | 0 0.00% 99.88% | 3 0.09% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
system.ruby.hit_latency_hist::samples 2784
|
||||
system.ruby.hit_latency_hist::samples 2750
|
||||
system.ruby.hit_latency_hist::mean 3
|
||||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2784
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::samples 510
|
||||
system.ruby.miss_latency_hist::mean 65.337255
|
||||
system.ruby.miss_latency_hist::gmean 59.286872
|
||||
system.ruby.miss_latency_hist::stdev 21.222000
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 87 17.06% 17.06% | 0 0.00% 17.06% | 0 0.00% 17.06% | 414 81.18% 98.24% | 3 0.59% 98.82% | 5 0.98% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 510
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2750
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 544
|
||||
system.ruby.miss_latency_hist::mean 67.534926
|
||||
system.ruby.miss_latency_hist::gmean 60.177697
|
||||
system.ruby.miss_latency_hist::stdev 30.933879
|
||||
system.ruby.miss_latency_hist | 159 29.23% 29.23% | 378 69.49% 98.71% | 3 0.55% 99.26% | 0 0.00% 99.26% | 3 0.55% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 544
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 6.188845
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 502
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 510
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 36144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4080
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 87 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 423 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 9.792519
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 846
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 578
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 814
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 933
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 60912
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 41616
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 6512
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 7464
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 499 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 423 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 76 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 313 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 77 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 77 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.154309 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 41 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 25 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 9 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.61% 3.61% | 10 2.00% 5.61% | 0 0.00% 5.61% | 34 6.81% 12.42% | 20 4.01% 16.43% | 19 3.81% 20.24% | 28 5.61% 25.85% | 21 4.21% 30.06% | 5 1.00% 31.06% | 3 0.60% 31.66% | 6 1.20% 32.87% | 4 0.80% 33.67% | 21 4.21% 37.88% | 40 8.02% 45.89% | 20 4.01% 49.90% | 3 0.60% 50.50% | 4 0.80% 51.30% | 5 1.00% 52.30% | 7 1.40% 53.71% | 13 2.61% 56.31% | 10 2.00% 58.32% | 16 3.21% 61.52% | 14 2.81% 64.33% | 41 8.22% 72.55% | 15 3.01% 75.55% | 5 1.00% 76.55% | 5 1.00% 77.56% | 12 2.40% 79.96% | 12 2.40% 82.36% | 18 3.61% 85.97% | 14 2.81% 88.78% | 56 11.22% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 499 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 3.603118
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 76
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 814
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 422
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5472
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 6512
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3376
|
||||
system.ruby.network.routers3.percent_links_utilized 6.528346
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 846
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 578
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 814
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 933
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 60912
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 41616
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 6512
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 7464
|
||||
system.ruby.network.msg_count.Request_Control 2799
|
||||
system.ruby.network.msg_count.Response_Data 2538
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 261
|
||||
system.ruby.network.msg_count.Writeback_Data 1734
|
||||
system.ruby.network.msg_count.Writeback_Control 6447
|
||||
system.ruby.network.msg_count.Unblock_Control 2798
|
||||
system.ruby.network.msg_byte.Request_Control 22392
|
||||
system.ruby.network.msg_byte.Response_Data 182736
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 18792
|
||||
system.ruby.network.msg_byte.Writeback_Data 124848
|
||||
system.ruby.network.msg_byte.Writeback_Control 51576
|
||||
system.ruby.network.msg_byte.Unblock_Control 22384
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.874739
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 8.967442
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 930
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 560
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1029
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 66960
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8232
|
||||
system.ruby.network.routers2.percent_links_utilized 3.092186
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 464
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3712
|
||||
system.ruby.network.routers3.percent_links_utilized 5.978295
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 930
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 560
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1004
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 156
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1029
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 66960
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8232
|
||||
system.ruby.network.msg_count.Request_Control 3027
|
||||
system.ruby.network.msg_count.Response_Data 2790
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 237
|
||||
system.ruby.network.msg_count.Writeback_Data 1680
|
||||
system.ruby.network.msg_count.Writeback_Control 3480
|
||||
system.ruby.network.msg_count.Unblock_Control 3086
|
||||
system.ruby.network.msg_byte.Request_Control 24216
|
||||
system.ruby.network.msg_byte.Response_Data 200880
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 17064
|
||||
system.ruby.network.msg_byte.Writeback_Data 120960
|
||||
system.ruby.network.msg_byte.Writeback_Control 27840
|
||||
system.ruby.network.msg_byte.Unblock_Control 24688
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -177,7 +400,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 44968 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 48283 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -196,7 +419,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 44968 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 48283 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -235,106 +458,100 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.661804
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.589959
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.715887
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 502
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.159518
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 510
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 36144
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4080
|
||||
system.ruby.network.routers1.throttle0.link_utilization 11.401441
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 502
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers1.throttle0.link_utilization 10.574115
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 510
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 36144
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4080
|
||||
system.ruby.network.routers1.throttle1.link_utilization 8.183597
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 76
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers1.throttle1.link_utilization 7.360769
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 423
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5472
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 465
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3384
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.520681
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 76
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 422
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5472
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3376
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.685554
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.661804
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 87
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3720
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.769774
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 464
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3712
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.414597
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.589959
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 79
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 6264
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5688
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers3.throttle1.link_utilization 11.401441
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 510
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 423
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 502
|
||||
system.ruby.network.routers3.throttle1.link_utilization 10.574115
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 465
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 502
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 510
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 4080
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 30456
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 36144
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 564
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 4352
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 33480
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4080
|
||||
system.ruby.network.routers3.throttle2.link_utilization 2.521793
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 423
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 76
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 407
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 331
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 423
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3384
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5472
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 3256
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 2648
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3384
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.770810
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 465
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 465
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3720
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3720
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 28.869880
|
||||
system.ruby.LD.latency_hist::gmean 10.683547
|
||||
system.ruby.LD.latency_hist::stdev 33.485413
|
||||
system.ruby.LD.latency_hist | 233 56.14% 56.14% | 43 10.36% 66.51% | 0 0.00% 66.51% | 0 0.00% 66.51% | 133 32.05% 98.55% | 1 0.24% 98.80% | 4 0.96% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 27.831325
|
||||
system.ruby.LD.latency_hist::gmean 10.396167
|
||||
system.ruby.LD.latency_hist::stdev 35.321716
|
||||
system.ruby.LD.latency_hist | 274 66.02% 66.02% | 45 10.84% 76.87% | 87 20.96% 97.83% | 7 1.69% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -343,44 +560,44 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 233
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 182
|
||||
system.ruby.LD.miss_latency_hist::mean 61.989011
|
||||
system.ruby.LD.miss_latency_hist::gmean 54.309691
|
||||
system.ruby.LD.miss_latency_hist::stdev 24.499406
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 43 23.63% 23.63% | 0 0.00% 23.63% | 0 0.00% 23.63% | 133 73.08% 96.70% | 1 0.55% 97.25% | 4 2.20% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 59.620879
|
||||
system.ruby.LD.miss_latency_hist::gmean 51.035744
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.307641
|
||||
system.ruby.LD.miss_latency_hist | 41 22.53% 22.53% | 45 24.73% 47.25% | 87 47.80% 95.05% | 7 3.85% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 182
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 14.547619
|
||||
system.ruby.ST.latency_hist::gmean 5.302369
|
||||
system.ruby.ST.latency_hist::stdev 25.764411
|
||||
system.ruby.ST.latency_hist | 236 80.27% 80.27% | 15 5.10% 85.37% | 0 0.00% 85.37% | 0 0.00% 85.37% | 42 14.29% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 20.806122
|
||||
system.ruby.ST.latency_hist::gmean 7.447374
|
||||
system.ruby.ST.latency_hist::stdev 29.113873
|
||||
system.ruby.ST.latency_hist | 202 68.71% 68.71% | 12 4.08% 72.79% | 0 0.00% 72.79% | 35 11.90% 84.69% | 37 12.59% 97.28% | 7 2.38% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist::samples 236
|
||||
system.ruby.ST.hit_latency_hist::samples 202
|
||||
system.ruby.ST.hit_latency_hist::mean 3
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 236
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 202
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 58
|
||||
system.ruby.ST.miss_latency_hist::mean 61.534483
|
||||
system.ruby.ST.miss_latency_hist::gmean 53.817463
|
||||
system.ruby.ST.miss_latency_hist::stdev 24.770678
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 15 25.86% 25.86% | 0 0.00% 25.86% | 0 0.00% 25.86% | 42 72.41% 98.28% | 1 1.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 58
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 92
|
||||
system.ruby.ST.miss_latency_hist::mean 59.902174
|
||||
system.ruby.ST.miss_latency_hist::gmean 54.831044
|
||||
system.ruby.ST.miss_latency_hist::stdev 21.909935
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 12 13.04% 13.04% | 0 0.00% 13.04% | 35 38.04% 51.09% | 37 40.22% 91.30% | 7 7.61% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 92
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 9.832108
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.131370
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.770372
|
||||
system.ruby.IFETCH.latency_hist | 2315 89.56% 89.56% | 29 1.12% 90.68% | 0 0.00% 90.68% | 0 0.00% 90.68% | 239 9.25% 99.92% | 1 0.04% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 10.569439
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.165075
|
||||
system.ruby.IFETCH.latency_hist::stdev 24.278647
|
||||
system.ruby.IFETCH.latency_hist | 2341 90.56% 90.56% | 239 9.25% 99.81% | 2 0.08% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -389,90 +606,113 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2315
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 270
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 68.411111
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 64.218167
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 17.266269
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 29 10.74% 10.74% | 0 0.00% 10.74% | 0 0.00% 10.74% | 239 88.52% 99.26% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 75.470370
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 69.413198
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 30.681798
|
||||
system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 270
|
||||
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 294 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 506 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 510 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 502 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 58 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 509 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 436 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 108 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 20 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 482 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 92 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 108 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 182 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 270 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 58 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 82 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1220 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 406 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 49 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1095 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 7 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 444 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 99 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 114 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Load 108 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Ifetch 2315 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Store 34 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 396 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 13 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 14 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 89 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 93 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 3 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 82 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 65 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 103 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 94 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 58 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 58 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 452 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 502 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 454 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 58 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 502 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data_Exclusive 380 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 396 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SM.Exclusive_Data 34 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 92 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 436 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 16 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack 20 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 376 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 452 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 92 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTS_only 396 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 465 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 407 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 510 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 407 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 380 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 502 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 72 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 407 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 396 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 78 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Unblock 456 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 108 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 443 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 45 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_GETX 32 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETS 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.S.L2_Replacement 336 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 20 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SLS.L2_Replacement 29 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 16 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 78 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 376 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SW.Unblock 20 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data_Exclusive 380 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 380 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 72 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.L1_GETS 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 407 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 43 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 380 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 407 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 422 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Clean_Writeback 331 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 76 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 423 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 76 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 43 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 380 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 74 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 407 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Exclusive_Unblock 379 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 380 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Ack 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 43 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 43 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Clean_Writeback 331 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 76 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Unblock 385 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 46 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMLS.Data 34 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 385 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unblock 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,7 +237,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
|
|
@ -182,16 +247,17 @@ distributed_persistent=true
|
|||
eventq_index=0
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[10]
|
||||
dmaResponseFromDir=system.ruby.network.slave[9]
|
||||
memory=system.mem_ctrls.port
|
||||
persistentFromDir=system.ruby.network.slave[8]
|
||||
persistentToDir=system.ruby.network.master[9]
|
||||
requestFromDir=system.ruby.network.slave[6]
|
||||
|
|
@ -202,33 +268,8 @@ responseToDir=system.ruby.network.master[8]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -248,13 +289,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -297,7 +338,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -326,9 +367,9 @@ filtering_enabled=true
|
|||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[3]
|
||||
|
|
@ -469,7 +510,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,260 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000043 # Number of seconds simulated
|
||||
sim_ticks 43073 # Number of ticks simulated
|
||||
final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000044 # Number of seconds simulated
|
||||
sim_ticks 43869 # Number of ticks simulated
|
||||
final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51660 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51645 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 862979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 159984 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 107 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1826 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435688 # Number of bytes of host memory used
|
||||
host_seconds 24.02 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 5376 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 653582256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 653582256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 122546673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 122546673 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 776128929 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 776128929 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 448 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 84 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 84 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 4672 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 28672 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 5376 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 73 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 38 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 72 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 60 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 43790 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 448 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 84 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 309.621622 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 203.292189 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 280.679347 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 21 28.38% 28.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 52.70% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 10 13.51% 66.22% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 7 9.46% 75.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 8 10.81% 86.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 3 4.05% 90.54% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 2 2.70% 93.24% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 94.59% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 4 5.41% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2655 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9780 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 7.08 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 26.08 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 547.08 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 23.34 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 653.58 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 122.55 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 4.46 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.27 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 294 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 78.40 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 82.31 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 1300 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 37882 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 158760 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 355320 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 88200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 197400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 1697280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 2483520 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 2542800 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 25360668 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 26385300 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 1267800 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 369000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 31115508 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 32499228 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 793.965501 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 829.273488 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -21,29 +263,29 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 12.076199
|
||||
system.ruby.latency_hist::gmean 3.436747
|
||||
system.ruby.latency_hist::stdev 24.316992
|
||||
system.ruby.latency_hist | 2776 84.27% 84.27% | 70 2.13% 86.40% | 0 0.00% 86.40% | 0 0.00% 86.40% | 435 13.21% 99.61% | 3 0.09% 99.70% | 4 0.12% 99.82% | 6 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 12.317851
|
||||
system.ruby.latency_hist::gmean 3.428807
|
||||
system.ruby.latency_hist::stdev 27.092783
|
||||
system.ruby.latency_hist | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 4
|
||||
system.ruby.hit_latency_hist::max_bucket 39
|
||||
system.ruby.hit_latency_hist::samples 2846
|
||||
system.ruby.hit_latency_hist::mean 2.555868
|
||||
system.ruby.hit_latency_hist::gmean 2.127279
|
||||
system.ruby.hit_latency_hist::stdev 3.505788
|
||||
system.ruby.hit_latency_hist | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::mean 2.554462
|
||||
system.ruby.hit_latency_hist::gmean 2.127153
|
||||
system.ruby.hit_latency_hist::stdev 3.497278
|
||||
system.ruby.hit_latency_hist | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2846
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 448
|
||||
system.ruby.miss_latency_hist::mean 72.555804
|
||||
system.ruby.miss_latency_hist::gmean 72.369886
|
||||
system.ruby.miss_latency_hist::stdev 5.907301
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 435 97.10% 97.10% | 3 0.67% 97.77% | 4 0.89% 98.66% | 6 1.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 74.341518
|
||||
system.ruby.miss_latency_hist::gmean 71.176280
|
||||
system.ruby.miss_latency_hist::stdev 29.447133
|
||||
system.ruby.miss_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 1 0.22% 99.33% | 3 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 448
|
||||
system.ruby.Directory.incomplete_times 447
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits
|
||||
|
|
@ -52,57 +294,50 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709
|
|||
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 5.629397
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.531811
|
||||
system.ruby.network.routers0.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers0.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers0.msg_count.Persistent_Control::3 8
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 4.203329
|
||||
system.ruby.network.routers1.percent_links_utilized 4.129340
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers1.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::4 586
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::4 365
|
||||
system.ruby.network.routers1.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 3632
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 532 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 448 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 84 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 299 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 150 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 150 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.281955 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 38 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 90 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 6 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 16 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 19 3.57% 3.57% | 10 1.88% 5.45% | 0 0.00% 5.45% | 39 7.33% 12.78% | 20 3.76% 16.54% | 19 3.57% 20.11% | 31 5.83% 25.94% | 22 4.14% 30.08% | 5 0.94% 31.02% | 3 0.56% 31.58% | 6 1.13% 32.71% | 4 0.75% 33.46% | 22 4.14% 37.59% | 41 7.71% 45.30% | 22 4.14% 49.44% | 3 0.56% 50.00% | 4 0.75% 50.75% | 6 1.13% 51.88% | 7 1.32% 53.20% | 13 2.44% 55.64% | 10 1.88% 57.52% | 18 3.38% 60.90% | 14 2.63% 63.53% | 42 7.89% 71.43% | 16 3.01% 74.44% | 5 0.94% 75.38% | 5 0.94% 76.32% | 12 2.26% 78.57% | 13 2.44% 81.02% | 18 3.38% 84.40% | 14 2.63% 87.03% | 69 12.97% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 532 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 3.254359
|
||||
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers2.percent_links_utilized 3.197588
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::4 84
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::4 365
|
||||
system.ruby.network.routers2.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::2 3632
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers3.percent_links_utilized 4.362362
|
||||
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers3.percent_links_utilized 4.286246
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers3.msg_count.Response_Data::4 448
|
||||
|
|
@ -110,6 +345,7 @@ system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 70
|
|||
system.ruby.network.routers3.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::4 586
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::4 365
|
||||
system.ruby.network.routers3.msg_count.Persistent_Control::3 8
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::2 3632
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::4 32256
|
||||
|
|
@ -117,19 +353,22 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 5040
|
|||
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 64
|
||||
system.ruby.network.msg_count.Request_Control 2916
|
||||
system.ruby.network.msg_count.Response_Data 1344
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 210
|
||||
system.ruby.network.msg_count.Response_Control 3
|
||||
system.ruby.network.msg_count.Writeback_Data 1758
|
||||
system.ruby.network.msg_count.Writeback_Control 1095
|
||||
system.ruby.network.msg_count.Persistent_Control 24
|
||||
system.ruby.network.msg_byte.Request_Control 23328
|
||||
system.ruby.network.msg_byte.Response_Data 96768
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 15120
|
||||
system.ruby.network.msg_byte.Response_Control 24
|
||||
system.ruby.network.msg_byte.Writeback_Data 126576
|
||||
system.ruby.network.msg_byte.Writeback_Control 8760
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.msg_byte.Persistent_Control 192
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -163,7 +402,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 43073 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 43869 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -182,7 +421,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 43073 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 43869 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -221,24 +460,30 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.412904
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.319246
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.845890
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.744375
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.845890
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.744375
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.560769
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.514304
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
|
||||
|
|
@ -249,66 +494,72 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5
|
|||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.828292
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.799676
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365
|
||||
system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.680426
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.595500
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.412904
|
||||
system.ruby.network.routers3.throttle0.link_utilization 5.314687
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
|
||||
system.ruby.network.routers3.throttle1.link_utilization 5.845890
|
||||
system.ruby.network.routers3.throttle1.link_utilization 5.744375
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502
|
||||
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.828292
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.799676
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365
|
||||
system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 4
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 32
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 29.339759
|
||||
system.ruby.LD.latency_hist::gmean 8.884516
|
||||
system.ruby.LD.latency_hist::stdev 33.606098
|
||||
system.ruby.LD.latency_hist | 233 56.14% 56.14% | 33 7.95% 64.10% | 0 0.00% 64.10% | 0 0.00% 64.10% | 143 34.46% 98.55% | 1 0.24% 98.80% | 2 0.48% 99.28% | 3 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 27.573494
|
||||
system.ruby.LD.latency_hist::gmean 8.538591
|
||||
system.ruby.LD.latency_hist::stdev 33.296048
|
||||
system.ruby.LD.latency_hist | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 67 16.14% 92.29% | 19 4.58% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 4
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 39
|
||||
system.ruby.LD.hit_latency_hist::samples 266
|
||||
system.ruby.LD.hit_latency_hist::mean 4.845865
|
||||
system.ruby.LD.hit_latency_hist::gmean 2.735122
|
||||
system.ruby.LD.hit_latency_hist::stdev 7.577195
|
||||
system.ruby.LD.hit_latency_hist | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::mean 4.830827
|
||||
system.ruby.LD.hit_latency_hist::gmean 2.733388
|
||||
system.ruby.LD.hit_latency_hist::stdev 7.539428
|
||||
system.ruby.LD.hit_latency_hist | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 266
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::samples 149
|
||||
system.ruby.LD.miss_latency_hist::mean 73.067114
|
||||
system.ruby.LD.miss_latency_hist::gmean 72.788354
|
||||
system.ruby.LD.miss_latency_hist::stdev 7.286293
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 143 95.97% 95.97% | 1 0.67% 96.64% | 2 1.34% 97.99% | 3 2.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 68.174497
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.240145
|
||||
system.ruby.LD.miss_latency_hist::stdev 20.253038
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 67 44.97% 78.52% | 19 12.75% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 1 0.67% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 149
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 15.690476
|
||||
system.ruby.ST.latency_hist::gmean 4.247505
|
||||
system.ruby.ST.latency_hist::stdev 27.630351
|
||||
system.ruby.ST.latency_hist | 228 77.55% 77.55% | 14 4.76% 82.31% | 0 0.00% 82.31% | 0 0.00% 82.31% | 49 16.67% 98.98% | 0 0.00% 98.98% | 0 0.00% 98.98% | 3 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 13.656463
|
||||
system.ruby.ST.latency_hist::gmean 4.101596
|
||||
system.ruby.ST.latency_hist::stdev 23.959601
|
||||
system.ruby.ST.latency_hist | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 22 7.48% 97.62% | 7 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 4
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 39
|
||||
|
|
@ -321,18 +572,18 @@ system.ruby.ST.hit_latency_hist::total 242
|
|||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::samples 52
|
||||
system.ruby.ST.miss_latency_hist::mean 73.711538
|
||||
system.ruby.ST.miss_latency_hist::gmean 73.204309
|
||||
system.ruby.ST.miss_latency_hist::stdev 9.969240
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 94.23% 94.23% | 0 0.00% 94.23% | 0 0.00% 94.23% | 3 5.77% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 62.211538
|
||||
system.ruby.ST.miss_latency_hist::gmean 60.076620
|
||||
system.ruby.ST.miss_latency_hist::stdev 16.157723
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 22 42.31% 86.54% | 7 13.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 52
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 8.893617
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.880478
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.653523
|
||||
system.ruby.IFETCH.latency_hist | 2315 89.56% 89.56% | 23 0.89% 90.44% | 0 0.00% 90.44% | 0 0.00% 90.44% | 243 9.40% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.716441
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.901884
|
||||
system.ruby.IFETCH.latency_hist::stdev 25.462800
|
||||
system.ruby.IFETCH.latency_hist | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 4
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 39
|
||||
|
|
@ -342,13 +593,13 @@ system.ruby.IFETCH.hit_latency_hist::gmean 2.050316
|
|||
system.ruby.IFETCH.hit_latency_hist::stdev 2.270469
|
||||
system.ruby.IFETCH.hit_latency_hist | 2315 99.02% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2338
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 247
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 72.004049
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 71.944768
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 3.180860
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 243 98.38% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 80.615385
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 77.741160
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 34.366891
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 247
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -360,18 +611,18 @@ system.ruby.L1Cache.hit_mach_latency_hist::total 2776
|
|||
system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 4
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 39
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::samples 70
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 24.600000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 24.570558
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.159710
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::mean 24.542857
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 24.511430
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::stdev 1.200069
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 70
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 448
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 72.555804
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 72.369886
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 5.907301
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 435 97.10% 97.10% | 3 0.67% 97.77% | 4 0.89% 98.66% | 6 1.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 74.341518
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 71.176280
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 29.447133
|
||||
system.ruby.Directory.miss_mach_latency_hist | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 1 0.22% 99.33% | 3 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 448
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -391,13 +642,13 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples
|
|||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 70
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 70.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 83
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 83.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -409,18 +660,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 233
|
|||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 33
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 24.939394
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 24.936912
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 0.348155
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 24.818182
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 24.809790
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 0.635145
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 33
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 149
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 73.067114
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 72.788354
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.286293
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 143 95.97% 95.97% | 1 0.67% 96.64% | 2 1.34% 97.99% | 3 2.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 68.174497
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.240145
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 20.253038
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 67 44.97% 78.52% | 19 12.75% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 1 0.67% 99.33% | 1 0.67% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 149
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -440,10 +691,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 14
|
|||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 52
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 73.711538
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 73.204309
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 9.969240
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 94.23% 94.23% | 0 0.00% 94.23% | 0 0.00% 94.23% | 3 5.77% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.211538
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 60.076620
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 16.157723
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 22 42.31% 86.54% | 7 13.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 52
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -459,13 +710,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 25
|
|||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 25.000000
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 23 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 23
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 247
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 72.004049
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 71.944768
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 3.180860
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 243 98.38% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 80.615385
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.741160
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.366891
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247
|
||||
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
|
||||
|
|
@ -474,6 +725,8 @@ system.ruby.L1Cache_Controller.L1_Replacement 504 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.Data_Shared 56 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data_All_Tokens 462 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Request_Timeout 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 461 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Load 182 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Ifetch 270 0.00% 0.00%
|
||||
|
|
@ -483,14 +736,15 @@ system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1161 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1150 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 104 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 996 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1007 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00%
|
||||
|
|
@ -503,16 +757,21 @@ system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
|
|||
system.ruby.L1Cache_Controller.SM.Data_All_Tokens 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_Shared 56 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_All_Tokens 396 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Request_Timeout 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 448 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS_Last_Token 4 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 66 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 458 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Shared_Data 21 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_All_Tokens 481 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Persistent_GETS 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 396 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 50 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 18 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 448 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 2 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I.L2_Replacement 9 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00%
|
||||
|
|
@ -526,8 +785,11 @@ system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 27 0.00%
|
|||
system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 70 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 405 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 61 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 398 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00%
|
||||
|
|
@ -543,9 +805,12 @@ system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00
|
|||
system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.O_W.GETX 12 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.O_W.GETS 9 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_W.Memory_Data 448 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,26 +237,27 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
children=directory probeFilter
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
eventq_index=0
|
||||
from_memory_controller_latency=2
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
probeFilter=system.ruby.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[5]
|
||||
dmaResponseFromDir=system.ruby.network.slave[5]
|
||||
forwardFromDir=system.ruby.network.slave[3]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[4]
|
||||
responseFromDir=system.ruby.network.slave[4]
|
||||
responseToDir=system.ruby.network.master[3]
|
||||
|
|
@ -200,33 +266,8 @@ unblockToDir=system.ruby.network.master[2]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.probeFilter]
|
||||
|
|
@ -259,11 +300,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -319,7 +360,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -423,7 +464,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,260 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000035 # Number of seconds simulated
|
||||
sim_ticks 35432 # Number of ticks simulated
|
||||
final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000036 # Number of seconds simulated
|
||||
sim_ticks 36255 # Number of ticks simulated
|
||||
final_tick 36255 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51262 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 51245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 704386 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 159904 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 16369 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 16367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 230240 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435584 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 5184 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 778485726 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 778485726 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 142987174 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 142987174 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 921472900 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 921472900 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 441 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 81 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 81 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 4224 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 28224 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 5184 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 35 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 72 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 36187 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 441 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 81 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 349.611940 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 229.746544 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 299.426571 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 17 25.37% 25.37% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 14 20.90% 46.27% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 61.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 5 7.46% 68.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 7 10.45% 79.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 7.46% 86.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 4 5.97% 92.54% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 1 1.49% 94.03% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 2306 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 9431 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 6.15 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 25.15 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 661.98 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 28.24 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 778.49 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 142.99 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 5.39 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 5.17 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 0.22 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 21.52 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 301 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.27 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 69.32 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 1040 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 30367 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 143640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 309960 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 79800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 172200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 1634880 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 2446080 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 20833956 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 21069936 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 567000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 360000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 25293516 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 26558304 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 805.423386 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 845.698128 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 1
|
||||
system.ruby.outstanding_req_hist::max_bucket 9
|
||||
|
|
@ -21,13 +263,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 32
|
||||
system.ruby.latency_hist::max_bucket 319
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 9.756527
|
||||
system.ruby.latency_hist::gmean 3.263022
|
||||
system.ruby.latency_hist::stdev 19.389629
|
||||
system.ruby.latency_hist | 2853 86.61% 86.61% | 0 0.00% 86.61% | 0 0.00% 86.61% | 421 12.78% 99.39% | 2 0.06% 99.45% | 12 0.36% 99.82% | 0 0.00% 99.82% | 6 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 10.006375
|
||||
system.ruby.latency_hist::gmean 3.254924
|
||||
system.ruby.latency_hist::stdev 22.032392
|
||||
system.ruby.latency_hist | 2912 88.40% 88.40% | 290 8.80% 97.21% | 87 2.64% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 2
|
||||
system.ruby.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -37,13 +279,13 @@ system.ruby.hit_latency_hist::gmean 2.092620
|
|||
system.ruby.hit_latency_hist::stdev 1.690154
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2853
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 32
|
||||
system.ruby.miss_latency_hist::max_bucket 319
|
||||
system.ruby.miss_latency_hist::samples 441
|
||||
system.ruby.miss_latency_hist::mean 58.215420
|
||||
system.ruby.miss_latency_hist::gmean 57.777235
|
||||
system.ruby.miss_latency_hist::stdev 8.819211
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 421 95.46% 95.46% | 2 0.45% 95.92% | 12 2.72% 98.64% | 0 0.00% 98.64% | 6 1.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 60.081633
|
||||
system.ruby.miss_latency_hist::gmean 56.714803
|
||||
system.ruby.miss_latency_hist::stdev 26.697338
|
||||
system.ruby.miss_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00%
|
||||
system.ruby.miss_latency_hist::total 441
|
||||
system.ruby.Directory.incomplete_times 440
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
|
|
@ -56,7 +298,8 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585
|
|||
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 4.778872
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 4.670390
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -71,23 +314,10 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400
|
|||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 522 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 441 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 81 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 246 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 39 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 39 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.074713 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 15 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 15 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 5 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.45% 3.45% | 10 1.92% 5.36% | 0 0.00% 5.36% | 36 6.90% 12.26% | 20 3.83% 16.09% | 19 3.64% 19.73% | 31 5.94% 25.67% | 22 4.21% 29.89% | 5 0.96% 30.84% | 4 0.77% 31.61% | 7 1.34% 32.95% | 4 0.77% 33.72% | 22 4.21% 37.93% | 41 7.85% 45.79% | 22 4.21% 50.00% | 3 0.57% 50.57% | 4 0.77% 51.34% | 6 1.15% 52.49% | 7 1.34% 53.83% | 13 2.49% 56.32% | 10 1.92% 58.24% | 18 3.45% 61.69% | 14 2.68% 64.37% | 41 7.85% 72.22% | 16 3.07% 75.29% | 5 0.96% 76.25% | 5 0.96% 77.20% | 12 2.30% 79.50% | 13 2.49% 81.99% | 18 3.45% 85.44% | 14 2.68% 88.12% | 62 11.88% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 522 # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
|
||||
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 4.778872
|
||||
system.ruby.network.routers1.percent_links_utilized 4.670390
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -102,7 +332,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400
|
|||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers2.percent_links_utilized 4.778872
|
||||
system.ruby.network.routers2.percent_links_utilized 4.670390
|
||||
system.ruby.network.routers2.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::5 81
|
||||
|
|
@ -127,7 +357,6 @@ system.ruby.network.msg_byte.Response_Data 95256
|
|||
system.ruby.network.msg_byte.Writeback_Data 17496
|
||||
system.ruby.network.msg_byte.Writeback_Control 28656
|
||||
system.ruby.network.msg_byte.Unblock_Control 10560
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -161,7 +390,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 35432 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 36255 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -180,7 +409,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 35432 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 36255 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -219,12 +448,12 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.200610
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.059854
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.357135
|
||||
system.ruby.network.routers0.throttle1.link_utilization 3.280927
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -235,7 +464,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.357135
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.280927
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -246,17 +475,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.200610
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.059854
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.200610
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.059854
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.357135
|
||||
system.ruby.network.routers2.throttle1.link_utilization 3.280927
|
||||
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425
|
||||
|
|
@ -267,13 +496,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 5832
|
|||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 3400
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 2752
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 22.831325
|
||||
system.ruby.LD.latency_hist::gmean 7.691886
|
||||
system.ruby.LD.latency_hist::stdev 27.052293
|
||||
system.ruby.LD.latency_hist | 269 64.82% 64.82% | 0 0.00% 64.82% | 0 0.00% 64.82% | 137 33.01% 97.83% | 2 0.48% 98.31% | 5 1.20% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 22.096386
|
||||
system.ruby.LD.latency_hist::gmean 7.349549
|
||||
system.ruby.LD.latency_hist::stdev 32.133859
|
||||
system.ruby.LD.latency_hist | 313 75.42% 75.42% | 69 16.63% 92.05% | 31 7.47% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 2
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -283,21 +512,21 @@ system.ruby.LD.hit_latency_hist::gmean 2.569339
|
|||
system.ruby.LD.hit_latency_hist::stdev 3.752134
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 269
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 146
|
||||
system.ruby.LD.miss_latency_hist::mean 58.500000
|
||||
system.ruby.LD.miss_latency_hist::gmean 58.001087
|
||||
system.ruby.LD.miss_latency_hist::stdev 9.336063
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 93.84% 93.84% | 2 1.37% 95.21% | 5 3.42% 98.63% | 0 0.00% 98.63% | 2 1.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 56.410959
|
||||
system.ruby.LD.miss_latency_hist::gmean 50.960600
|
||||
system.ruby.LD.miss_latency_hist::stdev 33.061838
|
||||
system.ruby.LD.miss_latency_hist | 44 30.14% 30.14% | 69 47.26% 77.40% | 31 21.23% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 1 0.68% 99.32% | 1 0.68% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 146
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 8
|
||||
system.ruby.ST.latency_hist::max_bucket 79
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 12.010204
|
||||
system.ruby.ST.latency_hist::gmean 3.697502
|
||||
system.ruby.ST.latency_hist::stdev 23.153956
|
||||
system.ruby.ST.latency_hist | 247 84.01% 84.01% | 0 0.00% 84.01% | 0 0.00% 84.01% | 43 14.63% 98.64% | 0 0.00% 98.64% | 0 0.00% 98.64% | 0 0.00% 98.64% | 4 1.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 10.299320
|
||||
system.ruby.ST.latency_hist::gmean 3.570687
|
||||
system.ruby.ST.latency_hist::stdev 19.141619
|
||||
system.ruby.ST.latency_hist | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 4 1.36% 97.96% | 6 2.04% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 2
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -307,21 +536,21 @@ system.ruby.ST.hit_latency_hist::gmean 2.173865
|
|||
system.ruby.ST.hit_latency_hist::stdev 2.273678
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 247
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 8
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 79
|
||||
system.ruby.ST.miss_latency_hist::samples 47
|
||||
system.ruby.ST.miss_latency_hist::mean 62.042553
|
||||
system.ruby.ST.miss_latency_hist::gmean 60.281421
|
||||
system.ruby.ST.miss_latency_hist::stdev 18.514339
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 43 91.49% 91.49% | 0 0.00% 91.49% | 0 0.00% 91.49% | 0 0.00% 91.49% | 4 8.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 51.340426
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.458941
|
||||
system.ruby.ST.miss_latency_hist::stdev 16.053276
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 4 8.51% 87.23% | 6 12.77% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 47
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 7.401161
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.803225
|
||||
system.ruby.IFETCH.latency_hist::stdev 16.355131
|
||||
system.ruby.IFETCH.latency_hist | 2337 90.41% 90.41% | 0 0.00% 90.41% | 0 0.00% 90.41% | 241 9.32% 99.73% | 0 0.00% 99.73% | 7 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.032108
|
||||
system.ruby.IFETCH.latency_hist::gmean 2.826057
|
||||
system.ruby.IFETCH.latency_hist::stdev 19.602299
|
||||
system.ruby.IFETCH.latency_hist | 2337 90.41% 90.41% | 199 7.70% 98.10% | 46 1.78% 99.88% | 1 0.04% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 2 0.08% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 2
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 19
|
||||
|
|
@ -331,13 +560,13 @@ system.ruby.IFETCH.hit_latency_hist::gmean 2.035554
|
|||
system.ruby.IFETCH.hit_latency_hist::stdev 1.062463
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2337
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 248
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 57.322581
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 57.184185
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 4.462254
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 241 97.18% 97.18% | 0 0.00% 97.18% | 7 2.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 63.899194
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 62.229629
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 23.299188
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 248
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1
|
||||
system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -353,13 +582,13 @@ system.ruby.L2Cache.hit_mach_latency_hist::mean 13
|
|||
system.ruby.L2Cache.hit_mach_latency_hist::gmean 13.000000
|
||||
system.ruby.L2Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L2Cache.hit_mach_latency_hist::total 69
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 32
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 319
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 441
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 58.215420
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 57.777235
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 8.819211
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 421 95.46% 95.46% | 2 0.45% 95.92% | 12 2.72% 98.64% | 0 0.00% 98.64% | 6 1.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 60.081633
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 56.714803
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 26.697338
|
||||
system.ruby.Directory.miss_mach_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 441
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -376,10 +605,10 @@ system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
|
|||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 9
|
||||
|
|
@ -401,13 +630,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 13
|
|||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 13.000000
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 36
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 146
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.500000
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 58.001087
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 9.336063
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 93.84% 93.84% | 2 1.37% 95.21% | 5 3.42% 98.63% | 0 0.00% 98.63% | 2 1.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 56.410959
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 50.960600
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.061838
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 44 30.14% 30.14% | 69 47.26% 77.40% | 31 21.23% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 0 0.00% 98.63% | 1 0.68% 99.32% | 1 0.68% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 146
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -423,13 +652,13 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 13
|
|||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 13
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 11
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 8
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 79
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 47
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.042553
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 60.281421
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 18.514339
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 43 91.49% 91.49% | 0 0.00% 91.49% | 0 0.00% 91.49% | 0 0.00% 91.49% | 4 8.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.340426
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.458941
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 16.053276
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 4 8.51% 87.23% | 6 12.77% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 47
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9
|
||||
|
|
@ -445,13 +674,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::mean 13
|
|||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::gmean 13
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 22
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 248
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.322581
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 57.184185
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 4.462254
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 241 97.18% 97.18% | 0 0.00% 97.18% | 7 2.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 63.899194
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.229629
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 23.299188
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248
|
||||
system.ruby.L1Cache_Controller.Load 422 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00%
|
||||
|
|
@ -495,7 +724,7 @@ system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.0
|
|||
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 51 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 410 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 409 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUT 425 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
|
|
@ -511,7 +740,7 @@ system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00%
|
|||
system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETS 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -136,17 +136,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -156,9 +221,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -172,56 +237,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -235,11 +276,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -264,7 +305,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -368,7 +409,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,266 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000052 # Number of seconds simulated
|
||||
sim_ticks 52498 # Number of ticks simulated
|
||||
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000048 # Number of seconds simulated
|
||||
sim_ticks 47840 # Number of ticks simulated
|
||||
final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 55191 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55175 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1123673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 158428 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 31483 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31473 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 584131 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435420 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 39808 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 837458194 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 837458194 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 832107023 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 832107023 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1669565217 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1669565217 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 626 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 622 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 24704 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 15360 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 23360 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 240 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 225 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 70 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 29 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 46 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 73 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 4 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 20 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 14 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 33 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 47801 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 626 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 386 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 21 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 24 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 25 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 438.605505 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 303.845174 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 335.937991 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 14 12.84% 12.84% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 30 27.52% 40.37% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 12 11.01% 51.38% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 11 10.09% 61.47% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 6 5.50% 66.97% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 9 8.26% 75.23% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 9 8.26% 83.49% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 4 3.67% 87.16% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 14 12.84% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.863636 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 16.473921 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 4.443245 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 3 13.64% 13.64% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 5 22.73% 36.36% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 9 40.91% 77.27% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 4 18.18% 95.45% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.590909 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.555699 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.140555 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 9.09% 86.36% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 13.64% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 4080 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 11414 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 1930 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 10.57 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 29.57 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 516.39 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 488.29 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 837.46 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 832.11 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.85 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.81 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.93 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 289 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 349 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 74.87 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 38.30 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 140 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 45290 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 249480 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 574560 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 138600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 319200 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 2009280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 2758080 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 1575936 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 2208384 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 30369600 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 31087116 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 1545600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 916200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 38939856 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 40914900 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 828.930858 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 870.974540 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
|
|
@ -26,13 +274,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 3295
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 3294
|
||||
system.ruby.latency_hist::mean 14.937462
|
||||
system.ruby.latency_hist::gmean 5.391229
|
||||
system.ruby.latency_hist::stdev 24.804214
|
||||
system.ruby.latency_hist | 2668 81.00% 81.00% | 0 0.00% 81.00% | 0 0.00% 81.00% | 142 4.31% 85.31% | 448 13.60% 98.91% | 36 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.523376
|
||||
system.ruby.latency_hist::gmean 5.183572
|
||||
system.ruby.latency_hist::stdev 25.409311
|
||||
system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 3294
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -41,20 +289,21 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 2668
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 626
|
||||
system.ruby.miss_latency_hist::mean 65.814696
|
||||
system.ruby.miss_latency_hist::gmean 65.560981
|
||||
system.ruby.miss_latency_hist::stdev 6.377524
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 58.373802
|
||||
system.ruby.miss_latency_hist::gmean 53.319163
|
||||
system.ruby.miss_latency_hist::stdev 30.235728
|
||||
system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 626
|
||||
system.ruby.Directory.incomplete_times 625
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 5.943084
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.521739
|
||||
system.ruby.network.routers0.msg_count.Control::2 626
|
||||
system.ruby.network.routers0.msg_count.Data::2 622
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 626
|
||||
|
|
@ -63,20 +312,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 5.943084
|
||||
system.ruby.network.routers1.percent_links_utilized 6.521739
|
||||
system.ruby.network.routers1.msg_count.Control::2 626
|
||||
system.ruby.network.routers1.msg_count.Data::2 622
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 626
|
||||
|
|
@ -85,7 +321,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.percent_links_utilized 5.943084
|
||||
system.ruby.network.routers2.percent_links_utilized 6.521739
|
||||
system.ruby.network.routers2.msg_count.Control::2 626
|
||||
system.ruby.network.routers2.msg_count.Data::2 622
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 626
|
||||
|
|
@ -102,7 +338,6 @@ system.ruby.network.msg_byte.Control 15024
|
|||
system.ruby.network.msg_byte.Data 134352
|
||||
system.ruby.network.msg_byte.Response_Data 135216
|
||||
system.ruby.network.msg_byte.Writeback_Control 14928
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -136,7 +371,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 52498 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 47840 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -155,7 +390,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 52498 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 47840 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -194,32 +429,32 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.958322
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.538462
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.927845
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.505017
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 626
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 622
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.927845
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.505017
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 626
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 622
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784
|
||||
system.ruby.network.routers1.throttle1.link_utilization 5.958322
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.538462
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.throttle0.link_utilization 5.958322
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.538462
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.927845
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.505017
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 626
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 622
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008
|
||||
|
|
@ -234,13 +469,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 415
|
||||
system.ruby.LD.latency_hist::mean 40.332530
|
||||
system.ruby.LD.latency_hist::gmean 18.593767
|
||||
system.ruby.LD.latency_hist::stdev 31.596647
|
||||
system.ruby.LD.latency_hist | 170 40.96% 40.96% | 0 0.00% 40.96% | 0 0.00% 40.96% | 49 11.81% 52.77% | 178 42.89% 95.66% | 18 4.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 33.055422
|
||||
system.ruby.LD.latency_hist::gmean 15.599823
|
||||
system.ruby.LD.latency_hist::stdev 34.047272
|
||||
system.ruby.LD.latency_hist | 375 90.36% 90.36% | 33 7.95% 98.31% | 6 1.45% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 415
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -249,21 +484,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 170
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 245
|
||||
system.ruby.LD.miss_latency_hist::mean 66.236735
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.930929
|
||||
system.ruby.LD.miss_latency_hist::stdev 7.007686
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 20.00% 20.00% | 178 72.65% 92.65% | 18 7.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 53.910204
|
||||
system.ruby.LD.miss_latency_hist::gmean 48.970543
|
||||
system.ruby.LD.miss_latency_hist::stdev 30.013250
|
||||
system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 245
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 294
|
||||
system.ruby.ST.latency_hist::mean 20.945578
|
||||
system.ruby.ST.latency_hist::gmean 7.241284
|
||||
system.ruby.ST.latency_hist::stdev 28.634041
|
||||
system.ruby.ST.latency_hist | 210 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 17 5.78% 77.21% | 62 21.09% 98.30% | 5 1.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 17.248299
|
||||
system.ruby.ST.latency_hist::gmean 6.615603
|
||||
system.ruby.ST.latency_hist::stdev 28.817235
|
||||
system.ruby.ST.latency_hist | 210 71.43% 71.43% | 74 25.17% 96.60% | 8 2.72% 99.32% | 0 0.00% 99.32% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.ST.latency_hist::total 294
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -272,21 +507,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 210
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 84
|
||||
system.ruby.ST.miss_latency_hist::mean 65.809524
|
||||
system.ruby.ST.miss_latency_hist::gmean 65.546776
|
||||
system.ruby.ST.miss_latency_hist::stdev 6.522392
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 20.24% 20.24% | 62 73.81% 94.05% | 5 5.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 52.869048
|
||||
system.ruby.ST.miss_latency_hist::gmean 47.773810
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.671260
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 84
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.latency_hist::samples 2585
|
||||
system.ruby.IFETCH.latency_hist::mean 10.177176
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.273616
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.019716
|
||||
system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 0 0.00% 88.51% | 0 0.00% 88.51% | 76 2.94% 91.45% | 208 8.05% 99.50% | 13 0.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.964023
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.224377
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.618756
|
||||
system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 234 9.05% 97.56% | 49 1.90% 99.46% | 3 0.12% 99.57% | 2 0.08% 99.65% | 7 0.27% 99.92% | 1 0.04% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 2585
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -295,21 +530,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 2288
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 297
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.468013
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 65.261366
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 5.762163
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 76 25.59% 25.59% | 208 70.03% 95.62% | 13 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 63.612795
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 58.999958
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 28.587258
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 297
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 626
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 65.814696
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 65.560981
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 6.377524
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 142 22.68% 22.68% | 448 71.57% 94.25% | 36 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 58.373802
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 53.319163
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 30.235728
|
||||
system.ruby.Directory.miss_mach_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 626
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -332,34 +567,34 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 66.236735
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.930929
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.007686
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 20.00% 20.00% | 178 72.65% 92.65% | 18 7.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.910204
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 48.970543
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.013250
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.809524
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.546776
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.522392
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 20.24% 20.24% | 62 73.81% 94.05% | 5 5.95% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.869048
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.773810
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.671260
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.468013
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.261366
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 5.762163
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 76 25.59% 25.59% | 208 70.03% 95.62% | 13 4.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 63.612795
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297
|
||||
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -138,17 +138,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -158,9 +223,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -174,56 +239,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -237,11 +278,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -266,7 +307,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -370,7 +411,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,268 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000123 # Number of seconds simulated
|
||||
sim_ticks 122907 # Number of ticks simulated
|
||||
final_tick 122907 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000116 # Number of seconds simulated
|
||||
sim_ticks 115508 # Number of ticks simulated
|
||||
final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19204 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19202 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 419624 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 174296 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_inst_rate 2198 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2198 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45146 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435400 # Number of bytes of host memory used
|
||||
host_seconds 2.56 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1470 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1466 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 115437 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 12468 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 39.32 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
|
|
@ -26,13 +276,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 7659
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 7658
|
||||
system.ruby.latency_hist::mean 15.049491
|
||||
system.ruby.latency_hist::gmean 5.422767
|
||||
system.ruby.latency_hist::stdev 24.869733
|
||||
system.ruby.latency_hist | 6188 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 330 4.31% 85.11% | 1061 13.85% 98.97% | 77 1.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 14.083312
|
||||
system.ruby.latency_hist::gmean 5.240199
|
||||
system.ruby.latency_hist::stdev 27.247033
|
||||
system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 7658
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -41,13 +291,13 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 6188
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1470
|
||||
system.ruby.miss_latency_hist::mean 65.772109
|
||||
system.ruby.miss_latency_hist::gmean 65.537231
|
||||
system.ruby.miss_latency_hist::stdev 6.143987
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 60.738776
|
||||
system.ruby.miss_latency_hist::gmean 54.828482
|
||||
system.ruby.miss_latency_hist::stdev 34.263958
|
||||
system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1470
|
||||
system.ruby.Directory.incomplete_times 1469
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
|
|
@ -55,7 +305,7 @@ system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188
|
|||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 5.971995
|
||||
system.ruby.network.routers0.percent_links_utilized 6.354538
|
||||
system.ruby.network.routers0.msg_count.Control::2 1470
|
||||
system.ruby.network.routers0.msg_count.Data::2 1466
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1470
|
||||
|
|
@ -64,21 +314,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2936 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1470 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1466 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 854 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2108 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 2110 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.718665 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 845 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1147 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 40 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 76 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 232 7.90% 7.90% | 108 3.68% 11.58% | 64 2.18% 13.76% | 51 1.74% 15.50% | 26 0.89% 16.38% | 106 3.61% 19.99% | 20 0.68% 20.67% | 38 1.29% 21.97% | 16 0.54% 22.51% | 52 1.77% 24.28% | 138 4.70% 28.99% | 48 1.63% 30.62% | 16 0.54% 31.16% | 70 2.38% 33.55% | 30 1.02% 34.57% | 220 7.49% 42.06% | 80 2.72% 44.79% | 60 2.04% 46.83% | 80 2.72% 49.56% | 118 4.02% 53.58% | 46 1.57% 55.14% | 52 1.77% 56.91% | 84 2.86% 59.78% | 180 6.13% 65.91% | 108 3.68% 69.58% | 74 2.52% 72.10% | 140 4.77% 76.87% | 112 3.81% 80.69% | 198 6.74% 87.43% | 261 8.89% 96.32% | 40 1.36% 97.68% | 68 2.32% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2936 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 5.971995
|
||||
system.ruby.network.routers1.percent_links_utilized 6.354538
|
||||
system.ruby.network.routers1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1470
|
||||
|
|
@ -87,7 +323,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.percent_links_utilized 5.971995
|
||||
system.ruby.network.routers2.percent_links_utilized 6.354538
|
||||
system.ruby.network.routers2.msg_count.Control::2 1470
|
||||
system.ruby.network.routers2.msg_count.Data::2 1466
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1470
|
||||
|
|
@ -123,7 +359,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 122907 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 115508 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5624 # Number of instructions committed
|
||||
|
|
@ -142,7 +378,7 @@ system.cpu.num_mem_refs 2034 # nu
|
|||
system.cpu.num_load_insts 1132 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 122907 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 115508 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 883 # Number of branches fetched
|
||||
|
|
@ -181,32 +417,32 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5625 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.978504
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.361464
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.965486
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.347612
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.965486
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.347612
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
|
||||
system.ruby.network.routers1.throttle1.link_utilization 5.978504
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.361464
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.throttle0.link_utilization 5.978504
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.361464
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.965486
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.347612
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
|
||||
|
|
@ -221,13 +457,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 64
|
||||
system.ruby.LD.latency_hist::max_bucket 639
|
||||
system.ruby.LD.latency_hist::samples 1132
|
||||
system.ruby.LD.latency_hist::mean 39.690813
|
||||
system.ruby.LD.latency_hist::gmean 18.392553
|
||||
system.ruby.LD.latency_hist::stdev 30.890580
|
||||
system.ruby.LD.latency_hist | 465 41.08% 41.08% | 0 0.00% 41.08% | 0 0.00% 41.08% | 147 12.99% 54.06% | 497 43.90% 97.97% | 22 1.94% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 35.522968
|
||||
system.ruby.LD.latency_hist::gmean 16.130611
|
||||
system.ruby.LD.latency_hist::stdev 37.257775
|
||||
system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1132
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -236,21 +472,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 465
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 64
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 639
|
||||
system.ruby.LD.miss_latency_hist::samples 667
|
||||
system.ruby.LD.miss_latency_hist::mean 65.269865
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.112332
|
||||
system.ruby.LD.miss_latency_hist::stdev 5.027167
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 58.196402
|
||||
system.ruby.LD.miss_latency_hist::gmean 52.112336
|
||||
system.ruby.LD.miss_latency_hist::stdev 33.226027
|
||||
system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 667
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 901
|
||||
system.ruby.ST.latency_hist::mean 18.103219
|
||||
system.ruby.ST.latency_hist::gmean 6.303338
|
||||
system.ruby.ST.latency_hist::stdev 27.010521
|
||||
system.ruby.ST.latency_hist | 684 75.92% 75.92% | 0 0.00% 75.92% | 0 0.00% 75.92% | 46 5.11% 81.02% | 158 17.54% 98.56% | 13 1.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 15.558269
|
||||
system.ruby.ST.latency_hist::gmean 5.883337
|
||||
system.ruby.ST.latency_hist::stdev 27.738104
|
||||
system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 901
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -259,21 +495,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 684
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 217
|
||||
system.ruby.ST.miss_latency_hist::mean 65.709677
|
||||
system.ruby.ST.miss_latency_hist::gmean 65.456791
|
||||
system.ruby.ST.miss_latency_hist::stdev 6.376574
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 55.142857
|
||||
system.ruby.ST.miss_latency_hist::gmean 49.160125
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.648687
|
||||
system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 217
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 5625
|
||||
system.ruby.IFETCH.latency_hist::mean 9.601422
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.140083
|
||||
system.ruby.IFETCH.latency_hist::stdev 19.494566
|
||||
system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 0 0.00% 89.58% | 0 0.00% 89.58% | 137 2.44% 92.02% | 406 7.22% 99.24% | 42 0.75% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 9.532444
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.102291
|
||||
system.ruby.IFETCH.latency_hist::stdev 22.246367
|
||||
system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 5625
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -282,21 +518,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 5039
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 586
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 66.366894
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 66.054272
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 7.096661
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.704778
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 60.488386
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 35.064530
|
||||
system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 586
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1470
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 65.772109
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 65.537231
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 6.143987
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 60.738776
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1470
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -319,34 +555,34 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.269865
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.112332
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.027167
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.709677
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.456791
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.376574
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.366894
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.054272
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.096661
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586
|
||||
system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -135,17 +135,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -155,9 +220,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -171,56 +236,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -234,11 +275,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -263,7 +304,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -367,7 +408,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,267 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000108 # Number of seconds simulated
|
||||
sim_ticks 107952 # Number of ticks simulated
|
||||
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000096 # Number of seconds simulated
|
||||
sim_ticks 95992 # Number of ticks simulated
|
||||
final_tick 95992 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57135 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 57126 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1157488 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 168948 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 28429 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28426 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 512186 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435856 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 859404950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 859404950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 856738062 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 856738062 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716143012 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1716143012 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1289 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1285 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 37760 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 45312 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 590 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 557 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 111 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 63 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 31 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 15 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 120 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 148 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 37 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 12 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 18 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 95928 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 699 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 50 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 47 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 230 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 387.339130 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 262.668395 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 318.441590 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 45 19.57% 19.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 51 22.17% 41.74% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 39 16.96% 58.70% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 22 9.57% 68.26% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 23 10.00% 78.26% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 5 2.17% 80.43% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 12 5.22% 85.65% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 9 3.91% 89.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 24 10.43% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 230 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 43 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.186047 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.978763 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.231215 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 22 51.16% 51.16% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 14 32.56% 83.72% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 5 11.63% 95.35% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 1 2.33% 97.67% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.33% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 43 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 43 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.465116 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.435760 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.031615 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 35 81.40% 81.40% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 8746 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 22027 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 466.04 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 472.04 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 859.40 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 856.74 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.69 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 676 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 70.96 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 37.27 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 3037 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 87552 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 1035720 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 672840 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 575400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 373800 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 5229120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 3257280 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 4271616 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 2716416 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 59194044 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 56254896 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 4292400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 6870600 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 80701020 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 76248552 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 861.316185 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 813.795315 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
|
|
@ -26,13 +275,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 6759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 6759
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 6758
|
||||
system.ruby.latency_hist::mean 14.973957
|
||||
system.ruby.latency_hist::gmean 5.402086
|
||||
system.ruby.latency_hist::stdev 24.830446
|
||||
system.ruby.latency_hist | 5469 80.93% 80.93% | 0 0.00% 80.93% | 0 0.00% 80.93% | 306 4.53% 85.45% | 913 13.51% 98.96% | 68 1.01% 99.97% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 13.204202
|
||||
system.ruby.latency_hist::gmean 5.149414
|
||||
system.ruby.latency_hist::stdev 25.350800
|
||||
system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 6758
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -41,20 +290,21 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5469 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 5469
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1289
|
||||
system.ruby.miss_latency_hist::mean 65.777347
|
||||
system.ruby.miss_latency_hist::gmean 65.516328
|
||||
system.ruby.miss_latency_hist::stdev 6.536157
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 56.498836
|
||||
system.ruby.miss_latency_hist::gmean 50.965885
|
||||
system.ruby.miss_latency_hist::stdev 32.457285
|
||||
system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1289
|
||||
system.ruby.Directory.incomplete_times 1288
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 5.960983
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.703684
|
||||
system.ruby.network.routers0.msg_count.Control::2 1289
|
||||
system.ruby.network.routers0.msg_count.Data::2 1285
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1289
|
||||
|
|
@ -63,21 +313,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 5.960983
|
||||
system.ruby.network.routers1.percent_links_utilized 6.703684
|
||||
system.ruby.network.routers1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1289
|
||||
|
|
@ -86,7 +322,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.percent_links_utilized 5.960983
|
||||
system.ruby.network.routers2.percent_links_utilized 6.703684
|
||||
system.ruby.network.routers2.msg_count.Control::2 1289
|
||||
system.ruby.network.routers2.msg_count.Data::2 1285
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1289
|
||||
|
|
@ -103,9 +339,8 @@ system.ruby.network.msg_byte.Control 30936
|
|||
system.ruby.network.msg_byte.Data 277560
|
||||
system.ruby.network.msg_byte.Response_Data 278424
|
||||
system.ruby.network.msg_byte.Writeback_Control 30840
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 107952 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 95992 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
|
|
@ -123,10 +358,10 @@ system.cpu.num_fp_register_writes 0 # nu
|
|||
system.cpu.num_mem_refs 1401 # number of memory refs
|
||||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.999991 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 107951.000009 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000009 # Percentage of idle cycles
|
||||
system.cpu.num_idle_cycles 0.999990 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 95991.000010 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000010 # Percentage of idle cycles
|
||||
system.cpu.Branches 1121 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction
|
||||
|
|
@ -163,32 +398,32 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5370 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.968393
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.712018
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.953572
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.695350
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.953572
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.695350
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1289
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1285
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520
|
||||
system.ruby.network.routers1.throttle1.link_utilization 5.968393
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.712018
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.throttle0.link_utilization 5.968393
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.712018
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.953572
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.695350
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1289
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1285
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312
|
||||
|
|
@ -203,13 +438,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 715
|
||||
system.ruby.LD.latency_hist::mean 37.334266
|
||||
system.ruby.LD.latency_hist::gmean 16.405583
|
||||
system.ruby.LD.latency_hist::stdev 31.171638
|
||||
system.ruby.LD.latency_hist | 320 44.76% 44.76% | 0 0.00% 44.76% | 0 0.00% 44.76% | 105 14.69% 59.44% | 276 38.60% 98.04% | 14 1.96% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 30.928671
|
||||
system.ruby.LD.latency_hist::gmean 13.876476
|
||||
system.ruby.LD.latency_hist::stdev 34.808507
|
||||
system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00%
|
||||
system.ruby.LD.latency_hist::total 715
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -218,21 +453,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 320 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 320
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 395
|
||||
system.ruby.LD.miss_latency_hist::mean 65.149367
|
||||
system.ruby.LD.miss_latency_hist::gmean 64.977069
|
||||
system.ruby.LD.miss_latency_hist::stdev 5.269438
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 26.58% 26.58% | 276 69.87% 96.46% | 14 3.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 53.554430
|
||||
system.ruby.LD.miss_latency_hist::gmean 47.988958
|
||||
system.ruby.LD.miss_latency_hist::stdev 32.387704
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 395
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 32
|
||||
system.ruby.ST.latency_hist::max_bucket 319
|
||||
system.ruby.ST.latency_hist::samples 673
|
||||
system.ruby.ST.latency_hist::mean 20.022288
|
||||
system.ruby.ST.latency_hist::gmean 6.840248
|
||||
system.ruby.ST.latency_hist::stdev 28.682599
|
||||
system.ruby.ST.latency_hist | 494 73.40% 73.40% | 0 0.00% 73.40% | 0 0.00% 73.40% | 45 6.69% 80.09% | 117 17.38% 97.47% | 16 2.38% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 17.843982
|
||||
system.ruby.ST.latency_hist::gmean 6.493774
|
||||
system.ruby.ST.latency_hist::stdev 27.592771
|
||||
system.ruby.ST.latency_hist | 494 73.40% 73.40% | 145 21.55% 94.95% | 28 4.16% 99.11% | 1 0.15% 99.26% | 2 0.30% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 673
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -241,21 +476,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 494
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 32
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 319
|
||||
system.ruby.ST.miss_latency_hist::samples 179
|
||||
system.ruby.ST.miss_latency_hist::mean 67
|
||||
system.ruby.ST.miss_latency_hist::gmean 66.517437
|
||||
system.ruby.ST.miss_latency_hist::stdev 9.078930
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 25.14% 25.14% | 117 65.36% 90.50% | 16 8.94% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 58.810056
|
||||
system.ruby.ST.miss_latency_hist::gmean 54.709109
|
||||
system.ruby.ST.miss_latency_hist::stdev 23.983086
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 179
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 5370
|
||||
system.ruby.IFETCH.latency_hist::mean 11.364060
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.523558
|
||||
system.ruby.IFETCH.latency_hist::stdev 21.469550
|
||||
system.ruby.IFETCH.latency_hist | 4655 86.69% 86.69% | 0 0.00% 86.69% | 0 0.00% 86.69% | 156 2.91% 89.59% | 520 9.68% 99.27% | 38 0.71% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 10.262756
|
||||
system.ruby.IFETCH.latency_hist::gmean 4.383388
|
||||
system.ruby.IFETCH.latency_hist::stdev 22.342607
|
||||
system.ruby.IFETCH.latency_hist | 5246 97.69% 97.69% | 101 1.88% 99.57% | 16 0.30% 99.87% | 1 0.02% 99.89% | 5 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 5370
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -264,21 +499,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4655 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 4655
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 715
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.818182
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 65.566761
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 6.371809
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 156 21.82% 21.82% | 520 72.73% 94.55% | 38 5.31% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 57.546853
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 51.762329
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 34.218674
|
||||
system.ruby.IFETCH.miss_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 715
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1289
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 65.777347
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 65.516328
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 6.536157
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 56.498836
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 50.965885
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 32.457285
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1289
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -301,34 +536,34 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.149367
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 64.977069
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.269438
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 26.58% 26.58% | 276 69.87% 96.46% | 14 3.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.554430
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.988958
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.387704
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 67
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 66.517437
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 9.078930
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 25.14% 25.14% | 117 65.36% 90.50% | 16 8.94% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 58.810056
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 54.709109
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.983086
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.818182
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.566761
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 6.371809
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 156 21.82% 21.82% | 520 72.73% 94.55% | 38 5.31% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.546853
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715
|
||||
system.ruby.L1Cache_Controller.Load 715 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00%
|
||||
|
|
|
|||
|
|
@ -714,6 +714,7 @@ clk_domain=system.clk_domain
|
|||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -169,17 +169,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -189,9 +254,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -205,56 +270,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -268,11 +309,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=4
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -297,7 +338,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -402,7 +443,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,18 +1,266 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000122 # Number of seconds simulated
|
||||
sim_ticks 121759 # Number of ticks simulated
|
||||
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000107 # Number of seconds simulated
|
||||
sim_ticks 107237 # Number of ticks simulated
|
||||
final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 47256 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 85597 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1069027 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 179456 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 14917 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 27022 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 297251 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 452416 # Number of bytes of host memory used
|
||||
host_seconds 0.36 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 821805907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 821805907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 819418671 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 819418671 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 1641224577 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 1641224577 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 1377 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 1373 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 42624 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 45504 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 42752 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 711 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 686 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 57 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 27 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 134 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 126 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 32 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 10 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 55 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 133 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 22 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 30 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 7 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 33 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 107133 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 666 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 39 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 272 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 306.823529 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 199.088320 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 295.785748 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 71 26.10% 26.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 86 31.62% 57.72% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 34 12.50% 70.22% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 20 7.35% 77.57% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 17 6.25% 83.82% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 9 3.31% 87.13% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 11 4.04% 91.18% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 3 1.10% 92.28% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 21 7.72% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 272 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 16.121951 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 15.902045 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 3.325621 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::12-13 2 4.88% 4.88% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 18 43.90% 48.78% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 92.68% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::20-21 2 4.88% 97.56% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 16.292683 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 16.274345 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 0.813754 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 36 87.80% 87.80% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 3 7.32% 95.12% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 2 4.88% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 9844 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 22498 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3330 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 14.78 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 33.78 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 397.47 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 398.67 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 821.81 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 819.42 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 6.22 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 3.11 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 3.11 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 26.04 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 427 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 64.11 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 38.96 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
|
||||
|
|
@ -26,13 +274,13 @@ system.ruby.outstanding_req_hist::mean 1
|
|||
system.ruby.outstanding_req_hist::gmean 1
|
||||
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 8852
|
||||
system.ruby.latency_hist::bucket_size 16
|
||||
system.ruby.latency_hist::max_bucket 159
|
||||
system.ruby.latency_hist::bucket_size 64
|
||||
system.ruby.latency_hist::max_bucket 639
|
||||
system.ruby.latency_hist::samples 8852
|
||||
system.ruby.latency_hist::mean 12.754971
|
||||
system.ruby.latency_hist::gmean 4.846146
|
||||
system.ruby.latency_hist::stdev 22.865469
|
||||
system.ruby.latency_hist | 7475 84.44% 84.44% | 0 0.00% 84.44% | 0 0.00% 84.44% | 329 3.72% 88.16% | 977 11.04% 99.20% | 69 0.78% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::mean 11.114437
|
||||
system.ruby.latency_hist::gmean 4.638311
|
||||
system.ruby.latency_hist::stdev 22.978637
|
||||
system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 8852
|
||||
system.ruby.hit_latency_hist::bucket_size 1
|
||||
system.ruby.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -41,20 +289,21 @@ system.ruby.hit_latency_hist::mean 3
|
|||
system.ruby.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 7475
|
||||
system.ruby.miss_latency_hist::bucket_size 16
|
||||
system.ruby.miss_latency_hist::max_bucket 159
|
||||
system.ruby.miss_latency_hist::bucket_size 64
|
||||
system.ruby.miss_latency_hist::max_bucket 639
|
||||
system.ruby.miss_latency_hist::samples 1377
|
||||
system.ruby.miss_latency_hist::mean 65.709513
|
||||
system.ruby.miss_latency_hist::gmean 65.465397
|
||||
system.ruby.miss_latency_hist::stdev 6.315805
|
||||
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::mean 55.163399
|
||||
system.ruby.miss_latency_hist::gmean 49.389613
|
||||
system.ruby.miss_latency_hist::stdev 33.121212
|
||||
system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 1377
|
||||
system.ruby.Directory.incomplete_times 1376
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 5.646400
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.network.routers0.percent_links_utilized 6.411034
|
||||
system.ruby.network.routers0.msg_count.Control::2 1377
|
||||
system.ruby.network.routers0.msg_count.Data::2 1373
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 1377
|
||||
|
|
@ -63,21 +312,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers0.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 2750 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 1377 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 1373 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 846 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1965 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1968 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.715636 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 823 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 1044 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 33 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 65 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 160 5.82% 5.82% | 144 5.24% 11.05% | 210 7.64% 18.69% | 146 5.31% 24.00% | 196 7.13% 31.13% | 96 3.49% 34.62% | 66 2.40% 37.02% | 38 1.38% 38.40% | 22 0.80% 39.20% | 20 0.73% 39.93% | 184 6.69% 46.62% | 297 10.80% 57.42% | 71 2.58% 60.00% | 124 4.51% 64.51% | 60 2.18% 66.69% | 18 0.65% 67.35% | 84 3.05% 70.40% | 6 0.22% 70.62% | 8 0.29% 70.91% | 14 0.51% 71.42% | 92 3.35% 74.76% | 56 2.04% 76.80% | 14 0.51% 77.31% | 60 2.18% 79.49% | 34 1.24% 80.73% | 58 2.11% 82.84% | 84 3.05% 85.89% | 66 2.40% 88.29% | 42 1.53% 89.82% | 122 4.44% 94.25% | 104 3.78% 98.04% | 54 1.96% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2750 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 5.646400
|
||||
system.ruby.network.routers1.percent_links_utilized 6.411034
|
||||
system.ruby.network.routers1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 1377
|
||||
|
|
@ -86,7 +321,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016
|
|||
system.ruby.network.routers1.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.percent_links_utilized 5.646400
|
||||
system.ruby.network.routers2.percent_links_utilized 6.411034
|
||||
system.ruby.network.routers2.msg_count.Control::2 1377
|
||||
system.ruby.network.routers2.msg_count.Data::2 1373
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 1377
|
||||
|
|
@ -103,10 +338,9 @@ system.ruby.network.msg_byte.Control 33048
|
|||
system.ruby.network.msg_byte.Data 296568
|
||||
system.ruby.network.msg_byte.Response_Data 297432
|
||||
system.ruby.network.msg_byte.Writeback_Control 32952
|
||||
system.cpu.clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 16 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 121759 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 107237 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
|
|
@ -126,10 +360,10 @@ system.cpu.num_cc_register_writes 3536 # nu
|
|||
system.cpu.num_mem_refs 1988 # number of memory refs
|
||||
system.cpu.num_load_insts 1053 # Number of load instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.999992 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 121758.000008 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999992 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000008 # Percentage of idle cycles
|
||||
system.cpu.num_idle_cycles 0.999991 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000009 # Percentage of idle cycles
|
||||
system.cpu.Branches 1208 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction
|
||||
|
|
@ -166,32 +400,32 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 9748 # Class of executed instruction
|
||||
system.ruby.network.routers0.throttle0.link_utilization 5.652970
|
||||
system.ruby.network.routers0.throttle0.link_utilization 6.418494
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers0.throttle1.link_utilization 5.639829
|
||||
system.ruby.network.routers0.throttle1.link_utilization 6.403573
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.throttle0.link_utilization 5.639829
|
||||
system.ruby.network.routers1.throttle0.link_utilization 6.403573
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 1377
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 1373
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856
|
||||
system.ruby.network.routers1.throttle1.link_utilization 5.652970
|
||||
system.ruby.network.routers1.throttle1.link_utilization 6.418494
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.throttle0.link_utilization 5.652970
|
||||
system.ruby.network.routers2.throttle0.link_utilization 6.418494
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984
|
||||
system.ruby.network.routers2.throttle1.link_utilization 5.639829
|
||||
system.ruby.network.routers2.throttle1.link_utilization 6.403573
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 1377
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 1373
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016
|
||||
|
|
@ -206,13 +440,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
|
|||
system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 16
|
||||
system.ruby.LD.latency_hist::max_bucket 159
|
||||
system.ruby.LD.latency_hist::bucket_size 32
|
||||
system.ruby.LD.latency_hist::max_bucket 319
|
||||
system.ruby.LD.latency_hist::samples 1045
|
||||
system.ruby.LD.latency_hist::mean 33.084211
|
||||
system.ruby.LD.latency_hist::gmean 13.097827
|
||||
system.ruby.LD.latency_hist::stdev 31.853421
|
||||
system.ruby.LD.latency_hist | 546 52.25% 52.25% | 0 0.00% 52.25% | 0 0.00% 52.25% | 105 10.05% 62.30% | 361 34.55% 96.84% | 32 3.06% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::mean 24.819139
|
||||
system.ruby.LD.latency_hist::gmean 10.890845
|
||||
system.ruby.LD.latency_hist::stdev 28.082269
|
||||
system.ruby.LD.latency_hist | 546 52.25% 52.25% | 414 39.62% 91.87% | 77 7.37% 99.23% | 1 0.10% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 1045
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -221,21 +455,21 @@ system.ruby.LD.hit_latency_hist::mean 3
|
|||
system.ruby.LD.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 546
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 16
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 159
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 32
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 319
|
||||
system.ruby.LD.miss_latency_hist::samples 499
|
||||
system.ruby.LD.miss_latency_hist::mean 66.002004
|
||||
system.ruby.LD.miss_latency_hist::gmean 65.699964
|
||||
system.ruby.LD.miss_latency_hist::stdev 7.001864
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::mean 48.693387
|
||||
system.ruby.LD.miss_latency_hist::gmean 44.641812
|
||||
system.ruby.LD.miss_latency_hist::stdev 23.667547
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 499
|
||||
system.ruby.ST.latency_hist::bucket_size 16
|
||||
system.ruby.ST.latency_hist::max_bucket 159
|
||||
system.ruby.ST.latency_hist::bucket_size 64
|
||||
system.ruby.ST.latency_hist::max_bucket 639
|
||||
system.ruby.ST.latency_hist::samples 935
|
||||
system.ruby.ST.latency_hist::mean 20.084492
|
||||
system.ruby.ST.latency_hist::gmean 6.936580
|
||||
system.ruby.ST.latency_hist::stdev 28.187775
|
||||
system.ruby.ST.latency_hist | 681 72.83% 72.83% | 0 0.00% 72.83% | 0 0.00% 72.83% | 62 6.63% 79.47% | 177 18.93% 98.40% | 15 1.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::mean 16.765775
|
||||
system.ruby.ST.latency_hist::gmean 6.381495
|
||||
system.ruby.ST.latency_hist::stdev 28.609452
|
||||
system.ruby.ST.latency_hist | 895 95.72% 95.72% | 35 3.74% 99.47% | 1 0.11% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 935
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -244,21 +478,21 @@ system.ruby.ST.hit_latency_hist::mean 3
|
|||
system.ruby.ST.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 681
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 16
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 159
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 64
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 639
|
||||
system.ruby.ST.miss_latency_hist::samples 254
|
||||
system.ruby.ST.miss_latency_hist::mean 65.889764
|
||||
system.ruby.ST.miss_latency_hist::gmean 65.634390
|
||||
system.ruby.ST.miss_latency_hist::stdev 6.416664
|
||||
system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::mean 53.673228
|
||||
system.ruby.ST.miss_latency_hist::gmean 48.282634
|
||||
system.ruby.ST.miss_latency_hist::stdev 33.823763
|
||||
system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 254
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.latency_hist::samples 6864
|
||||
system.ruby.IFETCH.latency_hist::mean 8.663899
|
||||
system.ruby.IFETCH.latency_hist::gmean 3.967250
|
||||
system.ruby.IFETCH.latency_hist::stdev 18.008804
|
||||
system.ruby.IFETCH.latency_hist | 6241 90.92% 90.92% | 0 0.00% 90.92% | 0 0.00% 90.92% | 162 2.36% 93.28% | 438 6.38% 99.66% | 22 0.32% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::mean 8.263112
|
||||
system.ruby.IFETCH.latency_hist::gmean 3.900454
|
||||
system.ruby.IFETCH.latency_hist::stdev 20.208626
|
||||
system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 6864
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
|
||||
|
|
@ -267,20 +501,20 @@ system.ruby.IFETCH.hit_latency_hist::mean 3
|
|||
system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 6241
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 623
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 65.402889
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 65.210291
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 5.662802
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 60.987159
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 54.083768
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 37.997755
|
||||
system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 623
|
||||
system.ruby.RMW_Read.latency_hist::bucket_size 8
|
||||
system.ruby.RMW_Read.latency_hist::max_bucket 79
|
||||
system.ruby.RMW_Read.latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.latency_hist::samples 8
|
||||
system.ruby.RMW_Read.latency_hist::mean 10.750000
|
||||
system.ruby.RMW_Read.latency_hist::gmean 4.406515
|
||||
system.ruby.RMW_Read.latency_hist::stdev 21.920310
|
||||
system.ruby.RMW_Read.latency_hist::mean 6.875000
|
||||
system.ruby.RMW_Read.latency_hist::gmean 4.063647
|
||||
system.ruby.RMW_Read.latency_hist::stdev 10.960155
|
||||
system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.latency_hist::total 8
|
||||
system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
|
||||
|
|
@ -290,21 +524,21 @@ system.ruby.RMW_Read.hit_latency_hist::mean 3
|
|||
system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000
|
||||
system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.hit_latency_hist::total 7
|
||||
system.ruby.RMW_Read.miss_latency_hist::bucket_size 8
|
||||
system.ruby.RMW_Read.miss_latency_hist::max_bucket 79
|
||||
system.ruby.RMW_Read.miss_latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.miss_latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.miss_latency_hist::samples 1
|
||||
system.ruby.RMW_Read.miss_latency_hist::mean 65
|
||||
system.ruby.RMW_Read.miss_latency_hist::gmean 65.000000
|
||||
system.ruby.RMW_Read.miss_latency_hist::mean 34
|
||||
system.ruby.RMW_Read.miss_latency_hist::gmean 34.000000
|
||||
system.ruby.RMW_Read.miss_latency_hist::stdev nan
|
||||
system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.miss_latency_hist::total 1
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 16
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 159
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 1377
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 65.709513
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 65.465397
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 6.315805
|
||||
system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 329 23.89% 23.89% | 977 70.95% 94.84% | 69 5.01% 99.85% | 1 0.07% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 55.163399
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212
|
||||
system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 1377
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
|
|
@ -327,40 +561,40 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total
|
|||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 66.002004
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.699964
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 7.001864
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 21.04% 21.04% | 361 72.34% 93.39% | 32 6.41% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.693387
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.641812
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 23.667547
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.889764
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.634390
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.416664
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 62 24.41% 24.41% | 177 69.69% 94.09% | 15 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.673228
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.282634
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.823763
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.402889
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 65.210291
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 5.662802
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 162 26.00% 26.00% | 438 70.30% 96.31% | 22 3.53% 99.84% | 0 0.00% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 8
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 79
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 65
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 65.000000
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 34
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem system.funcmem
|
||||
memories=system.funcmem system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -242,17 +242,82 @@ null=false
|
|||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -262,9 +327,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=8
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -278,21 +343,21 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[19]
|
||||
responseFromDir=system.ruby.network.slave[27]
|
||||
responseToDir=system.ruby.network.master[20]
|
||||
|
|
@ -300,33 +365,8 @@ responseToDir=system.ruby.network.master[20]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -343,12 +383,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl0.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -396,12 +436,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -431,12 +472,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl1.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl1.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
|
|
@ -484,12 +525,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl1.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -519,12 +561,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl2.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl2.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
|
|
@ -572,12 +614,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl2.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -607,12 +650,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl3.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl3.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
|
|
@ -660,12 +703,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl3.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -695,12 +739,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl4.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl4.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
|
|
@ -748,12 +792,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl4.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -783,12 +828,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl5.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl5.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
|
|
@ -836,12 +881,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl5.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -871,12 +917,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl6.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl6.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
|
|
@ -924,12 +970,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl6.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -959,12 +1006,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl7.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl7.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
|
|
@ -1012,12 +1059,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl7.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -1044,9 +1092,9 @@ eventq_index=0
|
|||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -1376,7 +1424,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem system.funcmem
|
||||
memories=system.funcmem system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -242,17 +242,82 @@ null=false
|
|||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -262,9 +327,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=8
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -278,21 +343,22 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardFromDir=system.ruby.network.slave[20]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[19]
|
||||
responseFromDir=system.ruby.network.slave[19]
|
||||
responseToDir=system.ruby.network.master[20]
|
||||
|
|
@ -300,33 +366,8 @@ responseToDir=system.ruby.network.master[20]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -340,12 +381,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -386,7 +427,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -413,12 +454,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl1.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=1
|
||||
|
|
@ -459,7 +500,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl1.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -486,12 +527,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl2.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=2
|
||||
|
|
@ -532,7 +573,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl2.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -559,12 +600,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl3.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=3
|
||||
|
|
@ -605,7 +646,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl3.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -632,12 +673,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl4.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=4
|
||||
|
|
@ -678,7 +719,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl4.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -705,12 +746,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl5.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=5
|
||||
|
|
@ -751,7 +792,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl5.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -778,12 +819,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl6.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=6
|
||||
|
|
@ -824,7 +865,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl6.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -851,12 +892,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl7.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=7
|
||||
|
|
@ -897,7 +938,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl7.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -922,11 +963,11 @@ clk_domain=system.ruby.clk_domain
|
|||
cluster_id=0
|
||||
eventq_index=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[16]
|
||||
|
|
@ -1255,7 +1296,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem system.funcmem
|
||||
memories=system.funcmem system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -242,17 +242,82 @@ null=false
|
|||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -262,9 +327,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=8
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -278,7 +343,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
|
|
@ -288,16 +353,17 @@ distributed_persistent=true
|
|||
eventq_index=0
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[31]
|
||||
dmaResponseFromDir=system.ruby.network.slave[30]
|
||||
memory=system.mem_ctrls.port
|
||||
persistentFromDir=system.ruby.network.slave[29]
|
||||
persistentToDir=system.ruby.network.master[30]
|
||||
requestFromDir=system.ruby.network.slave[27]
|
||||
|
|
@ -308,33 +374,8 @@ responseToDir=system.ruby.network.master[29]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -354,13 +395,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -403,7 +444,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -436,13 +477,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl1.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=1
|
||||
|
|
@ -485,7 +526,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl1.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -518,13 +559,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl2.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=2
|
||||
|
|
@ -567,7 +608,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl2.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -600,13 +641,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl3.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=3
|
||||
|
|
@ -649,7 +690,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl3.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -682,13 +723,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl4.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=4
|
||||
|
|
@ -731,7 +772,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl4.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -764,13 +805,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl5.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=5
|
||||
|
|
@ -813,7 +854,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl5.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -846,13 +887,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl6.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=6
|
||||
|
|
@ -895,7 +936,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl6.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -928,13 +969,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl7.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=7
|
||||
|
|
@ -977,7 +1018,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl7.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -1006,9 +1047,9 @@ filtering_enabled=true
|
|||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[24]
|
||||
|
|
@ -1338,7 +1379,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem system.funcmem
|
||||
memories=system.mem_ctrls system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -242,17 +242,82 @@ null=false
|
|||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -262,9 +327,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=8
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -278,26 +343,27 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
children=directory probeFilter
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
eventq_index=0
|
||||
from_memory_controller_latency=2
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
probeFilter=system.ruby.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[19]
|
||||
dmaResponseFromDir=system.ruby.network.slave[26]
|
||||
forwardFromDir=system.ruby.network.slave[24]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[18]
|
||||
responseFromDir=system.ruby.network.slave[25]
|
||||
responseToDir=system.ruby.network.master[17]
|
||||
|
|
@ -306,33 +372,8 @@ unblockToDir=system.ruby.network.master[16]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.probeFilter]
|
||||
|
|
@ -365,11 +406,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -425,7 +466,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -456,11 +497,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl1.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
forwardToCache=system.ruby.network.master[2]
|
||||
|
|
@ -516,7 +557,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl1.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -547,11 +588,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl2.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
forwardToCache=system.ruby.network.master[4]
|
||||
|
|
@ -607,7 +648,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl2.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -638,11 +679,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl3.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
forwardToCache=system.ruby.network.master[6]
|
||||
|
|
@ -698,7 +739,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl3.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -729,11 +770,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl4.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
forwardToCache=system.ruby.network.master[8]
|
||||
|
|
@ -789,7 +830,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl4.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -820,11 +861,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl5.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
forwardToCache=system.ruby.network.master[10]
|
||||
|
|
@ -880,7 +921,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl5.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -911,11 +952,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl6.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
forwardToCache=system.ruby.network.master[12]
|
||||
|
|
@ -971,7 +1012,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl6.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -1002,11 +1043,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl7.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
forwardToCache=system.ruby.network.master[14]
|
||||
|
|
@ -1062,7 +1103,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl7.L1Dcache
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -1355,7 +1396,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem system.funcmem
|
||||
memories=system.mem_ctrls system.funcmem
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -242,17 +242,82 @@ null=false
|
|||
range=0:134217727
|
||||
port=system.funcbus.master[0]
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -262,9 +327,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=8
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
|
||||
|
|
@ -278,56 +343,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[17]
|
||||
dmaResponseFromDir=system.ruby.network.slave[17]
|
||||
forwardFromDir=system.ruby.network.slave[18]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[16]
|
||||
responseFromDir=system.ruby.network.slave[16]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -341,11 +382,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -370,7 +411,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -397,11 +438,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl1.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=1
|
||||
forwardToCache=system.ruby.network.master[2]
|
||||
|
|
@ -426,7 +467,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl1.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl1.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -453,11 +494,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl2.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=2
|
||||
forwardToCache=system.ruby.network.master[4]
|
||||
|
|
@ -482,7 +523,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl2.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl2.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -509,11 +550,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl3.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=3
|
||||
forwardToCache=system.ruby.network.master[6]
|
||||
|
|
@ -538,7 +579,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl3.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl3.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -565,11 +606,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl4.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=4
|
||||
forwardToCache=system.ruby.network.master[8]
|
||||
|
|
@ -594,7 +635,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl4.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl4.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -621,11 +662,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl5.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=5
|
||||
forwardToCache=system.ruby.network.master[10]
|
||||
|
|
@ -650,7 +691,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl5.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl5.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -677,11 +718,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl6.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=6
|
||||
forwardToCache=system.ruby.network.master[12]
|
||||
|
|
@ -706,7 +747,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl6.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl6.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -733,11 +774,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl7.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=7
|
||||
forwardToCache=system.ruby.network.master[14]
|
||||
|
|
@ -762,7 +803,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl7.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.cpu_clk_domain
|
||||
dcache=system.ruby.l1_cntrl7.cacheMemory
|
||||
deadlock_threshold=1000000
|
||||
|
|
@ -1055,7 +1096,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -64,17 +64,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -84,9 +149,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
||||
|
|
@ -100,21 +165,21 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[6]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -122,33 +187,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -165,12 +205,12 @@ l1_request_latency=2
|
|||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
prefetcher=system.ruby.l1_cntrl0.prefetcher
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -218,12 +258,13 @@ nonunit_filter=8
|
|||
num_startup_pfs=1
|
||||
num_streams=4
|
||||
pf_per_stream=1
|
||||
sys=system
|
||||
train_misses=4
|
||||
unit_filter=8
|
||||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.ruby.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -250,9 +291,9 @@ eventq_index=0
|
|||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
|
@ -393,7 +434,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -64,17 +64,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -84,9 +149,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
||||
|
|
@ -100,21 +165,22 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=6
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardFromDir=system.ruby.network.slave[6]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[5]
|
||||
responseFromDir=system.ruby.network.slave[5]
|
||||
responseToDir=system.ruby.network.master[6]
|
||||
|
|
@ -122,33 +188,8 @@ responseToDir=system.ruby.network.master[6]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -162,12 +203,12 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -208,7 +249,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.ruby.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -233,11 +274,11 @@ clk_domain=system.ruby.clk_domain
|
|||
cluster_id=0
|
||||
eventq_index=0
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[2]
|
||||
|
|
@ -377,7 +418,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -64,17 +64,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -84,9 +149,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
||||
|
|
@ -100,7 +165,7 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
|
|
@ -110,16 +175,17 @@ distributed_persistent=true
|
|||
eventq_index=0
|
||||
fixed_timeout_latency=100
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[10]
|
||||
dmaResponseFromDir=system.ruby.network.slave[9]
|
||||
memory=system.mem_ctrls.port
|
||||
persistentFromDir=system.ruby.network.slave[8]
|
||||
persistentToDir=system.ruby.network.master[9]
|
||||
requestFromDir=system.ruby.network.slave[6]
|
||||
|
|
@ -130,33 +196,8 @@ responseToDir=system.ruby.network.master[8]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -176,13 +217,13 @@ l1_response_latency=2
|
|||
l2_select_num_bits=0
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
reissue_wakeup_latency=10
|
||||
retry_threshold=1
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
use_timeout_latency=50
|
||||
version=0
|
||||
|
|
@ -225,7 +266,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.ruby.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -254,9 +295,9 @@ filtering_enabled=true
|
|||
l2_request_latency=5
|
||||
l2_response_latency=5
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
GlobalRequestFromL2Cache=system.ruby.network.slave[3]
|
||||
|
|
@ -397,7 +438,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -64,17 +64,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -84,9 +149,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
||||
|
|
@ -100,26 +165,27 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer probeFilter
|
||||
children=directory probeFilter
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
eventq_index=0
|
||||
from_memory_controller_latency=2
|
||||
full_bit_dir_enabled=false
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
memory_controller_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
probeFilter=system.ruby.dir_cntrl0.probeFilter
|
||||
probe_filter_enabled=false
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[5]
|
||||
dmaResponseFromDir=system.ruby.network.slave[5]
|
||||
forwardFromDir=system.ruby.network.slave[3]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[4]
|
||||
responseFromDir=system.ruby.network.slave[4]
|
||||
responseToDir=system.ruby.network.master[3]
|
||||
|
|
@ -128,33 +194,8 @@ unblockToDir=system.ruby.network.master[2]
|
|||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.probeFilter]
|
||||
|
|
@ -187,11 +228,11 @@ issue_latency=2
|
|||
l2_cache_hit_latency=10
|
||||
no_mig_atomic=true
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -247,7 +288,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.ruby.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.L1Dcache
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -351,7 +392,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain
|
||||
children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
|
||||
boot_osflags=a
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
|
|
@ -22,7 +22,7 @@ load_addr_mask=1099511627775
|
|||
load_offset=0
|
||||
mem_mode=timing
|
||||
mem_ranges=0:268435455
|
||||
memories=system.physmem
|
||||
memories=system.mem_ctrls
|
||||
num_work_ids=16
|
||||
readfile=
|
||||
symbolfile=
|
||||
|
|
@ -64,17 +64,82 @@ eventq_index=0
|
|||
sys_clk_domain=system.clk_domain
|
||||
transition_latency=100000
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=0.000000
|
||||
[system.mem_ctrls]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
IDD02=0.000000
|
||||
IDD2N=0.050000
|
||||
IDD2N2=0.000000
|
||||
IDD2P0=0.000000
|
||||
IDD2P02=0.000000
|
||||
IDD2P1=0.000000
|
||||
IDD2P12=0.000000
|
||||
IDD3N=0.057000
|
||||
IDD3N2=0.000000
|
||||
IDD3P0=0.000000
|
||||
IDD3P02=0.000000
|
||||
IDD3P1=0.000000
|
||||
IDD3P12=0.000000
|
||||
IDD4R=0.187000
|
||||
IDD4R2=0.000000
|
||||
IDD4W=0.165000
|
||||
IDD4W2=0.000000
|
||||
IDD5=0.220000
|
||||
IDD52=0.000000
|
||||
IDD6=0.000000
|
||||
IDD62=0.000000
|
||||
VDD=1.500000
|
||||
VDD2=0.000000
|
||||
activation_limit=4
|
||||
addr_mapping=RoRaBaChCo
|
||||
bank_groups_per_rank=0
|
||||
banks_per_rank=8
|
||||
burst_length=8
|
||||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
devices_per_rank=8
|
||||
dll=true
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=true
|
||||
range=0:134217727
|
||||
max_accesses_per_row=16
|
||||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
page_policy=open_adaptive
|
||||
range=0:268435455
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
static_backend_latency=10
|
||||
static_frontend_latency=10
|
||||
tBURST=5
|
||||
tCCD_L=0
|
||||
tCK=1
|
||||
tCL=14
|
||||
tCS=3
|
||||
tRAS=35
|
||||
tRCD=14
|
||||
tREFI=7800
|
||||
tRFC=260
|
||||
tRP=14
|
||||
tRRD=6
|
||||
tRRD_L=0
|
||||
tRTP=8
|
||||
tRTW=3
|
||||
tWR=15
|
||||
tWTR=8
|
||||
tXAW=30
|
||||
tXP=0
|
||||
tXPDLL=0
|
||||
tXS=0
|
||||
tXSDLL=0
|
||||
write_buffer_size=64
|
||||
write_high_thresh_perc=85
|
||||
write_low_thresh_perc=50
|
||||
port=system.ruby.dir_cntrl0.memory
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
|
|
@ -84,9 +149,9 @@ block_size_bytes=64
|
|||
clk_domain=system.ruby.clk_domain
|
||||
eventq_index=0
|
||||
hot_lines=false
|
||||
mem_size=268435456
|
||||
no_mem_vec=false
|
||||
memory_size_bits=48
|
||||
num_of_sequencers=1
|
||||
phys_mem=Null
|
||||
random_seed=1234
|
||||
randomization=true
|
||||
|
||||
|
|
@ -100,56 +165,32 @@ voltage_domain=system.voltage_domain
|
|||
|
||||
[system.ruby.dir_cntrl0]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
children=directory
|
||||
buffer_size=0
|
||||
clk_domain=system.ruby.clk_domain
|
||||
cluster_id=0
|
||||
directory=system.ruby.dir_cntrl0.directory
|
||||
directory_latency=12
|
||||
eventq_index=0
|
||||
memBuffer=system.ruby.dir_cntrl0.memBuffer
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
system=system
|
||||
to_memory_controller_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
dmaRequestToDir=system.ruby.network.master[3]
|
||||
dmaResponseFromDir=system.ruby.network.slave[3]
|
||||
forwardFromDir=system.ruby.network.slave[4]
|
||||
memory=system.mem_ctrls.port
|
||||
requestToDir=system.ruby.network.master[2]
|
||||
responseFromDir=system.ruby.network.slave[2]
|
||||
|
||||
[system.ruby.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
eventq_index=0
|
||||
map_levels=4
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
||||
[system.ruby.dir_cntrl0.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
clk_domain=system.ruby.memctrl_clk_domain
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
eventq_index=0
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
ruby_system=system.ruby
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.l1_cntrl0]
|
||||
|
|
@ -163,11 +204,11 @@ cluster_id=0
|
|||
eventq_index=0
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
peer=Null
|
||||
recycle_latency=10
|
||||
ruby_system=system.ruby
|
||||
send_evictions=false
|
||||
sequencer=system.ruby.l1_cntrl0.sequencer
|
||||
system=system
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
forwardToCache=system.ruby.network.master[0]
|
||||
|
|
@ -192,7 +233,7 @@ tagArrayBanks=1
|
|||
|
||||
[system.ruby.l1_cntrl0.sequencer]
|
||||
type=RubySequencer
|
||||
access_phys_mem=false
|
||||
access_backing_store=false
|
||||
clk_domain=system.ruby.clk_domain
|
||||
dcache=system.ruby.l1_cntrl0.cacheMemory
|
||||
deadlock_threshold=500000
|
||||
|
|
@ -296,7 +337,7 @@ virt_nets=10
|
|||
|
||||
[system.sys_port_proxy]
|
||||
type=RubyPortProxy
|
||||
access_phys_mem=true
|
||||
access_backing_store=false
|
||||
clk_domain=system.clk_domain
|
||||
eventq_index=0
|
||||
ruby_system=system.ruby
|
||||
|
|
|
|||
|
|
@ -1,285 +1,516 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000228 # Number of seconds simulated
|
||||
sim_ticks 228001 # Number of ticks simulated
|
||||
final_tick 228001 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000233 # Number of seconds simulated
|
||||
sim_ticks 233251 # Number of ticks simulated
|
||||
final_tick 233251 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 3675993 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 127868 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 3056189 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 433064 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 58944 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_read::total 58944 # Number of bytes read from this memory
|
||||
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 58752 # Number of bytes written to this memory
|
||||
system.mem_ctrls.bytes_written::total 58752 # Number of bytes written to this memory
|
||||
system.mem_ctrls.num_reads::ruby.dir_cntrl0 921 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_reads::total 921 # Number of read requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::ruby.dir_cntrl0 918 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.num_writes::total 918 # Number of write requests responded to by this memory
|
||||
system.mem_ctrls.bw_read::ruby.dir_cntrl0 252706312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_read::total 252706312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::ruby.dir_cntrl0 251883164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_write::total 251883164 # Write bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::ruby.dir_cntrl0 504589477 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.bw_total::total 504589477 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrls.readReqs 921 # Number of read requests accepted
|
||||
system.mem_ctrls.writeReqs 918 # Number of write requests accepted
|
||||
system.mem_ctrls.readBursts 921 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.mem_ctrls.writeBursts 918 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.mem_ctrls.bytesReadDRAM 50624 # Total number of bytes read from DRAM
|
||||
system.mem_ctrls.bytesReadWrQ 8320 # Total number of bytes read from write queue
|
||||
system.mem_ctrls.bytesWritten 49472 # Total number of bytes written to DRAM
|
||||
system.mem_ctrls.bytesReadSys 58944 # Total read bytes from the system interface side
|
||||
system.mem_ctrls.bytesWrittenSys 58752 # Total written bytes from the system interface side
|
||||
system.mem_ctrls.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue
|
||||
system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one
|
||||
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.mem_ctrls.perBankRdBursts::0 247 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::1 234 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::2 258 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::3 52 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::0 237 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::1 229 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::2 256 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::3 51 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
|
||||
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrls.totGap 232954 # Total gap between requests
|
||||
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.mem_ctrls.readPktSize::6 921 # Read request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.mem_ctrls.writePktSize::6 918 # Write request sizes (log2)
|
||||
system.mem_ctrls.rdQLenPdf::0 668 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::1 123 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::15 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::16 27 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::17 44 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::18 47 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::19 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::20 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::21 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::23 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::24 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::25 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::26 48 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::27 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::28 46 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::29 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::30 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::31 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::32 45 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.mem_ctrls.bytesPerActivate::samples 156 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::mean 632.615385 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::gmean 446.819615 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::stdev 383.170651 # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::0-127 20 12.82% 12.82% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::128-255 19 12.18% 25.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::256-383 11 7.05% 32.05% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::384-511 9 5.77% 37.82% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::512-639 10 6.41% 44.23% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::640-767 12 7.69% 51.92% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::768-895 9 5.77% 57.69% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::896-1023 10 6.41% 64.10% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::1024-1151 56 35.90% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrls.bytesPerActivate::total 156 # Bytes accessed per row activation
|
||||
system.mem_ctrls.rdPerTurnAround::samples 45 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::mean 17.311111 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::gmean 17.138581 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::stdev 2.968181 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::14-15 6 13.33% 13.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::16-17 18 40.00% 53.33% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::18-19 20 44.44% 97.78% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::34-35 1 2.22% 100.00% # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.rdPerTurnAround::total 45 # Reads before turning the bus around for writes
|
||||
system.mem_ctrls.wrPerTurnAround::samples 45 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::mean 17.177778 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::gmean 17.147333 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::stdev 1.028876 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::16 19 42.22% 42.22% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::18 25 55.56% 97.78% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::19 1 2.22% 100.00% # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.wrPerTurnAround::total 45 # Writes before turning the bus around for reads
|
||||
system.mem_ctrls.totQLat 7966 # Total ticks spent queuing
|
||||
system.mem_ctrls.totMemAccLat 22995 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrls.totBusLat 3955 # Total ticks spent in databus transfers
|
||||
system.mem_ctrls.avgQLat 10.07 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrls.avgMemAccLat 29.07 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrls.avgRdBW 217.04 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBW 212.10 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgRdBWSys 252.71 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrls.avgWrBWSys 251.88 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrls.busUtil 3.35 # Data bus utilization in percentage
|
||||
system.mem_ctrls.busUtilRead 1.70 # Data bus utilization in percentage for reads
|
||||
system.mem_ctrls.busUtilWrite 1.66 # Data bus utilization in percentage for writes
|
||||
system.mem_ctrls.avgRdQLen 1.23 # Average read queue length when enqueuing
|
||||
system.mem_ctrls.avgWrQLen 24.79 # Average write queue length when enqueuing
|
||||
system.mem_ctrls.readRowHits 638 # Number of row buffer hits during reads
|
||||
system.mem_ctrls.writeRowHits 766 # Number of row buffer hits during writes
|
||||
system.mem_ctrls.readRowHitRate 80.66 # Row buffer hit rate for reads
|
||||
system.mem_ctrls.writeRowHitRate 95.51 # Row buffer hit rate for writes
|
||||
system.mem_ctrls.avgGap 126.67 # Average gap between requests
|
||||
system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrls.memoryStateTime::IDLE 697 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::REF 7540 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT 218097 # Time in different power states
|
||||
system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrls.actEnergy::0 1171800 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::0 651000 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::0 9597120 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::0 7848576 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::0 14748240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.refreshEnergy::1 14748240 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::0 153780300 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.actBackEnergy::1 4879656 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::0 737400 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.preBackEnergy::1 131352000 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::0 188534436 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.totalEnergy::1 150979896 # Total energy per rank (pJ)
|
||||
system.mem_ctrls.averagePower::0 834.023888 # Core power per rank (mW)
|
||||
system.mem_ctrls.averagePower::1 667.893052 # Core power per rank (mW)
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 2 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 19 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1875 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.413867 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.755437 # delay histogram for all message
|
||||
system.ruby.delayHist | 1737 92.64% 92.64% | 40 2.13% 94.77% | 28 1.49% 96.27% | 28 1.49% 97.76% | 24 1.28% 99.04% | 9 0.48% 99.52% | 3 0.16% 99.68% | 1 0.05% 99.73% | 3 0.16% 99.89% | 2 0.11% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1875 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1839 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.295813 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 1.367881 # delay histogram for all message
|
||||
system.ruby.delayHist | 1732 94.18% 94.18% | 33 1.79% 95.98% | 21 1.14% 97.12% | 29 1.58% 98.69% | 15 0.82% 99.51% | 5 0.27% 99.78% | 3 0.16% 99.95% | 1 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1839 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 993
|
||||
system.ruby.outstanding_req_hist::mean 15.769386
|
||||
system.ruby.outstanding_req_hist::gmean 15.669183
|
||||
system.ruby.outstanding_req_hist::stdev 1.147486
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.91% | 2 0.20% 1.11% | 2 0.20% 1.31% | 106 10.67% 11.98% | 874 88.02% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 993
|
||||
system.ruby.outstanding_req_hist::samples 971
|
||||
system.ruby.outstanding_req_hist::mean 15.772400
|
||||
system.ruby.outstanding_req_hist::gmean 15.670098
|
||||
system.ruby.outstanding_req_hist::stdev 1.157985
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 2 0.21% 0.93% | 2 0.21% 1.13% | 2 0.21% 1.34% | 98 10.09% 11.43% | 860 88.57% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 971
|
||||
system.ruby.latency_hist::bucket_size 1024
|
||||
system.ruby.latency_hist::max_bucket 10239
|
||||
system.ruby.latency_hist::samples 978
|
||||
system.ruby.latency_hist::mean 3693.343558
|
||||
system.ruby.latency_hist::gmean 3643.123362
|
||||
system.ruby.latency_hist::stdev 533.362444
|
||||
system.ruby.latency_hist | 4 0.41% 0.41% | 4 0.41% 0.82% | 73 7.46% 8.28% | 689 70.45% 78.73% | 206 21.06% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 978
|
||||
system.ruby.latency_hist::samples 956
|
||||
system.ruby.latency_hist::mean 3857.955021
|
||||
system.ruby.latency_hist::gmean 3808.152723
|
||||
system.ruby.latency_hist::stdev 536.282596
|
||||
system.ruby.latency_hist | 4 0.42% 0.42% | 4 0.42% 0.84% | 37 3.87% 4.71% | 609 63.70% 68.41% | 298 31.17% 99.58% | 4 0.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 956
|
||||
system.ruby.hit_latency_hist::bucket_size 512
|
||||
system.ruby.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.hit_latency_hist::samples 39
|
||||
system.ruby.hit_latency_hist::mean 3214.641026
|
||||
system.ruby.hit_latency_hist::gmean 3186.126692
|
||||
system.ruby.hit_latency_hist::stdev 431.722041
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 7.69% 7.69% | 10 25.64% 33.33% | 17 43.59% 76.92% | 8 20.51% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 39
|
||||
system.ruby.hit_latency_hist::samples 35
|
||||
system.ruby.hit_latency_hist::mean 3398.942857
|
||||
system.ruby.hit_latency_hist::gmean 3374.308107
|
||||
system.ruby.hit_latency_hist::stdev 410.898796
|
||||
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.86% 2.86% | 8 22.86% 25.71% | 11 31.43% 57.14% | 14 40.00% 97.14% | 1 2.86% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 35
|
||||
system.ruby.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.miss_latency_hist::samples 939
|
||||
system.ruby.miss_latency_hist::mean 3713.225772
|
||||
system.ruby.miss_latency_hist::gmean 3663.461061
|
||||
system.ruby.miss_latency_hist::stdev 528.042705
|
||||
system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.85% | 60 6.39% 7.24% | 664 70.71% 77.96% | 205 21.83% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 939
|
||||
system.ruby.Directory.incomplete_times 939
|
||||
system.ruby.miss_latency_hist::samples 921
|
||||
system.ruby.miss_latency_hist::mean 3875.398480
|
||||
system.ruby.miss_latency_hist::gmean 3825.697233
|
||||
system.ruby.miss_latency_hist::stdev 532.898268
|
||||
system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 921
|
||||
system.ruby.Directory.incomplete_times 921
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 980 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 10 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 112 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load
|
||||
system.ruby.network.routers0.percent_links_utilized 2.055583
|
||||
system.ruby.network.routers0.msg_count.Control::2 939
|
||||
system.ruby.network.routers0.msg_count.Data::2 936
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 67392
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1875 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 939 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 936 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 1584 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1797 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 156 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 18 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 1971 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 1.051200 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 297 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 648 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 605 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 187 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 59 3.15% 3.15% | 68 3.63% 6.77% | 62 3.31% 10.08% | 78 4.16% 14.24% | 119 6.35% 20.59% | 54 2.88% 23.47% | 61 3.25% 26.72% | 54 2.88% 29.60% | 40 2.13% 31.73% | 64 3.41% 35.15% | 46 2.45% 37.60% | 60 3.20% 40.80% | 54 2.88% 43.68% | 68 3.63% 47.31% | 52 2.77% 50.08% | 44 2.35% 52.43% | 50 2.67% 55.09% | 42 2.24% 57.33% | 44 2.35% 59.68% | 64 3.41% 63.09% | 64 3.41% 66.51% | 44 2.35% 68.85% | 64 3.41% 72.27% | 52 2.77% 75.04% | 62 3.31% 78.35% | 58 3.09% 81.44% | 60 3.20% 84.64% | 56 2.99% 87.63% | 52 2.77% 90.40% | 64 3.41% 93.81% | 52 2.77% 96.59% | 64 3.41% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1875 # Number of accesses per bank
|
||||
system.ruby.network.routers1.percent_links_utilized 2.055912
|
||||
system.ruby.network.routers1.msg_count.Control::2 939
|
||||
system.ruby.network.routers1.msg_count.Data::2 936
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 67392
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.network.routers2.percent_links_utilized 2.055912
|
||||
system.ruby.network.routers2.msg_count.Control::2 939
|
||||
system.ruby.network.routers2.msg_count.Data::2 936
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 67392
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.network.msg_count.Control 2817
|
||||
system.ruby.network.msg_count.Data 2808
|
||||
system.ruby.network.msg_count.Response_Data 2817
|
||||
system.ruby.network.msg_count.Writeback_Control 2808
|
||||
system.ruby.network.msg_byte.Control 22536
|
||||
system.ruby.network.msg_byte.Data 202176
|
||||
system.ruby.network.msg_byte.Response_Data 202824
|
||||
system.ruby.network.msg_byte.Writeback_Control 22464
|
||||
system.ruby.network.routers0.throttle0.link_utilization 2.057886
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.053280
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 939
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 936
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 67392
|
||||
system.ruby.network.routers1.throttle0.link_utilization 2.053280
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 939
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 936
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 67392
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.058544
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.network.routers2.throttle0.link_utilization 2.058544
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 939
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 936
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 67608
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7488
|
||||
system.ruby.network.routers2.throttle1.link_utilization 2.053280
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 939
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 936
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7512
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 67392
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 35 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 923 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 958 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 117 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
|
||||
system.ruby.network.routers0.percent_links_utilized 1.971696
|
||||
system.ruby.network.routers0.msg_count.Control::2 921
|
||||
system.ruby.network.routers0.msg_count.Data::2 919
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 66168
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers1.percent_links_utilized 1.971053
|
||||
system.ruby.network.routers1.msg_count.Control::2 921
|
||||
system.ruby.network.routers1.msg_count.Data::2 918
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.percent_links_utilized 1.971053
|
||||
system.ruby.network.routers2.msg_count.Control::2 921
|
||||
system.ruby.network.routers2.msg_count.Data::2 918
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.msg_count.Control 2763
|
||||
system.ruby.network.msg_count.Data 2755
|
||||
system.ruby.network.msg_count.Response_Data 2763
|
||||
system.ruby.network.msg_count.Writeback_Control 2754
|
||||
system.ruby.network.msg_byte.Control 22104
|
||||
system.ruby.network.msg_byte.Data 198360
|
||||
system.ruby.network.msg_byte.Response_Data 198936
|
||||
system.ruby.network.msg_byte.Writeback_Control 22032
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.973625
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers0.throttle1.link_utilization 1.969766
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 921
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 919
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 66168
|
||||
system.ruby.network.routers1.throttle0.link_utilization 1.968480
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::2 921
|
||||
system.ruby.network.routers1.throttle0.msg_count.Data::2 918
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 66096
|
||||
system.ruby.network.routers1.throttle1.link_utilization 1.973625
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.973625
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 921
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 918
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 66312
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7344
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.968480
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 921
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 918
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7368
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 66096
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 939 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.470714 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 1.775198 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 854 90.95% 90.95% | 28 2.98% 93.93% | 18 1.92% 95.85% | 17 1.81% 97.66% | 12 1.28% 98.94% | 5 0.53% 99.47% | 3 0.32% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 939 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 921 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.408252 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 1.494373 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 839 91.10% 91.10% | 28 3.04% 94.14% | 20 2.17% 96.31% | 21 2.28% 98.59% | 9 0.98% 99.57% | 3 0.33% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 921 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 2 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 19 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 936 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.356838 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 1.734462 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 883 94.34% 94.34% | 12 1.28% 95.62% | 10 1.07% 96.69% | 11 1.18% 97.86% | 12 1.28% 99.15% | 4 0.43% 99.57% | 0 0.00% 99.57% | 0 0.00% 99.57% | 2 0.21% 99.79% | 2 0.21% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 936 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 918 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.183007 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 1.218386 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 893 97.28% 97.28% | 5 0.54% 97.82% | 1 0.11% 97.93% | 8 0.87% 98.80% | 6 0.65% 99.46% | 2 0.22% 99.67% | 2 0.22% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 918 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 512
|
||||
system.ruby.LD.latency_hist::max_bucket 5119
|
||||
system.ruby.LD.latency_hist::samples 50
|
||||
system.ruby.LD.latency_hist::mean 3717.400000
|
||||
system.ruby.LD.latency_hist::gmean 3691.585103
|
||||
system.ruby.LD.latency_hist::stdev 435.779386
|
||||
system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 4.00% 4.00% | 18 36.00% 40.00% | 20 40.00% 80.00% | 10 20.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 50
|
||||
system.ruby.LD.latency_hist::samples 46
|
||||
system.ruby.LD.latency_hist::mean 3901.739130
|
||||
system.ruby.LD.latency_hist::gmean 3880.241355
|
||||
system.ruby.LD.latency_hist::stdev 413.461724
|
||||
system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.17% 2.17% | 11 23.91% 26.09% | 18 39.13% 65.22% | 14 30.43% 95.65% | 2 4.35% 100.00%
|
||||
system.ruby.LD.latency_hist::total 46
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 512
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.hit_latency_hist::samples 2
|
||||
system.ruby.LD.hit_latency_hist::mean 2856
|
||||
system.ruby.LD.hit_latency_hist::gmean 2844.049050
|
||||
system.ruby.LD.hit_latency_hist::stdev 369.109740
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 2
|
||||
system.ruby.LD.hit_latency_hist::samples 1
|
||||
system.ruby.LD.hit_latency_hist::mean 3037
|
||||
system.ruby.LD.hit_latency_hist::gmean 3037.000000
|
||||
system.ruby.LD.hit_latency_hist::stdev nan
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 1
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 512
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.miss_latency_hist::samples 48
|
||||
system.ruby.LD.miss_latency_hist::mean 3753.291667
|
||||
system.ruby.LD.miss_latency_hist::gmean 3731.923305
|
||||
system.ruby.LD.miss_latency_hist::stdev 402.734903
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.08% 2.08% | 17 35.42% 37.50% | 20 41.67% 79.17% | 10 20.83% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 48
|
||||
system.ruby.LD.miss_latency_hist::samples 45
|
||||
system.ruby.LD.miss_latency_hist::mean 3920.955556
|
||||
system.ruby.LD.miss_latency_hist::gmean 3901.427082
|
||||
system.ruby.LD.miss_latency_hist::stdev 396.816477
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 24.44% 24.44% | 18 40.00% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 45
|
||||
system.ruby.ST.latency_hist::bucket_size 1024
|
||||
system.ruby.ST.latency_hist::max_bucket 10239
|
||||
system.ruby.ST.latency_hist::samples 878
|
||||
system.ruby.ST.latency_hist::mean 3684.186788
|
||||
system.ruby.ST.latency_hist::gmean 3631.018183
|
||||
system.ruby.ST.latency_hist::stdev 544.872418
|
||||
system.ruby.ST.latency_hist | 4 0.46% 0.46% | 4 0.46% 0.91% | 70 7.97% 8.88% | 611 69.59% 78.47% | 188 21.41% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 878
|
||||
system.ruby.ST.latency_hist::samples 856
|
||||
system.ruby.ST.latency_hist::mean 3853.304907
|
||||
system.ruby.ST.latency_hist::gmean 3800.468487
|
||||
system.ruby.ST.latency_hist::stdev 547.762073
|
||||
system.ruby.ST.latency_hist | 4 0.47% 0.47% | 4 0.47% 0.93% | 35 4.09% 5.02% | 547 63.90% 68.93% | 262 30.61% 99.53% | 4 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 856
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 512
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.ST.hit_latency_hist::samples 36
|
||||
system.ruby.ST.hit_latency_hist::mean 3222.750000
|
||||
system.ruby.ST.hit_latency_hist::gmean 3194.454829
|
||||
system.ruby.ST.hit_latency_hist::stdev 431.138120
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 8.33% 8.33% | 9 25.00% 33.33% | 16 44.44% 77.78% | 7 19.44% 97.22% | 1 2.78% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 36
|
||||
system.ruby.ST.hit_latency_hist::samples 33
|
||||
system.ruby.ST.hit_latency_hist::mean 3403.939394
|
||||
system.ruby.ST.hit_latency_hist::gmean 3378.573502
|
||||
system.ruby.ST.hit_latency_hist::stdev 417.201535
|
||||
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 7 21.21% 24.24% | 11 33.33% 57.58% | 13 39.39% 96.97% | 1 3.03% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 33
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.ST.miss_latency_hist::samples 842
|
||||
system.ruby.ST.miss_latency_hist::mean 3703.915677
|
||||
system.ruby.ST.miss_latency_hist::gmean 3650.959161
|
||||
system.ruby.ST.miss_latency_hist::stdev 540.698215
|
||||
system.ruby.ST.miss_latency_hist | 4 0.48% 0.48% | 4 0.48% 0.95% | 58 6.89% 7.84% | 588 69.83% 77.67% | 187 22.21% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 842
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 1024
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 10239
|
||||
system.ruby.IFETCH.latency_hist::samples 50
|
||||
system.ruby.IFETCH.latency_hist::mean 3830.080000
|
||||
system.ruby.IFETCH.latency_hist::gmean 3811.685277
|
||||
system.ruby.IFETCH.latency_hist::stdev 383.882042
|
||||
system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.00% 2.00% | 40 80.00% 82.00% | 8 16.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 50
|
||||
system.ruby.ST.miss_latency_hist::samples 823
|
||||
system.ruby.ST.miss_latency_hist::mean 3871.323208
|
||||
system.ruby.ST.miss_latency_hist::gmean 3818.442488
|
||||
system.ruby.ST.miss_latency_hist::stdev 544.868028
|
||||
system.ruby.ST.miss_latency_hist | 4 0.49% 0.49% | 4 0.49% 0.97% | 27 3.28% 4.25% | 523 63.55% 67.80% | 261 31.71% 99.51% | 4 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 823
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.latency_hist::samples 54
|
||||
system.ruby.IFETCH.latency_hist::mean 3894.370370
|
||||
system.ruby.IFETCH.latency_hist::gmean 3869.743086
|
||||
system.ruby.IFETCH.latency_hist::stdev 439.746423
|
||||
system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.85% 1.85% | 13 24.07% 25.93% | 20 37.04% 62.96% | 17 31.48% 94.44% | 3 5.56% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 54
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 1
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3640
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3640.000000
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 3596
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 3596.000000
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev nan
|
||||
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 1
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 49
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 3833.959184
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 3815.272105
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 386.868785
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.04% 2.04% | 39 79.59% 81.63% | 8 16.33% 97.96% | 1 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 49
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 53
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 3900
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 3875.103542
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 441.985729
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 53
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 1024
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 10239
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 939
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 3713.225772
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 3663.461061
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 528.042705
|
||||
system.ruby.Directory.miss_mach_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.85% | 60 6.39% 7.24% | 664 70.71% 77.96% | 205 21.83% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 939
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 921
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 3875.398480
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 3825.697233
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 532.898268
|
||||
system.ruby.Directory.miss_mach_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 921
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 48
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3753.291667
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3731.923305
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 402.734903
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.08% 2.08% | 17 35.42% 37.50% | 20 41.67% 79.17% | 10 20.83% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 48
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 45
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 3920.955556
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 3901.427082
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 396.816477
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 24.44% 24.44% | 18 40.00% 64.44% | 14 31.11% 95.56% | 2 4.44% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 45
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 1024
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 10239
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 842
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3703.915677
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3650.959161
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 540.698215
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 4 0.48% 0.48% | 4 0.48% 0.95% | 58 6.89% 7.84% | 588 69.83% 77.67% | 187 22.21% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 842
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 1024
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 10239
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 49
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 3833.959184
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3815.272105
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 386.868785
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.04% 2.04% | 39 79.59% 81.63% | 8 16.33% 97.96% | 1 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 49
|
||||
system.ruby.L1Cache_Controller.Load 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 880 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 939 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Replacement 938 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 936 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 49 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 844 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 823
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 3871.323208
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 3818.442488
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 544.868028
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 4 0.49% 0.49% | 4 0.49% 0.97% | 27 3.28% 4.25% | 523 63.55% 67.80% | 261 31.71% 99.51% | 4 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 823
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 53
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 3900
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3875.103542
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 441.985729
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00%
|
||||
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53
|
||||
system.ruby.L1Cache_Controller.Load 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 857 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data 921 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Replacement 920 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack 918 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 45 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 54 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 824 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 36 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement 938 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 936 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 97 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data 842 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 939 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 936 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 939 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 936 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 939 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 936 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 939 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 936 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement 920 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack 918 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data 98 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data 823 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue