1862 lines
41 KiB
INI
1862 lines
41 KiB
INI
[root]
|
|
type=Root
|
|
children=system
|
|
eventq_index=0
|
|
full_system=true
|
|
sim_quantum=0
|
|
time_sync_enable=false
|
|
time_sync_period=100000000000
|
|
time_sync_spin_threshold=100000000
|
|
|
|
[system]
|
|
type=LinuxX86System
|
|
children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus mem_ctrls pc ruby smbios_table sys_port_proxy voltage_domain
|
|
acpi_description_table_pointer=system.acpi_description_table_pointer
|
|
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
|
|
cache_line_size=64
|
|
clk_domain=system.clk_domain
|
|
e820_table=system.e820_table
|
|
eventq_index=0
|
|
init_param=0
|
|
intel_mp_pointer=system.intel_mp_pointer
|
|
intel_mp_table=system.intel_mp_table
|
|
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
|
|
kernel_addr_check=true
|
|
load_addr_mask=18446744073709551615
|
|
load_offset=0
|
|
mem_mode=timing
|
|
mem_ranges=0:134217727
|
|
memories=system.mem_ctrls
|
|
num_work_ids=16
|
|
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
|
|
smbios_table=system.smbios_table
|
|
symbolfile=
|
|
work_begin_ckpt_count=0
|
|
work_begin_cpu_id_exit=-1
|
|
work_begin_exit_count=0
|
|
work_cpus_ckpt_count=0
|
|
work_end_ckpt_count=0
|
|
work_end_exit_count=0
|
|
work_item_id=-1
|
|
system_port=system.sys_port_proxy.slave[0]
|
|
|
|
[system.acpi_description_table_pointer]
|
|
type=X86ACPIRSDP
|
|
children=xsdt
|
|
eventq_index=0
|
|
oem_id=
|
|
revision=2
|
|
rsdt=Null
|
|
xsdt=system.acpi_description_table_pointer.xsdt
|
|
|
|
[system.acpi_description_table_pointer.xsdt]
|
|
type=X86ACPIXSDT
|
|
creator_id=
|
|
creator_revision=0
|
|
entries=
|
|
eventq_index=0
|
|
oem_id=
|
|
oem_revision=0
|
|
oem_table_id=
|
|
|
|
[system.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=1000
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.cpu0]
|
|
type=TimingSimpleCPU
|
|
children=apic_clk_domain dtb interrupts isa itb tracer
|
|
branchPred=Null
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
cpu_id=0
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu0.dtb
|
|
eventq_index=0
|
|
function_trace=false
|
|
function_trace_start=0
|
|
interrupts=system.cpu0.interrupts
|
|
isa=system.cpu0.isa
|
|
itb=system.cpu0.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
numThreads=1
|
|
profile=0
|
|
progress_interval=0
|
|
simpoint_start_insts=
|
|
socket_id=0
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu0.tracer
|
|
workload=
|
|
dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
|
|
icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
|
|
|
|
[system.cpu0.apic_clk_domain]
|
|
type=DerivedClockDomain
|
|
clk_divider=16
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
|
|
[system.cpu0.dtb]
|
|
type=X86TLB
|
|
children=walker
|
|
eventq_index=0
|
|
size=64
|
|
walker=system.cpu0.dtb.walker
|
|
|
|
[system.cpu0.dtb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.ruby.l1_cntrl0.sequencer.slave[3]
|
|
|
|
[system.cpu0.interrupts]
|
|
type=X86LocalApic
|
|
clk_domain=system.cpu0.apic_clk_domain
|
|
eventq_index=0
|
|
int_latency=1000
|
|
pio_addr=2305843009213693952
|
|
pio_latency=100000
|
|
system=system
|
|
int_master=system.ruby.l1_cntrl0.sequencer.slave[4]
|
|
int_slave=system.ruby.l1_cntrl0.sequencer.master[1]
|
|
pio=system.ruby.l1_cntrl0.sequencer.master[0]
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|
|
|
[system.cpu0.isa]
|
|
type=X86ISA
|
|
eventq_index=0
|
|
|
|
[system.cpu0.itb]
|
|
type=X86TLB
|
|
children=walker
|
|
eventq_index=0
|
|
size=64
|
|
walker=system.cpu0.itb.walker
|
|
|
|
[system.cpu0.itb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.ruby.l1_cntrl0.sequencer.slave[2]
|
|
|
|
[system.cpu0.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu1]
|
|
type=TimingSimpleCPU
|
|
children=apic_clk_domain dtb interrupts isa itb tracer
|
|
branchPred=Null
|
|
checker=Null
|
|
clk_domain=system.cpu_clk_domain
|
|
cpu_id=1
|
|
do_checkpoint_insts=true
|
|
do_quiesce=true
|
|
do_statistics_insts=true
|
|
dtb=system.cpu1.dtb
|
|
eventq_index=0
|
|
function_trace=false
|
|
function_trace_start=0
|
|
interrupts=system.cpu1.interrupts
|
|
isa=system.cpu1.isa
|
|
itb=system.cpu1.itb
|
|
max_insts_all_threads=0
|
|
max_insts_any_thread=0
|
|
max_loads_all_threads=0
|
|
max_loads_any_thread=0
|
|
numThreads=1
|
|
profile=0
|
|
progress_interval=0
|
|
simpoint_start_insts=
|
|
socket_id=0
|
|
switched_out=false
|
|
system=system
|
|
tracer=system.cpu1.tracer
|
|
workload=
|
|
dcache_port=system.ruby.l1_cntrl1.sequencer.slave[1]
|
|
icache_port=system.ruby.l1_cntrl1.sequencer.slave[0]
|
|
|
|
[system.cpu1.apic_clk_domain]
|
|
type=DerivedClockDomain
|
|
clk_divider=16
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
|
|
[system.cpu1.dtb]
|
|
type=X86TLB
|
|
children=walker
|
|
eventq_index=0
|
|
size=64
|
|
walker=system.cpu1.dtb.walker
|
|
|
|
[system.cpu1.dtb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.ruby.l1_cntrl1.sequencer.slave[3]
|
|
|
|
[system.cpu1.interrupts]
|
|
type=X86LocalApic
|
|
clk_domain=system.cpu1.apic_clk_domain
|
|
eventq_index=0
|
|
int_latency=1000
|
|
pio_addr=2305843009213693952
|
|
pio_latency=100000
|
|
system=system
|
|
int_master=system.ruby.l1_cntrl1.sequencer.slave[4]
|
|
int_slave=system.ruby.l1_cntrl1.sequencer.master[1]
|
|
pio=system.ruby.l1_cntrl1.sequencer.master[0]
|
|
|
|
[system.cpu1.isa]
|
|
type=X86ISA
|
|
eventq_index=0
|
|
|
|
[system.cpu1.itb]
|
|
type=X86TLB
|
|
children=walker
|
|
eventq_index=0
|
|
size=64
|
|
walker=system.cpu1.itb.walker
|
|
|
|
[system.cpu1.itb.walker]
|
|
type=X86PagetableWalker
|
|
clk_domain=system.cpu_clk_domain
|
|
eventq_index=0
|
|
num_squash_per_cycle=4
|
|
system=system
|
|
port=system.ruby.l1_cntrl1.sequencer.slave[2]
|
|
|
|
[system.cpu1.tracer]
|
|
type=ExeTracer
|
|
eventq_index=0
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.dvfs_handler]
|
|
type=DVFSHandler
|
|
domains=
|
|
enable=false
|
|
eventq_index=0
|
|
sys_clk_domain=system.clk_domain
|
|
transition_latency=100000000
|
|
|
|
[system.e820_table]
|
|
type=X86E820Table
|
|
children=entries0 entries1 entries2 entries3 entries4
|
|
entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
|
|
eventq_index=0
|
|
|
|
[system.e820_table.entries0]
|
|
type=X86E820Entry
|
|
addr=0
|
|
eventq_index=0
|
|
range_type=1
|
|
size=654336
|
|
|
|
[system.e820_table.entries1]
|
|
type=X86E820Entry
|
|
addr=654336
|
|
eventq_index=0
|
|
range_type=2
|
|
size=394240
|
|
|
|
[system.e820_table.entries2]
|
|
type=X86E820Entry
|
|
addr=1048576
|
|
eventq_index=0
|
|
range_type=1
|
|
size=133169152
|
|
|
|
[system.e820_table.entries3]
|
|
type=X86E820Entry
|
|
addr=134217728
|
|
eventq_index=0
|
|
range_type=2
|
|
size=3087007744
|
|
|
|
[system.e820_table.entries4]
|
|
type=X86E820Entry
|
|
addr=4294901760
|
|
eventq_index=0
|
|
range_type=2
|
|
size=65536
|
|
|
|
[system.intel_mp_pointer]
|
|
type=X86IntelMPFloatingPointer
|
|
default_config=0
|
|
eventq_index=0
|
|
imcr_present=true
|
|
spec_rev=4
|
|
|
|
[system.intel_mp_table]
|
|
type=X86IntelMPConfigTable
|
|
children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries
|
|
base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 system.intel_mp_table.base_entries33
|
|
eventq_index=0
|
|
ext_entries=system.intel_mp_table.ext_entries
|
|
local_apic=4276092928
|
|
oem_id=
|
|
oem_table_addr=0
|
|
oem_table_size=0
|
|
product_id=
|
|
spec_rev=4
|
|
|
|
[system.intel_mp_table.base_entries00]
|
|
type=X86IntelMPProcessor
|
|
bootstrap=true
|
|
enable=true
|
|
eventq_index=0
|
|
family=0
|
|
feature_flags=0
|
|
local_apic_id=0
|
|
local_apic_version=20
|
|
model=0
|
|
stepping=0
|
|
|
|
[system.intel_mp_table.base_entries01]
|
|
type=X86IntelMPProcessor
|
|
bootstrap=false
|
|
enable=true
|
|
eventq_index=0
|
|
family=0
|
|
feature_flags=0
|
|
local_apic_id=1
|
|
local_apic_version=20
|
|
model=0
|
|
stepping=0
|
|
|
|
[system.intel_mp_table.base_entries02]
|
|
type=X86IntelMPIOAPIC
|
|
address=4273995776
|
|
enable=true
|
|
eventq_index=0
|
|
id=2
|
|
version=17
|
|
|
|
[system.intel_mp_table.base_entries03]
|
|
type=X86IntelMPBus
|
|
bus_id=0
|
|
bus_type=PCI
|
|
eventq_index=0
|
|
|
|
[system.intel_mp_table.base_entries04]
|
|
type=X86IntelMPBus
|
|
bus_id=1
|
|
bus_type=ISA
|
|
eventq_index=0
|
|
|
|
[system.intel_mp_table.base_entries05]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=16
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=0
|
|
source_bus_irq=16
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries06]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=0
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries07]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=2
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=0
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries08]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=1
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries09]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=1
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=1
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries10]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=3
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries11]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=3
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=3
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries12]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=4
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries13]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=4
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=4
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries14]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=5
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries15]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=5
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=5
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries16]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=6
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries17]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=6
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=6
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries18]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=7
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries19]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=7
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=7
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries20]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=8
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries21]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=8
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=8
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries22]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=9
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries23]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=9
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=9
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries24]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=10
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries25]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=10
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=10
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries26]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=11
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries27]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=11
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=11
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries28]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=12
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries29]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=12
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=12
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries30]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=13
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries31]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=13
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=13
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries32]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=0
|
|
eventq_index=0
|
|
interrupt_type=ExtInt
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=14
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.base_entries33]
|
|
type=X86IntelMPIOIntAssignment
|
|
dest_io_apic_id=2
|
|
dest_io_apic_intin=14
|
|
eventq_index=0
|
|
interrupt_type=INT
|
|
polarity=ConformPolarity
|
|
source_bus_id=1
|
|
source_bus_irq=14
|
|
trigger=ConformTrigger
|
|
|
|
[system.intel_mp_table.ext_entries]
|
|
type=X86IntelMPBusHierarchy
|
|
bus_id=1
|
|
eventq_index=0
|
|
parent_bus=0
|
|
subtractive_decode=true
|
|
|
|
[system.intrctrl]
|
|
type=IntrControl
|
|
eventq_index=0
|
|
sys=system
|
|
|
|
[system.iobus]
|
|
type=NoncoherentXBar
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
header_cycles=1
|
|
use_default_range=false
|
|
width=8
|
|
default=system.pc.pciconfig.pio
|
|
master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
|
|
slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
|
|
|
|
[system.mem_ctrls]
|
|
type=DRAMCtrl
|
|
IDD0=0.075000
|
|
IDD02=0.000000
|
|
IDD2N=0.050000
|
|
IDD2N2=0.000000
|
|
IDD2P0=0.000000
|
|
IDD2P02=0.000000
|
|
IDD2P1=0.000000
|
|
IDD2P12=0.000000
|
|
IDD3N=0.057000
|
|
IDD3N2=0.000000
|
|
IDD3P0=0.000000
|
|
IDD3P02=0.000000
|
|
IDD3P1=0.000000
|
|
IDD3P12=0.000000
|
|
IDD4R=0.187000
|
|
IDD4R2=0.000000
|
|
IDD4W=0.165000
|
|
IDD4W2=0.000000
|
|
IDD5=0.220000
|
|
IDD52=0.000000
|
|
IDD6=0.000000
|
|
IDD62=0.000000
|
|
VDD=1.500000
|
|
VDD2=0.000000
|
|
activation_limit=4
|
|
addr_mapping=RoRaBaChCo
|
|
bank_groups_per_rank=0
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
device_size=536870912
|
|
devices_per_rank=8
|
|
dll=true
|
|
eventq_index=0
|
|
in_addr_map=true
|
|
max_accesses_per_row=16
|
|
mem_sched_policy=frfcfs
|
|
min_writes_per_switch=16
|
|
null=false
|
|
page_policy=open_adaptive
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCCD_L=0
|
|
tCK=1250
|
|
tCL=13750
|
|
tCS=2500
|
|
tRAS=35000
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=260000
|
|
tRP=13750
|
|
tRRD=6000
|
|
tRRD_L=0
|
|
tRTP=7500
|
|
tRTW=2500
|
|
tWR=15000
|
|
tWTR=7500
|
|
tXAW=30000
|
|
tXP=0
|
|
tXPDLL=0
|
|
tXS=0
|
|
tXSDLL=0
|
|
write_buffer_size=64
|
|
write_high_thresh_perc=85
|
|
write_low_thresh_perc=50
|
|
port=system.ruby.dir_cntrl0.memory
|
|
|
|
[system.pc]
|
|
type=Pc
|
|
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
|
|
eventq_index=0
|
|
intrctrl=system.intrctrl
|
|
system=system
|
|
|
|
[system.pc.behind_pci]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854779128
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[11]
|
|
|
|
[system.pc.com_1]
|
|
type=Uart8250
|
|
children=terminal
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=9223372036854776824
|
|
pio_latency=100000
|
|
platform=system.pc
|
|
system=system
|
|
terminal=system.pc.com_1.terminal
|
|
pio=system.iobus.master[12]
|
|
|
|
[system.pc.com_1.terminal]
|
|
type=Terminal
|
|
eventq_index=0
|
|
intr_control=system.intrctrl
|
|
number=0
|
|
output=true
|
|
port=3456
|
|
|
|
[system.pc.fake_com_2]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854776568
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[13]
|
|
|
|
[system.pc.fake_com_3]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854776808
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[14]
|
|
|
|
[system.pc.fake_com_4]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854776552
|
|
pio_latency=100000
|
|
pio_size=8
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[15]
|
|
|
|
[system.pc.fake_floppy]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854776818
|
|
pio_latency=100000
|
|
pio_size=2
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[16]
|
|
|
|
[system.pc.i_dont_exist]
|
|
type=IsaFake
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
fake_mem=false
|
|
pio_addr=9223372036854775936
|
|
pio_latency=100000
|
|
pio_size=1
|
|
ret_bad_addr=false
|
|
ret_data16=65535
|
|
ret_data32=4294967295
|
|
ret_data64=18446744073709551615
|
|
ret_data8=255
|
|
system=system
|
|
update_data=false
|
|
warn_access=
|
|
pio=system.iobus.master[10]
|
|
|
|
[system.pc.pciconfig]
|
|
type=PciConfigAll
|
|
bus=0
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=0
|
|
pio_latency=30000
|
|
platform=system.pc
|
|
size=16777216
|
|
system=system
|
|
pio=system.iobus.default
|
|
|
|
[system.pc.south_bridge]
|
|
type=SouthBridge
|
|
children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
|
|
cmos=system.pc.south_bridge.cmos
|
|
dma1=system.pc.south_bridge.dma1
|
|
eventq_index=0
|
|
io_apic=system.pc.south_bridge.io_apic
|
|
keyboard=system.pc.south_bridge.keyboard
|
|
pic1=system.pc.south_bridge.pic1
|
|
pic2=system.pc.south_bridge.pic2
|
|
pit=system.pc.south_bridge.pit
|
|
platform=system.pc
|
|
speaker=system.pc.south_bridge.speaker
|
|
|
|
[system.pc.south_bridge.cmos]
|
|
type=Cmos
|
|
children=int_pin
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
int_pin=system.pc.south_bridge.cmos.int_pin
|
|
pio_addr=9223372036854775920
|
|
pio_latency=100000
|
|
system=system
|
|
time=Sun Jan 1 00:00:00 2012
|
|
pio=system.iobus.master[0]
|
|
|
|
[system.pc.south_bridge.cmos.int_pin]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.dma1]
|
|
type=I8237
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
pio_addr=9223372036854775808
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[1]
|
|
|
|
[system.pc.south_bridge.ide]
|
|
type=IdeController
|
|
children=disks0 disks1
|
|
BAR0=496
|
|
BAR0LegacyIO=true
|
|
BAR0Size=8
|
|
BAR1=1012
|
|
BAR1LegacyIO=true
|
|
BAR1Size=3
|
|
BAR2=368
|
|
BAR2LegacyIO=true
|
|
BAR2Size=8
|
|
BAR3=884
|
|
BAR3LegacyIO=true
|
|
BAR3Size=3
|
|
BAR4=1
|
|
BAR4LegacyIO=false
|
|
BAR4Size=16
|
|
BAR5=1
|
|
BAR5LegacyIO=false
|
|
BAR5Size=0
|
|
BIST=0
|
|
CacheLineSize=0
|
|
CapabilityPtr=0
|
|
CardbusCIS=0
|
|
ClassCode=1
|
|
Command=0
|
|
DeviceID=28945
|
|
ExpansionROM=0
|
|
HeaderType=0
|
|
InterruptLine=14
|
|
InterruptPin=1
|
|
LatencyTimer=0
|
|
LegacyIOBase=9223372036854775808
|
|
MSICAPBaseOffset=0
|
|
MSICAPCapId=0
|
|
MSICAPMaskBits=0
|
|
MSICAPMsgAddr=0
|
|
MSICAPMsgCtrl=0
|
|
MSICAPMsgData=0
|
|
MSICAPMsgUpperAddr=0
|
|
MSICAPNextCapability=0
|
|
MSICAPPendingBits=0
|
|
MSIXCAPBaseOffset=0
|
|
MSIXCAPCapId=0
|
|
MSIXCAPNextCapability=0
|
|
MSIXMsgCtrl=0
|
|
MSIXPbaOffset=0
|
|
MSIXTableOffset=0
|
|
MaximumLatency=0
|
|
MinimumGrant=0
|
|
PMCAPBaseOffset=0
|
|
PMCAPCapId=0
|
|
PMCAPCapabilities=0
|
|
PMCAPCtrlStatus=0
|
|
PMCAPNextCapability=0
|
|
PXCAPBaseOffset=0
|
|
PXCAPCapId=0
|
|
PXCAPCapabilities=0
|
|
PXCAPDevCap2=0
|
|
PXCAPDevCapabilities=0
|
|
PXCAPDevCtrl=0
|
|
PXCAPDevCtrl2=0
|
|
PXCAPDevStatus=0
|
|
PXCAPLinkCap=0
|
|
PXCAPLinkCtrl=0
|
|
PXCAPLinkStatus=0
|
|
PXCAPNextCapability=0
|
|
ProgIF=128
|
|
Revision=0
|
|
Status=640
|
|
SubClassCode=1
|
|
SubsystemID=0
|
|
SubsystemVendorID=0
|
|
VendorID=32902
|
|
clk_domain=system.clk_domain
|
|
config_latency=20000
|
|
ctrl_offset=0
|
|
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
|
|
eventq_index=0
|
|
io_shift=0
|
|
pci_bus=0
|
|
pci_dev=4
|
|
pci_func=0
|
|
pio_latency=30000
|
|
platform=system.pc
|
|
system=system
|
|
config=system.iobus.master[3]
|
|
dma=system.ruby.dma_cntrl0.dma_sequencer.slave
|
|
pio=system.iobus.master[2]
|
|
|
|
[system.pc.south_bridge.ide.disks0]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.pc.south_bridge.ide.disks0.image
|
|
|
|
[system.pc.south_bridge.ide.disks0.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.pc.south_bridge.ide.disks0.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.pc.south_bridge.ide.disks0.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
|
|
read_only=true
|
|
|
|
[system.pc.south_bridge.ide.disks1]
|
|
type=IdeDisk
|
|
children=image
|
|
delay=1000000
|
|
driveID=master
|
|
eventq_index=0
|
|
image=system.pc.south_bridge.ide.disks1.image
|
|
|
|
[system.pc.south_bridge.ide.disks1.image]
|
|
type=CowDiskImage
|
|
children=child
|
|
child=system.pc.south_bridge.ide.disks1.image.child
|
|
eventq_index=0
|
|
image_file=
|
|
read_only=false
|
|
table_size=65536
|
|
|
|
[system.pc.south_bridge.ide.disks1.image.child]
|
|
type=RawDiskImage
|
|
eventq_index=0
|
|
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
|
|
read_only=true
|
|
|
|
[system.pc.south_bridge.int_lines0]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines0.sink
|
|
source=system.pc.south_bridge.pic1.output
|
|
|
|
[system.pc.south_bridge.int_lines0.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.io_apic
|
|
eventq_index=0
|
|
number=0
|
|
|
|
[system.pc.south_bridge.int_lines1]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines1.sink
|
|
source=system.pc.south_bridge.pic2.output
|
|
|
|
[system.pc.south_bridge.int_lines1.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.pic1
|
|
eventq_index=0
|
|
number=2
|
|
|
|
[system.pc.south_bridge.int_lines2]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines2.sink
|
|
source=system.pc.south_bridge.cmos.int_pin
|
|
|
|
[system.pc.south_bridge.int_lines2.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.pic2
|
|
eventq_index=0
|
|
number=0
|
|
|
|
[system.pc.south_bridge.int_lines3]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines3.sink
|
|
source=system.pc.south_bridge.pit.int_pin
|
|
|
|
[system.pc.south_bridge.int_lines3.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.pic1
|
|
eventq_index=0
|
|
number=0
|
|
|
|
[system.pc.south_bridge.int_lines4]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines4.sink
|
|
source=system.pc.south_bridge.pit.int_pin
|
|
|
|
[system.pc.south_bridge.int_lines4.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.io_apic
|
|
eventq_index=0
|
|
number=2
|
|
|
|
[system.pc.south_bridge.int_lines5]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines5.sink
|
|
source=system.pc.south_bridge.keyboard.keyboard_int_pin
|
|
|
|
[system.pc.south_bridge.int_lines5.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.io_apic
|
|
eventq_index=0
|
|
number=1
|
|
|
|
[system.pc.south_bridge.int_lines6]
|
|
type=X86IntLine
|
|
children=sink
|
|
eventq_index=0
|
|
sink=system.pc.south_bridge.int_lines6.sink
|
|
source=system.pc.south_bridge.keyboard.mouse_int_pin
|
|
|
|
[system.pc.south_bridge.int_lines6.sink]
|
|
type=X86IntSinkPin
|
|
device=system.pc.south_bridge.io_apic
|
|
eventq_index=0
|
|
number=12
|
|
|
|
[system.pc.south_bridge.io_apic]
|
|
type=I82094AA
|
|
apic_id=2
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
external_int_pic=system.pc.south_bridge.pic1
|
|
int_latency=1000
|
|
pio_addr=4273995776
|
|
pio_latency=100000
|
|
system=system
|
|
int_master=system.iobus.slave[0]
|
|
pio=system.iobus.master[9]
|
|
|
|
[system.pc.south_bridge.keyboard]
|
|
type=I8042
|
|
children=keyboard_int_pin mouse_int_pin
|
|
clk_domain=system.clk_domain
|
|
command_port=9223372036854775908
|
|
data_port=9223372036854775904
|
|
eventq_index=0
|
|
keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
|
|
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
|
|
pio_addr=0
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[4]
|
|
|
|
[system.pc.south_bridge.keyboard.keyboard_int_pin]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.keyboard.mouse_int_pin]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.pic1]
|
|
type=I8259
|
|
children=output
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
mode=I8259Master
|
|
output=system.pc.south_bridge.pic1.output
|
|
pio_addr=9223372036854775840
|
|
pio_latency=100000
|
|
slave=system.pc.south_bridge.pic2
|
|
system=system
|
|
pio=system.iobus.master[5]
|
|
|
|
[system.pc.south_bridge.pic1.output]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.pic2]
|
|
type=I8259
|
|
children=output
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
mode=I8259Slave
|
|
output=system.pc.south_bridge.pic2.output
|
|
pio_addr=9223372036854775968
|
|
pio_latency=100000
|
|
slave=Null
|
|
system=system
|
|
pio=system.iobus.master[6]
|
|
|
|
[system.pc.south_bridge.pic2.output]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.pit]
|
|
type=I8254
|
|
children=int_pin
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
int_pin=system.pc.south_bridge.pit.int_pin
|
|
pio_addr=9223372036854775872
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[7]
|
|
|
|
[system.pc.south_bridge.pit.int_pin]
|
|
type=X86IntSourcePin
|
|
eventq_index=0
|
|
|
|
[system.pc.south_bridge.speaker]
|
|
type=PcSpeaker
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
i8254=system.pc.south_bridge.pit
|
|
pio_addr=9223372036854775905
|
|
pio_latency=100000
|
|
system=system
|
|
pio=system.iobus.master[8]
|
|
|
|
[system.ruby]
|
|
type=RubySystem
|
|
children=clk_domain dir_cntrl0 dma_cntrl0 io_controller l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network
|
|
all_instructions=false
|
|
block_size_bytes=64
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
hot_lines=false
|
|
memory_size_bits=48
|
|
num_of_sequencers=2
|
|
phys_mem=Null
|
|
random_seed=1234
|
|
randomization=false
|
|
|
|
[system.ruby.clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
domain_id=-1
|
|
eventq_index=0
|
|
init_perf_level=0
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.ruby.dir_cntrl0]
|
|
type=Directory_Controller
|
|
children=directory
|
|
buffer_size=0
|
|
clk_domain=system.ruby.clk_domain
|
|
cluster_id=0
|
|
directory=system.ruby.dir_cntrl0.directory
|
|
directory_latency=6
|
|
eventq_index=0
|
|
number_of_TBEs=256
|
|
recycle_latency=10
|
|
ruby_system=system.ruby
|
|
system=system
|
|
to_mem_ctrl_latency=1
|
|
transitions_per_cycle=4
|
|
version=0
|
|
memory=system.mem_ctrls.port
|
|
requestToDir=system.ruby.network.master[7]
|
|
responseFromDir=system.ruby.network.slave[9]
|
|
responseToDir=system.ruby.network.master[8]
|
|
|
|
[system.ruby.dir_cntrl0.directory]
|
|
type=RubyDirectoryMemory
|
|
eventq_index=0
|
|
numa_high_bit=5
|
|
size=134217728
|
|
version=0
|
|
|
|
[system.ruby.dma_cntrl0]
|
|
type=DMA_Controller
|
|
children=dma_sequencer
|
|
buffer_size=0
|
|
clk_domain=system.ruby.clk_domain
|
|
cluster_id=0
|
|
dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
|
|
eventq_index=0
|
|
number_of_TBEs=256
|
|
recycle_latency=10
|
|
request_latency=6
|
|
ruby_system=system.ruby
|
|
system=system
|
|
transitions_per_cycle=4
|
|
version=0
|
|
requestToDir=system.ruby.network.slave[10]
|
|
responseFromDir=system.ruby.network.master[9]
|
|
|
|
[system.ruby.dma_cntrl0.dma_sequencer]
|
|
type=DMASequencer
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
ruby_system=system.ruby
|
|
system=system
|
|
using_ruby_tester=false
|
|
version=0
|
|
slave=system.pc.south_bridge.ide.dma
|
|
|
|
[system.ruby.io_controller]
|
|
type=DMA_Controller
|
|
children=dma_sequencer
|
|
buffer_size=0
|
|
clk_domain=system.ruby.clk_domain
|
|
cluster_id=0
|
|
dma_sequencer=system.ruby.io_controller.dma_sequencer
|
|
eventq_index=0
|
|
number_of_TBEs=256
|
|
recycle_latency=10
|
|
request_latency=6
|
|
ruby_system=system.ruby
|
|
system=system
|
|
transitions_per_cycle=32
|
|
version=1
|
|
requestToDir=system.ruby.network.slave[11]
|
|
responseFromDir=system.ruby.network.master[10]
|
|
|
|
[system.ruby.io_controller.dma_sequencer]
|
|
type=DMASequencer
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
ruby_system=system.ruby
|
|
system=system
|
|
using_ruby_tester=false
|
|
version=1
|
|
slave=system.iobus.master[19]
|
|
|
|
[system.ruby.l1_cntrl0]
|
|
type=L1Cache_Controller
|
|
children=L1Dcache L1Icache prefetcher sequencer
|
|
L1Dcache=system.ruby.l1_cntrl0.L1Dcache
|
|
L1Icache=system.ruby.l1_cntrl0.L1Icache
|
|
buffer_size=0
|
|
clk_domain=system.cpu_clk_domain
|
|
cluster_id=0
|
|
enable_prefetch=false
|
|
eventq_index=0
|
|
l1_request_latency=2
|
|
l1_response_latency=2
|
|
l2_select_num_bits=0
|
|
number_of_TBEs=256
|
|
prefetcher=system.ruby.l1_cntrl0.prefetcher
|
|
recycle_latency=10
|
|
ruby_system=system.ruby
|
|
send_evictions=false
|
|
sequencer=system.ruby.l1_cntrl0.sequencer
|
|
system=system
|
|
to_l2_latency=1
|
|
transitions_per_cycle=4
|
|
version=0
|
|
requestFromL1Cache=system.ruby.network.slave[0]
|
|
requestToL1Cache=system.ruby.network.master[0]
|
|
responseFromL1Cache=system.ruby.network.slave[1]
|
|
responseToL1Cache=system.ruby.network.master[1]
|
|
unblockFromL1Cache=system.ruby.network.slave[2]
|
|
|
|
[system.ruby.l1_cntrl0.L1Dcache]
|
|
type=RubyCache
|
|
assoc=2
|
|
dataAccessLatency=1
|
|
dataArrayBanks=1
|
|
eventq_index=0
|
|
is_icache=false
|
|
latency=3
|
|
replacement_policy=PSEUDO_LRU
|
|
resourceStalls=false
|
|
size=32768
|
|
start_index_bit=6
|
|
tagAccessLatency=1
|
|
tagArrayBanks=1
|
|
|
|
[system.ruby.l1_cntrl0.L1Icache]
|
|
type=RubyCache
|
|
assoc=2
|
|
dataAccessLatency=1
|
|
dataArrayBanks=1
|
|
eventq_index=0
|
|
is_icache=true
|
|
latency=3
|
|
replacement_policy=PSEUDO_LRU
|
|
resourceStalls=false
|
|
size=32768
|
|
start_index_bit=6
|
|
tagAccessLatency=1
|
|
tagArrayBanks=1
|
|
|
|
[system.ruby.l1_cntrl0.prefetcher]
|
|
type=Prefetcher
|
|
cross_page=false
|
|
eventq_index=0
|
|
nonunit_filter=8
|
|
num_startup_pfs=1
|
|
num_streams=4
|
|
pf_per_stream=1
|
|
sys=system
|
|
train_misses=4
|
|
unit_filter=8
|
|
|
|
[system.ruby.l1_cntrl0.sequencer]
|
|
type=RubySequencer
|
|
access_backing_store=false
|
|
clk_domain=system.cpu_clk_domain
|
|
dcache=system.ruby.l1_cntrl0.L1Dcache
|
|
deadlock_threshold=500000
|
|
eventq_index=0
|
|
icache=system.ruby.l1_cntrl0.L1Icache
|
|
max_outstanding_requests=16
|
|
ruby_system=system.ruby
|
|
support_data_reqs=true
|
|
support_inst_reqs=true
|
|
system=system
|
|
using_network_tester=false
|
|
using_ruby_tester=false
|
|
version=0
|
|
master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
|
|
mem_master_port=system.iobus.slave[2]
|
|
pio_master_port=system.iobus.slave[1]
|
|
pio_slave_port=system.iobus.master[17]
|
|
slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
|
|
|
|
[system.ruby.l1_cntrl1]
|
|
type=L1Cache_Controller
|
|
children=L1Dcache L1Icache prefetcher sequencer
|
|
L1Dcache=system.ruby.l1_cntrl1.L1Dcache
|
|
L1Icache=system.ruby.l1_cntrl1.L1Icache
|
|
buffer_size=0
|
|
clk_domain=system.cpu_clk_domain
|
|
cluster_id=0
|
|
enable_prefetch=false
|
|
eventq_index=0
|
|
l1_request_latency=2
|
|
l1_response_latency=2
|
|
l2_select_num_bits=0
|
|
number_of_TBEs=256
|
|
prefetcher=system.ruby.l1_cntrl1.prefetcher
|
|
recycle_latency=10
|
|
ruby_system=system.ruby
|
|
send_evictions=false
|
|
sequencer=system.ruby.l1_cntrl1.sequencer
|
|
system=system
|
|
to_l2_latency=1
|
|
transitions_per_cycle=4
|
|
version=1
|
|
requestFromL1Cache=system.ruby.network.slave[3]
|
|
requestToL1Cache=system.ruby.network.master[2]
|
|
responseFromL1Cache=system.ruby.network.slave[4]
|
|
responseToL1Cache=system.ruby.network.master[3]
|
|
unblockFromL1Cache=system.ruby.network.slave[5]
|
|
|
|
[system.ruby.l1_cntrl1.L1Dcache]
|
|
type=RubyCache
|
|
assoc=2
|
|
dataAccessLatency=1
|
|
dataArrayBanks=1
|
|
eventq_index=0
|
|
is_icache=false
|
|
latency=3
|
|
replacement_policy=PSEUDO_LRU
|
|
resourceStalls=false
|
|
size=32768
|
|
start_index_bit=6
|
|
tagAccessLatency=1
|
|
tagArrayBanks=1
|
|
|
|
[system.ruby.l1_cntrl1.L1Icache]
|
|
type=RubyCache
|
|
assoc=2
|
|
dataAccessLatency=1
|
|
dataArrayBanks=1
|
|
eventq_index=0
|
|
is_icache=true
|
|
latency=3
|
|
replacement_policy=PSEUDO_LRU
|
|
resourceStalls=false
|
|
size=32768
|
|
start_index_bit=6
|
|
tagAccessLatency=1
|
|
tagArrayBanks=1
|
|
|
|
[system.ruby.l1_cntrl1.prefetcher]
|
|
type=Prefetcher
|
|
cross_page=false
|
|
eventq_index=0
|
|
nonunit_filter=8
|
|
num_startup_pfs=1
|
|
num_streams=4
|
|
pf_per_stream=1
|
|
sys=system
|
|
train_misses=4
|
|
unit_filter=8
|
|
|
|
[system.ruby.l1_cntrl1.sequencer]
|
|
type=RubySequencer
|
|
access_backing_store=false
|
|
clk_domain=system.cpu_clk_domain
|
|
dcache=system.ruby.l1_cntrl1.L1Dcache
|
|
deadlock_threshold=500000
|
|
eventq_index=0
|
|
icache=system.ruby.l1_cntrl1.L1Icache
|
|
max_outstanding_requests=16
|
|
ruby_system=system.ruby
|
|
support_data_reqs=true
|
|
support_inst_reqs=true
|
|
system=system
|
|
using_network_tester=false
|
|
using_ruby_tester=false
|
|
version=1
|
|
master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
|
|
mem_master_port=system.iobus.slave[4]
|
|
pio_master_port=system.iobus.slave[3]
|
|
pio_slave_port=system.iobus.master[18]
|
|
slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master
|
|
|
|
[system.ruby.l2_cntrl0]
|
|
type=L2Cache_Controller
|
|
children=L2cache
|
|
L2cache=system.ruby.l2_cntrl0.L2cache
|
|
buffer_size=0
|
|
clk_domain=system.ruby.clk_domain
|
|
cluster_id=0
|
|
eventq_index=0
|
|
l2_request_latency=2
|
|
l2_response_latency=2
|
|
number_of_TBEs=256
|
|
recycle_latency=10
|
|
ruby_system=system.ruby
|
|
system=system
|
|
to_l1_latency=1
|
|
transitions_per_cycle=4
|
|
version=0
|
|
DirRequestFromL2Cache=system.ruby.network.slave[6]
|
|
L1RequestFromL2Cache=system.ruby.network.slave[7]
|
|
L1RequestToL2Cache=system.ruby.network.master[5]
|
|
responseFromL2Cache=system.ruby.network.slave[8]
|
|
responseToL2Cache=system.ruby.network.master[6]
|
|
unblockToL2Cache=system.ruby.network.master[4]
|
|
|
|
[system.ruby.l2_cntrl0.L2cache]
|
|
type=RubyCache
|
|
assoc=2
|
|
dataAccessLatency=1
|
|
dataArrayBanks=1
|
|
eventq_index=0
|
|
is_icache=false
|
|
latency=15
|
|
replacement_policy=PSEUDO_LRU
|
|
resourceStalls=false
|
|
size=4194304
|
|
start_index_bit=6
|
|
tagAccessLatency=1
|
|
tagArrayBanks=1
|
|
|
|
[system.ruby.memctrl_clk_domain]
|
|
type=DerivedClockDomain
|
|
clk_divider=3
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
|
|
[system.ruby.network]
|
|
type=SimpleNetwork
|
|
children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 routers4 routers5 routers6
|
|
adaptive_routing=false
|
|
buffer_size=0
|
|
clk_domain=system.ruby.clk_domain
|
|
control_msg_size=8
|
|
endpoint_bandwidth=1000
|
|
eventq_index=0
|
|
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5
|
|
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
|
|
netifs=
|
|
number_of_virtual_networks=10
|
|
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5 system.ruby.network.routers6
|
|
ruby_system=system.ruby
|
|
topology=Crossbar
|
|
master=system.ruby.l1_cntrl0.requestToL1Cache system.ruby.l1_cntrl0.responseToL1Cache system.ruby.l1_cntrl1.requestToL1Cache system.ruby.l1_cntrl1.responseToL1Cache system.ruby.l2_cntrl0.unblockToL2Cache system.ruby.l2_cntrl0.L1RequestToL2Cache system.ruby.l2_cntrl0.responseToL2Cache system.ruby.dir_cntrl0.requestToDir system.ruby.dir_cntrl0.responseToDir system.ruby.dma_cntrl0.responseFromDir system.ruby.io_controller.responseFromDir
|
|
slave=system.ruby.l1_cntrl0.requestFromL1Cache system.ruby.l1_cntrl0.responseFromL1Cache system.ruby.l1_cntrl0.unblockFromL1Cache system.ruby.l1_cntrl1.requestFromL1Cache system.ruby.l1_cntrl1.responseFromL1Cache system.ruby.l1_cntrl1.unblockFromL1Cache system.ruby.l2_cntrl0.DirRequestFromL2Cache system.ruby.l2_cntrl0.L1RequestFromL2Cache system.ruby.l2_cntrl0.responseFromL2Cache system.ruby.dir_cntrl0.responseFromDir system.ruby.dma_cntrl0.requestToDir system.ruby.io_controller.requestToDir
|
|
|
|
[system.ruby.network.ext_links0]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.l1_cntrl0
|
|
int_node=system.ruby.network.routers0
|
|
latency=1
|
|
link_id=0
|
|
weight=1
|
|
|
|
[system.ruby.network.ext_links1]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.l1_cntrl1
|
|
int_node=system.ruby.network.routers1
|
|
latency=1
|
|
link_id=1
|
|
weight=1
|
|
|
|
[system.ruby.network.ext_links2]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.l2_cntrl0
|
|
int_node=system.ruby.network.routers2
|
|
latency=1
|
|
link_id=2
|
|
weight=1
|
|
|
|
[system.ruby.network.ext_links3]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.dir_cntrl0
|
|
int_node=system.ruby.network.routers3
|
|
latency=1
|
|
link_id=3
|
|
weight=1
|
|
|
|
[system.ruby.network.ext_links4]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.dma_cntrl0
|
|
int_node=system.ruby.network.routers4
|
|
latency=1
|
|
link_id=4
|
|
weight=1
|
|
|
|
[system.ruby.network.ext_links5]
|
|
type=SimpleExtLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
ext_node=system.ruby.io_controller
|
|
int_node=system.ruby.network.routers5
|
|
latency=1
|
|
link_id=5
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links0]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=6
|
|
node_a=system.ruby.network.routers0
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links1]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=7
|
|
node_a=system.ruby.network.routers1
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links2]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=8
|
|
node_a=system.ruby.network.routers2
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links3]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=9
|
|
node_a=system.ruby.network.routers3
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links4]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=10
|
|
node_a=system.ruby.network.routers4
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.int_links5]
|
|
type=SimpleIntLink
|
|
bandwidth_factor=16
|
|
eventq_index=0
|
|
latency=1
|
|
link_id=11
|
|
node_a=system.ruby.network.routers5
|
|
node_b=system.ruby.network.routers6
|
|
weight=1
|
|
|
|
[system.ruby.network.routers0]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=0
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers1]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=1
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers2]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=2
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers3]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=3
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers4]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=4
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers5]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=5
|
|
virt_nets=10
|
|
|
|
[system.ruby.network.routers6]
|
|
type=Switch
|
|
clk_domain=system.ruby.clk_domain
|
|
eventq_index=0
|
|
router_id=6
|
|
virt_nets=10
|
|
|
|
[system.smbios_table]
|
|
type=X86SMBiosSMBiosTable
|
|
children=structures
|
|
eventq_index=0
|
|
major_version=2
|
|
minor_version=5
|
|
structures=system.smbios_table.structures
|
|
|
|
[system.smbios_table.structures]
|
|
type=X86SMBiosBiosInformation
|
|
characteristic_ext_bytes=
|
|
characteristics=
|
|
emb_cont_firmware_major=0
|
|
emb_cont_firmware_minor=0
|
|
eventq_index=0
|
|
major=0
|
|
minor=0
|
|
release_date=06/08/2008
|
|
rom_size=0
|
|
starting_addr_segment=0
|
|
vendor=
|
|
version=
|
|
|
|
[system.sys_port_proxy]
|
|
type=RubyPortProxy
|
|
access_backing_store=false
|
|
clk_domain=system.clk_domain
|
|
eventq_index=0
|
|
ruby_system=system.ruby
|
|
support_data_reqs=true
|
|
support_inst_reqs=true
|
|
system=system
|
|
using_ruby_tester=false
|
|
version=0
|
|
slave=system.system_port
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
eventq_index=0
|
|
voltage=1.000000
|
|
|