stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.

tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.061494                       # Nu
 sim_ticks                                 61493732000                       # Number of ticks simulated
 final_tick                                61493732000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 280016                       # Simulator instruction rate (inst/s)
-host_op_rate                                   281410                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              190051649                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 385752                       # Number of bytes of host memory used
-host_seconds                                   323.56                       # Real time elapsed on the host
+host_inst_rate                                 271090                       # Simulator instruction rate (inst/s)
+host_op_rate                                   272440                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              183993432                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 445016                       # Number of bytes of host memory used
+host_seconds                                   334.22                       # Real time elapsed on the host
 sim_insts                                    90602849                       # Number of instructions simulated
 sim_ops                                      91054080                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895           37      2.41%     51.50% # By
 system.physmem.bytesPerActivate::896-1023           39      2.54%     54.04% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          705     45.96%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1534                       # Bytes accessed per row activation
-system.physmem.totQLat                       73246500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 365277750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       73247750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 365279000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     77875000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4702.83                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        4702.91                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23452.83                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23452.91                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          16.21                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       16.21                       # Average system read bandwidth in MiByte/s
@@ -218,29 +218,34 @@ system.physmem.readRowHitRate                   90.09                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                      3948227.51                       # Average gap between requests
 system.physmem.pageHitRate                      90.09                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      56242943250                       # Time in different power states
-system.physmem.memoryStateTime::REF        2053220000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        3193793750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   6320160                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   5261760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   3448500                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2871000                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 63663600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 57462600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            4016098320                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            4016098320                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            2490497865                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            2514078765                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           34708310250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           34687625250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             41288338695                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             41283397695                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             671.483256                       # Core power per rank (mW)
-system.physmem.averagePower::1             671.402899                       # Core power per rank (mW)
+system.physmem_0.actEnergy                    6320160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3448500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  63663600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             4016098320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2490640650                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34708185000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41288356230                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.483541                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57732029500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2053220000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1704707500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    5261760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2871000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  57462600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             4016098320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2514095865                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34687610250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41283399795                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.402933                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57698939250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2053220000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1738589750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                20789429                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          17091399                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            765966                       # Number of conditional branches incorrect
@@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct             98.812096                       # BT
 system.cpu.branchPred.usedRAS                   62716                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -383,14 +420,14 @@ system.cpu.dcache.demand_misses::cpu.inst       988866                       # n
 system.cpu.dcache.demand_misses::total         988866                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst       988866                       # number of overall misses
 system.cpu.dcache.overall_misses::total        988866                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11910311744                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11910311744                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2345697500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2345697500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  14256009244                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14256009244                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  14256009244                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14256009244                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  11910296994                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11910296994                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   2345727500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2345727500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  14256024494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14256024494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  14256024494                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14256024494                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst     22513771                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     22513771                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst      4734981                       # number of WriteReq accesses(hits+misses)
@@ -411,14 +448,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.036290
 system.cpu.dcache.demand_miss_rate::total     0.036290                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.036290                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.036290                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.331663                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.331663                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.073010                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.073010                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.522809                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14416.522809                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.522809                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14416.522809                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.315542                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31738.478920                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14416.538231                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14416.538231                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14416.538231                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14416.538231                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -445,14 +482,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst       950203
 system.cpu.dcache.demand_mshr_misses::total       950203                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst       950203                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950203                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958869756                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958869756                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1333434750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1333434750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11292304506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11292304506                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11292304506                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11292304506                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   9958855506                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9958855506                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   1333449750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1333449750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  11292305256                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11292305256                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  11292305256                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11292305256                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.040128                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040128                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.009877                       # mshr miss rate for WriteReq accesses
@@ -461,22 +498,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.034871
 system.cpu.dcache.demand_mshr_miss_rate::total     0.034871                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.034871                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.034871                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.338432                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.338432                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28511.690686                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28511.690686                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.096878                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.096878                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.096878                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.096878                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.322659                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28512.011418                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11884.097668                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11884.097668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           690.411179                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           690.411182                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            27857009                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               803                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          34691.169365                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   690.411179                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst   690.411182                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.337115                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.337115                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          798                       # Occupied blocks per task id
@@ -556,13 +593,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128
 system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10247.121792                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        10247.121902                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1831334                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            15558                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           117.710117                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9356.236502                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.885290                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  9356.236608                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   890.885294                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.285530                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.027188                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.312717                       # Average percentage of cache occupancy
@@ -593,14 +630,14 @@ system.cpu.l2cache.demand_misses::cpu.inst        15583                       #
 system.cpu.l2cache.demand_misses::total         15583                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst        15583                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        15583                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71718500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     71718500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    958069250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    958069250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1029787750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1029787750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1029787750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1029787750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71704250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     71704250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    958084250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    958084250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1029788500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1029788500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1029788500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1029788500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       904238                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       904238                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks       943286                       # number of Writeback accesses(hits+misses)
@@ -619,14 +656,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016386
 system.cpu.l2cache.demand_miss_rate::total     0.016386                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016386                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.016386                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69026.467757                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69026.467757                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65873.848322                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65873.848322                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.049926                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66084.049926                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.049926                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66084.049926                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69012.752647                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65874.879675                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66084.098056                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66084.098056                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -649,14 +686,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst        15575
 system.cpu.l2cache.demand_mshr_misses::total        15575                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst        15575                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        15575                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58344750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58344750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    774500250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    774500250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    832845000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    832845000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    832845000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    832845000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58331000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58331000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    774515250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    774515250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    832846250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    832846250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    832846250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    832846250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.001140                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001140                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.310982                       # mshr miss rate for ReadExReq accesses
@@ -665,14 +702,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016377
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016377                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56590.446169                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56590.446169                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53252.217409                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53252.217409                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.194222                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.194222                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.194222                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.194222                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56577.109602                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53253.248762                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53473.274478                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53473.274478                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         904238                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        904238                       # Transaction distribution
@@ -705,7 +742,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy     1890432000                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy       1370748                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1428672494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1428672244                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                1031                       # Transaction distribution
 system.membus.trans_dist::ReadResp               1031                       # Transaction distribution
@@ -728,7 +765,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total               15575                       # Request fanout histogram
 system.membus.reqLayer0.occupancy            17956500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          146202000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          146201750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.054141                       # Nu
 sim_ticks                                 54141000000                       # Number of ticks simulated
 final_tick                                54141000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2068738                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2079040                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1236208278                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 428768                       # Number of bytes of host memory used
-host_seconds                                    43.80                       # Real time elapsed on the host
+host_inst_rate                                1669323                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1677636                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              997531404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 433488                       # Number of bytes of host memory used
+host_seconds                                    54.28                       # Real time elapsed on the host
 sim_insts                                    90602407                       # Number of instructions simulated
 sim_ops                                      91053638                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total              349238802                       # Wr
 system.physmem.bw_total::cpu.inst          7966662603                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          2011871521                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9978534124                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           130287905                       # Transaction distribution
-system.membus.trans_dist::ReadResp          130291792                       # Transaction distribution
-system.membus.trans_dist::WriteReq            4734981                       # Transaction distribution
-system.membus.trans_dist::WriteResp           4734981                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq               510                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp              510                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq          3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq           3887                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp          3887                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    215661540                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     54400800                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              270062340                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               540247816                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         135031170                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.798562                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                27200400     20.14%     20.14% # Request fanout histogram
-system.membus.snoop_fanout::5               107830770     79.86%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total           135031170                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   91054080                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           130287905                       # Transaction distribution
+system.membus.trans_dist::ReadResp          130291792                       # Transaction distribution
+system.membus.trans_dist::WriteReq            4734981                       # Transaction distribution
+system.membus.trans_dist::WriteResp           4734981                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq               510                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp              510                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq          3887                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq           3887                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp          3887                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    215661540                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     54400800                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total              270062340                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    431323080                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    108924736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               540247816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples         135031170                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.798562                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.401074                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                27200400     20.14%     20.14% # Request fanout histogram
+system.membus.snoop_fanout::5               107830770     79.86%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total           135031170                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.147041                       # Nu
 sim_ticks                                147041218000                       # Number of ticks simulated
 final_tick                               147041218000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1130471                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1136089                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1835190843                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 438268                       # Number of bytes of host memory used
-host_seconds                                    80.12                       # Real time elapsed on the host
+host_inst_rate                                1114927                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1120467                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1809956176                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 442716                       # Number of bytes of host memory used
+host_seconds                                    81.24                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91026990                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total             251576                       # In
 system.physmem.bw_total::cpu.inst              251576                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data             6425192                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                6676767                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
-system.membus.trans_dist::ReadResp                792                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  30680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  981760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15340                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15340    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15340                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15603000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          138323000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -198,6 +207,144 @@ system.cpu.op_class::MemWrite                 4744844      5.21%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   91054080                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            942702                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3565.593965                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       54410413000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593965                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.870506                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.870506                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1355                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          55347598                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55347598                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21556948                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21556948                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          507                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           507                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      26245320                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26245320                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26245827                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26245827                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900187                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900187                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       946796                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         946796                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       946799                       # number of overall misses
+system.cpu.dcache.overall_misses::total        946799                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711364000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11711364000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1217183500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1217183500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  12928547500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  12928547500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  12928547500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  12928547500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22457135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22457135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          510                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          510                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     27192116                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27192116                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27192626                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27192626                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040085                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040085                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005882                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005882                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.034819                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.034819                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.034818                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.034818                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13655.050824                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13655.007557                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
+system.cpu.dcache.writebacks::total            942334                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900186                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       900186                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       946795                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9910952000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9910952000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123965500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123965500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       117000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       117000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11034917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11034917500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11035034500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11035034500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005882                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005882                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        39000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        39000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 2                       # number of replacements
 system.cpu.icache.tags.tagsinuse           510.120575                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           107830172                       # Total number of references to valid blocks.
@@ -429,144 +576,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            942702                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3565.593965                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26253601                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            946798                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.728830                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       54410413000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3565.593965                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.870506                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.870506                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2550                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55347598                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55347598                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21556948                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21556948                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          507                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           507                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26245320                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26245320                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26245827                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26245827                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       900187                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        900187                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       946796                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         946796                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       946799                       # number of overall misses
-system.cpu.dcache.overall_misses::total        946799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11711364000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11711364000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1217183500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1217183500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  12928547500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  12928547500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  12928547500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  12928547500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22457135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          510                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27192116                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27192626                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040085                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005882                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.034819                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.034818                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13655.050824                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13655.007557                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942334                       # number of writebacks
-system.cpu.dcache.writebacks::total            942334                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       900186                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       946795                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9910952000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9910952000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123965500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123965500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       117000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       117000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11034917500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11034917500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11035034500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11035034500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040085                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005882                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034818                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        39000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        39000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        900788                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       942334                       # Transaction distribution
@@ -600,5 +609,28 @@ system.cpu.toL2Bus.respLayer0.occupancy        898500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1420197000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 792                       # Transaction distribution
+system.membus.trans_dist::ReadResp                792                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             14548                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            14548                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        30680                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  30680                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       981760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  981760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples             15340                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   15340    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total               15340                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            15603000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          138323000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.061857                       # Nu
 sim_ticks                                 61857343500                       # Number of ticks simulated
 final_tick                                61857343500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 117254                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206466                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45908562                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 395064                       # Number of bytes of host memory used
-host_seconds                                  1347.40                       # Real time elapsed on the host
+host_inst_rate                                 113051                       # Simulator instruction rate (inst/s)
+host_op_rate                                   199065                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               44263102                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 453712                       # Number of bytes of host memory used
+host_seconds                                  1397.49                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16                  2     20.00%     20.00% # Wr
 system.physmem.wrPerTurnAround::18                  7     70.00%     90.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::19                  1     10.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total              10                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      131010750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 700467000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                      130999000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 700455250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    151855000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4313.68                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        4313.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23063.68                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23063.29                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          31.42                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.18                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       31.52                       # Average system read bandwidth in MiByte/s
@@ -244,56 +244,34 @@ system.physmem.readRowHitRate                   91.19                       # Ro
 system.physmem.writeRowHitRate                  60.41                       # Row buffer hit rate for writes
 system.physmem.avgGap                      2017525.41                       # Average gap between requests
 system.physmem.pageHitRate                      90.99                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      55617527500                       # Time in different power states
-system.physmem.memoryStateTime::REF        2065440000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        4171276250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                  10939320                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   9623880                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   5968875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   5251125                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                122226000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                114246600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                 1095120                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                   51840                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            4040000640                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            4040000640                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            2776037940                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            2977033050                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           34677417000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           34501105500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             41633684895                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             41647312635                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             673.093577                       # Core power per rank (mW)
-system.physmem.averagePower::1             673.313897                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                1465                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1462                       # Transaction distribution
-system.membus.trans_dist::Writeback               197                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61120                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1962048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1962048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1962048                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30660                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30660    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30660                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            43500000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          291787250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                   10939320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    5968875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 122226000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1095120                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             4040000640                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2776043070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34677412500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41633685525                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.093587                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57673269750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2065440000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2115534000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    9623880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5251125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 114246600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             4040000640                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2977027920                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34501101750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41647303755                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.313903                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57380456750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2065440000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2409426750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                37414357                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          37414357                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            797165                       # Number of conditional branches incorrect
@@ -303,16 +281,17 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             99.501048                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 5521067                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               5418                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        123714688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28240184                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles           28240185                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                      201519425                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                    37414357                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches           26823716                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      94568947                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                      94568946                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                 1664995                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  796                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles         13919                       # Number of stall cycles due to pending traps
@@ -339,22 +318,22 @@ system.cpu.fetch.rateDist::max_value                8                       # Nu
 system.cpu.fetch.rateDist::total            123656373                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.302425                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        1.628905                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13285380                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63221157                       # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles                 13285381                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63221156                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                  36527318                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles               9790021                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                 832497                       # Number of cycles decode is squashing
 system.cpu.decode.DecodedInsts              334996459                       # Number of instructions handled by decode
 system.cpu.rename.SquashCycles                 832497                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18592313                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                 18592314                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                 8932600                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles          16230                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                  40801194                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              54481539                       # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles              54481538                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts              328650401                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                  2309                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                 768646                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48119118                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.LQFullEvents               48119117                       # Number of times rename has blocked due to LQ full
 system.cpu.rename.SQFullEvents                4597217                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands           330628900                       # Number of destination operands rename has renamed
 system.cpu.rename.RenameLookups             873052183                       # Number of register rename lookups that rename has made
@@ -380,21 +359,21 @@ system.cpu.iq.issued_per_cycle::samples     123656373                       # Nu
 system.cpu.iq.issued_per_cycle::mean         2.490585                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        2.124426                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30107103     24.35%     24.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            30107102     24.35%     24.35% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::1            19550071     15.81%     40.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16727631     13.53%     53.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            16727632     13.53%     53.68% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::3            17064547     13.80%     67.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16031842     12.96%     80.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12684149     10.26%     90.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             5762402      4.66%     95.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             4173790      3.38%     98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1554838      1.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            16031841     12.96%     80.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12684150     10.26%     90.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5762404      4.66%     95.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4173789      3.38%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1554837      1.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::total       123656373                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  316998      7.53%      7.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  316999      7.53%      7.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      7.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.53% # attempts to use FU when none available
@@ -463,17 +442,17 @@ system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Ty
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total              307976733                       # Type of FU issued
 system.cpu.iq.rate                           2.489411                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     4211171                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt                     4211172                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.013674                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          743874544                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads          743874545                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes         372209729                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses    305990656                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 599                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes               1009                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses          208                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              312154273                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              312154274                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     293                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58255906                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         58255905                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
 system.cpu.iew.lsq.thread0.squashedLoads     15546535                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses        56855                       # Number of memory responses ignored because the instruction is squashed
@@ -509,8 +488,8 @@ system.cpu.iew.exec_stores                   33824606                       # Nu
 system.cpu.iew.exec_rate                     2.480687                       # Inst execution rate
 system.cpu.iew.wb_sent                      306320115                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                     305990864                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 231632885                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 336126878                       # num instructions consuming a value
+system.cpu.iew.wb_producers                 231632886                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 336126880                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_rate                       2.473359                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.689123                       # average fanout of values written-back
@@ -522,12 +501,12 @@ system.cpu.commit.committed_per_cycle::samples    117208008
 system.cpu.commit.committed_per_cycle::mean     2.373494                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     3.089570                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52857680     45.10%     45.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     52857679     45.10%     45.10% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1     15964987     13.62%     58.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     10970810      9.36%     68.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8748486      7.46%     75.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     10970811      9.36%     68.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8748487      7.46%     75.54% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::4      1925592      1.64%     77.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1731777      1.48%     78.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1731776      1.48%     78.66% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6       850158      0.73%     79.39% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7       689946      0.59%     79.98% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8     23468572     20.02%    100.00% # Number of insts commited each cycle
@@ -600,37 +579,121 @@ system.cpu.cc_regfile_reads                 107699117                       # nu
 system.cpu.cc_regfile_writes                 64568807                       # number of cc regfile writes
 system.cpu.misc_regfile_reads               196282104                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq        1995493                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1995490                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82065                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82065                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2052                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219715                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6221767                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        65664                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265163712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265229376                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      4144212                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3            4144212    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        4144212                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4138760000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1710750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3121417500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          5.0                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements           2072433                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.938050                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            68459745                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076529                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             32.968355                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       19695463250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.938050                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993393                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993393                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          636                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3333                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         144502465                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        144502465                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     37113882                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37113882                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31345863                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31345863                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68459745                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68459745                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68459745                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68459745                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2659334                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2659334                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93889                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93889                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2753223                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2753223                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2753223                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2753223                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31861027000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31861027000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2765155494                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2765155494                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34626182494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34626182494                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34626182494                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34626182494                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     39773216                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     39773216                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     71212968                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     71212968                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     71212968                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     71212968                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.066862                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.066862                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002986                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002986                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.038662                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.038662                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.038662                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.038662                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12576.599314                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12576.599314                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       182189                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             39926                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     4.563167                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      2066654                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066654                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       664835                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       664835                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11856                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        11856                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       676691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       676691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       676691                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       676691                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994499                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994499                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82033                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82033                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076532                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076532                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076532                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076532                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22009124500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22009124500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2514972744                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2514972744                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24524097244                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24524097244                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24524097244                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24524097244                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050147                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050147                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.029159                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.029159                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                62                       # number of replacements
 system.cpu.icache.tags.tagsinuse           827.714171                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            27848273                       # Total number of references to valid blocks.
@@ -660,12 +723,12 @@ system.cpu.icache.demand_misses::cpu.inst         1347                       # n
 system.cpu.icache.demand_misses::total           1347                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1347                       # number of overall misses
 system.cpu.icache.overall_misses::total          1347                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     92883749                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     92883749                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     92883749                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     92883749                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     92883749                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     92883749                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     92877749                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     92877749                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     92877749                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     92877749                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     92877749                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     92877749                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     27849620                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     27849620                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     27849620                       # number of demand (read+write) accesses
@@ -678,12 +741,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000048
 system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68956.012621                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68956.012621                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68951.558278                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68951.558278                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68951.558278                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68951.558278                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68951.558278                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68951.558278                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          850                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
@@ -704,32 +767,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         1026
 system.cpu.icache.demand_mshr_misses::total         1026                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         1026                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         1026                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     72336999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     72336999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     72336999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     72336999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     72336999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     72336999                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     72330999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     72330999                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     72330999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     72330999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     72330999                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     72330999                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70498.049708                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70498.049708                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70498.049708                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70498.049708                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70498.049708                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70498.049708                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements              515                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20693.420536                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        20693.420547                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            4029533                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs            30444                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs           132.358856                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319882                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.inst   681.987127                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.data   249.113538                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.603098                       # Average percentage of cache occupancy
@@ -769,17 +832,17 @@ system.cpu.l2cache.demand_misses::total         30463                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         1010                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        29453                       # number of overall misses
 system.cpu.l2cache.overall_misses::total        30463                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71141750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     31680000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    102821750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1901914500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1901914500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     71141750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1933594500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2004736250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     71141750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1933594500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2004736250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     71135750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     31674000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    102809750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1901914750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1901914750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     71135750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1933588750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2004724500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     71135750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1933588750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2004724500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         1026                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      1994467                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total      1995493                       # number of ReadReq accesses(hits+misses)
@@ -804,17 +867,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.014663                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984405                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.014184                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.014663                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70431.435644                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69613.186813                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70177.303754                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.790537                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.790537                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70431.435644                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65649.976233                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 65808.505400                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70431.435644                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65649.976233                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 65808.505400                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -836,17 +899,17 @@ system.cpu.l2cache.demand_mshr_misses::total        30463
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1010                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        29453                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total        30463                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58482750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     26096500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     84579250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1530042000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1530042000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     58482750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1556138500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1614621250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     58482750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1556138500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1614621250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     58476750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     26090500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     84567250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1530042250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1530042250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     58476750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1556132750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1614609500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     58476750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1556132750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1614609500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.984405                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000228                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000734                       # mshr miss rate for ReadReq accesses
@@ -858,132 +921,74 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.014663
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984405                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014184                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.014663                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2072433                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.938050                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68459744                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076529                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.968354                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       19695463250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.938050                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993393                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993393                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          636                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3333                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         144502463                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        144502463                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     37113881                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37113881                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345863                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345863                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68459744                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68459744                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68459744                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68459744                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2659334                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2659334                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93889                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93889                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2753223                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2753223                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2753223                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2753223                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31861058000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31861058000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2765155744                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2765155744                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34626213744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34626213744                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34626213744                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34626213744                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39773215                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39773215                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     71212967                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     71212967                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     71212967                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     71212967                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.066862                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.066862                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002986                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002986                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.038662                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.038662                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.038662                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.038662                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12576.610665                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12576.610665                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       182189                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             39926                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     4.563167                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066654                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066654                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       664835                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       664835                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11856                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        11856                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       676691                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       676691                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       676691                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       676691                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994499                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994499                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82033                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82033                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076532                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076532                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076532                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076532                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22009130500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  22009130500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2514972494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2514972494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24524102994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24524102994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24524102994                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24524102994                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050147                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050147                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029159                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029159                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq        1995493                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1995490                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82065                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82065                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2052                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219715                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6221767                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        65664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265163712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265229376                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      4144212                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3            4144212    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        4144212                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4138760000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1710750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    3121417250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          5.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                1465                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1462                       # Transaction distribution
+system.membus.trans_dist::Writeback               197                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61120                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1962048                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples             30660                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30660    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total               30660                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            43499500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          291787500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.279362                       # Nu
 sim_ticks                                279362297500                       # Number of ticks simulated
 final_tick                               279362297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2087081                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2260585                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1150953174                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299952                       # Number of bytes of host memory used
-host_seconds                                   242.72                       # Real time elapsed on the host
+host_inst_rate                                1700410                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1841769                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              937717572                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304668                       # Number of bytes of host memory used
+host_seconds                                   297.92                       # Real time elapsed on the host
 sim_insts                                   506581607                       # Number of instructions simulated
 sim_ops                                     548694828                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total              773431583                       # Wr
 system.physmem.bw_total::cpu.inst          7397009255                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          2287067119                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9684076374                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           630711790                       # Transaction distribution
-system.membus.trans_dist::ReadResp          632200331                       # Transaction distribution
-system.membus.trans_dist::WriteReq           54239306                       # Transaction distribution
-system.membus.trans_dist::WriteResp          54239306                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq              2571                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp             2571                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq       1488541                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq        1488541                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp       1488541                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1033222750                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    342638748                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             1375861498                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2066445500                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    638920325                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2705365825                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         687930749                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.750964                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.432455                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4               171319374     24.90%     24.90% # Request fanout histogram
-system.membus.snoop_fanout::5               516611375     75.10%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total           687930749                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  548695378                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           630711790                       # Transaction distribution
+system.membus.trans_dist::ReadResp          632200331                       # Transaction distribution
+system.membus.trans_dist::WriteReq           54239306                       # Transaction distribution
+system.membus.trans_dist::WriteResp          54239306                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq              2571                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp             2571                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq       1488541                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq        1488541                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp       1488541                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1033222750                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    342638748                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total             1375861498                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2066445500                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    638920325                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              2705365825                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples         687930749                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.750964                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.432455                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4               171319374     24.90%     24.90% # Request fanout histogram
+system.membus.snoop_fanout::5               516611375     75.10%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total           687930749                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.707539                       # Nu
 sim_ticks                                707539023000                       # Number of ticks simulated
 final_tick                               707539023000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1199909                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1299448                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1681197618                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309428                       # Number of bytes of host memory used
-host_seconds                                   420.85                       # Real time elapsed on the host
+host_inst_rate                                1166033                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1262762                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1633733414                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312880                       # Number of bytes of host memory used
+host_seconds                                   433.08                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
 sim_ops                                     546878104                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks           8679369                       # To
 system.physmem.bw_total::cpu.inst              250559                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            12652667                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               21582595                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq               41855                       # Transaction distribution
-system.membus.trans_dist::ReadResp              41855                       # Transaction distribution
-system.membus.trans_dist::Writeback             95953                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100794                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100794                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       381251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 381251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15270528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15270528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            238603                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  238603    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              238603                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1018523828                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1290155000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -206,6 +214,139 @@ system.cpu.op_class::MemWrite                56860479     10.36%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  548695378                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           1134822                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4065.318438                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       11716392000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318438                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          343                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3546                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          165                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         343777666                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        343777666                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    113317758                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       113317758                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2570                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2570                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     167200804                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167200804                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167203374                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167203374                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       782657                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        782657                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       356260                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1138917                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11819576500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11819576500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8868781000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8868781000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  20688357500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  20688357500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  20688357500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  20688357500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2571                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2571                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    168339721                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168339721                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168342292                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168342292                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006859                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.006859                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000389                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000389                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006766                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18164.938709                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18164.922760                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      1064905                       # number of writebacks
+system.cpu.dcache.writebacks::total           1064905                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782657                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       782657                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1138917                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10254262500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10254262500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8156261000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8156261000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18410523500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18410523500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18410576500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18410576500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000389                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000389                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
 system.cpu.icache.tags.tagsinuse           983.372001                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516599855                       # Total number of references to valid blocks.
@@ -439,139 +580,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1134822                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4065.318438                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           170180456                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1138918                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.422922                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       11716392000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4065.318438                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992509                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992509                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          343                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3546                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          165                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         343777666                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        343777666                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    113317758                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       113317758                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2570                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2570                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     167200804                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        167200804                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    167203374                       # number of overall hits
-system.cpu.dcache.overall_hits::total       167203374                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       782657                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        782657                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       356260                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1138917                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1138917                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11819576500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11819576500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8868781000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8868781000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  20688357500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  20688357500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  20688357500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  20688357500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    114100415                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    114100415                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2571                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2571                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168339721                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168339721                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168342292                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168342292                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006859                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.006859                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000389                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.000389                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006766                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006766                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.006765                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.006765                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18164.938709                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18164.922760                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1064905                       # number of writebacks
-system.cpu.dcache.writebacks::total           1064905                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782657                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       782657                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356260                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1138917                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1138917                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10254262500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10254262500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8156261000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8156261000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18410523500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  18410523500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18410576500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  18410576500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006859                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006859                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006568                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000389                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000389                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006766                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006766                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006765                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006765                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         794179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        794179                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback      1064905                       # Transaction distribution
@@ -605,5 +613,29 @@ system.cpu.toL2Bus.respLayer0.occupancy      17281500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1708377000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq               41855                       # Transaction distribution
+system.membus.trans_dist::ReadResp              41855                       # Transaction distribution
+system.membus.trans_dist::Writeback             95953                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100794                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100794                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       381251                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 381251                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15270528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15270528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            238603                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  238603    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              238603                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1018523828                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1290155000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.226819                       # Nu
 sim_ticks                                226818771000                       # Number of ticks simulated
 final_tick                               226818771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 285609                       # Simulator instruction rate (inst/s)
-host_op_rate                                   285609                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              162496290                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242892                       # Number of bytes of host memory used
-host_seconds                                  1395.84                       # Real time elapsed on the host
+host_inst_rate                                 333141                       # Simulator instruction rate (inst/s)
+host_op_rate                                   333141                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              189539219                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300760                       # Number of bytes of host memory used
+host_seconds                                  1196.69                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895           32      2.10%     84.83% # By
 system.physmem.bytesPerActivate::896-1023           40      2.63%     87.46% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          191     12.54%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1523                       # Bytes accessed per row activation
-system.physmem.totQLat                       50615750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 198234500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       50610250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 198229000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6429.03                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6428.33                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25179.03                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25178.33                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.22                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.22                       # Average system read bandwidth in MiByte/s
@@ -218,36 +218,41 @@ system.physmem.readRowHitRate                   80.54                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                     28809690.02                       # Average gap between requests
 system.physmem.pageHitRate                      80.54                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     217525128250                       # Time in different power states
-system.physmem.memoryStateTime::REF        7573800000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1714919250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   6698160                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   4808160                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   3654750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2623500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 34164000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 26910000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           14814352800                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           14814352800                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            5823022815                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            5572463355                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          130980318750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          131200107750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            151662211275                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            151621265565                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.664178                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.483652                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                46273762                       # Number of BP lookups
+system.physmem_0.actEnergy                    6698160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3654750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  34164000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            14814352800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5823127980                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           130980226500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             151662224190                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.664235                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   217898379000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7573800000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1344256000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    4808160                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2623500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  26910000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            14814352800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5572496700                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           131200078500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             151621269660                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.483670                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   218263346500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7573800000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       976701000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                46273761                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          26730646                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1017469                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25595417                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups             25595416                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                21359944                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.452221                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             83.452224                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 8341649                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
@@ -293,15 +298,15 @@ system.cpu.discardedOps                       4467797                       # Nu
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.137893                       # CPI: cycles per instruction
 system.cpu.ipc                               0.878818                       # IPC: instructions per cycle
-system.cpu.tickCycles                       450174331                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3463211                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                       450174327                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3463215                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.955317                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3291.955330                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168028615                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          40343.004802                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.955317                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3291.955330                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.803700                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.803700                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
@@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst         7119                       # n
 system.cpu.dcache.demand_misses::total           7119                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst         7119                       # number of overall misses
 system.cpu.dcache.overall_misses::total          7119                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     81052500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     81052500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    391543250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    391543250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    472595750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    472595750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    472595750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    472595750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     81009750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     81009750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    391587500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    391587500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    472597250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    472597250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    472597250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    472597250                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst     94515004                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94515004                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     73520730                       # number of WriteReq accesses(hits+misses)
@@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68630.397968                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68630.397968                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65938.573594                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65938.573594                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.131339                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66385.131339                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.131339                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66385.131339                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68594.199831                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65946.025598                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66385.342042                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66385.342042                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66385.342042                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66385.342042                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64327500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     64327500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    214316000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    214316000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    278643500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    278643500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    278643500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    278643500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     64296000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     64296000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    214342750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    214342750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    278638750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    278638750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    278638750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    278638750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for WriteReq accesses
@@ -403,22 +408,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66317.010309                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66317.010309                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67078.560250                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67078.560250                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66901.200480                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66901.200480                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66901.200480                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66901.200480                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66284.536082                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67086.932707                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66900.060024                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66900.060024                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              3196                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1918.781810                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1918.781818                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            98776054                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              5174                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          19090.849246                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1918.781810                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1918.781818                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.936905                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.936905                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
@@ -441,12 +446,12 @@ system.cpu.icache.demand_misses::cpu.inst         5174                       # n
 system.cpu.icache.demand_misses::total           5174                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         5174                       # number of overall misses
 system.cpu.icache.overall_misses::total          5174                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    293010500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    293010500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    293010500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    293010500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    293010500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    293010500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    293011250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    293011250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    293011250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    293011250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    293011250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    293011250                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     98781228                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     98781228                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     98781228                       # number of demand (read+write) accesses
@@ -459,12 +464,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000052
 system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.329726                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56631.329726                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.329726                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56631.329726                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.329726                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56631.329726                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56631.474681                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56631.474681                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -479,33 +484,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         5174
 system.cpu.icache.demand_mshr_misses::total         5174                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         5174                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         5174                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281053500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281053500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281053500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281053500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281053500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281053500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281053750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281053750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281053750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281053750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281053750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281053750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.351759                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.351759                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.351759                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.351759                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4426.924710                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         4426.924727                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               1494                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5273                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.283330                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   373.138333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4053.786377                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   373.138335                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4053.786392                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011387                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.123712                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.135099                       # Average percentage of cache occupancy
@@ -535,14 +540,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         7873                       #
 system.cpu.l2cache.demand_misses::total          7873                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         7873                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7873                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    324986750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    324986750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    210671750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    210671750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    535658500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    535658500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    535658500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    535658500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    324955500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    324955500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    210698500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    210698500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    535654000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    535654000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    535654000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    535654000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         6141                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         6141                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          654                       # number of Writeback accesses(hits+misses)
@@ -561,14 +566,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.843024
 system.cpu.l2cache.demand_miss_rate::total     0.843024                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.843024                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.843024                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68620.513091                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68620.513091                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67157.076825                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67157.076825                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68037.406325                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68037.406325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68037.406325                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68037.406325                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68613.914696                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67165.604080                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68036.834752                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68036.834752                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -585,14 +590,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         7873
 system.cpu.l2cache.demand_mshr_misses::total         7873                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         7873                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7873                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    265636250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    265636250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    170998250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    170998250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    436634500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    436634500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    436634500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    436634500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    265602000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    265602000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    171025500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    171025500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    436627500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    436627500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    436627500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    436627500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.771210                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.771210                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.980926                       # mshr miss rate for ReadExReq accesses
@@ -601,14 +606,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.843024
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.843024                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.843024                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.843024                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56088.735220                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56088.735220                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54510.121135                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54510.121135                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55459.735806                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55459.735806                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55459.735806                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55459.735806                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56081.503378                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54518.807778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55458.846691                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55458.846691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq           6141                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          6141                       # Transaction distribution
@@ -635,9 +640,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total           9993                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy        5650500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       8565500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       8565750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6972500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6972750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                4736                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4736                       # Transaction distribution
@@ -660,7 +665,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                7873                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             9387500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           73875500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           73877500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.216828                       # Nu
 sim_ticks                                216828260500                       # Number of ticks simulated
 final_tick                               216828260500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 172164                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206702                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              136721287                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262128                       # Number of bytes of host memory used
-host_seconds                                  1585.91                       # Real time elapsed on the host
+host_inst_rate                                 175239                       # Simulator instruction rate (inst/s)
+host_op_rate                                   210394                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              139163086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320864                       # Number of bytes of host memory used
+host_seconds                                  1558.09                       # Real time elapsed on the host
 sim_insts                                   273037856                       # Number of instructions simulated
 sim_ops                                     327812213                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -184,24 +184,24 @@ system.physmem.wrQLenPdf::62                        0                       # Wh
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.bytesPerActivate::samples         1505                       # Bytes accessed per row activation
 system.physmem.bytesPerActivate::mean      321.360797                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.317321                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     333.826076                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            548     36.41%     36.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          349     23.19%     59.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          163     10.83%     70.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     189.304771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     333.736324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            549     36.48%     36.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          346     22.99%     59.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          165     10.96%     70.43% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::384-511           68      4.52%     74.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           69      4.58%     79.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           60      3.99%     83.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.19%     85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           70      4.65%     79.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           58      3.85%     83.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           34      2.26%     85.71% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::896-1023           33      2.19%     87.91% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          182     12.09%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total           1505                       # Bytes accessed per row activation
-system.physmem.totQLat                       50683250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 192902000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       50845500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 193064250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     37925000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6682.04                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6703.43                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25432.04                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25453.43                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.24                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.24                       # Average system read bandwidth in MiByte/s
@@ -218,29 +218,34 @@ system.physmem.readRowHitRate                   80.07                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                     28586424.65                       # Average gap between requests
 system.physmem.pageHitRate                      80.07                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     207228229000                       # Time in different power states
-system.physmem.memoryStateTime::REF        7240220000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        2356912000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   5012280                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   6342840                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   2734875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   3460875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 29905200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 29000400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           14161870320                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           14161870320                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            5651949285                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            5745162240                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          125136528000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          125054762250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            144987999960                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            145000598925                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.689925                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.748031                       # Core power per rank (mW)
+system.physmem_0.actEnergy                    5012280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2734875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            14161870320                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5652564030                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           125135988750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             144988075455                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.690273                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   208174326250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7240220000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1410814750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    6342840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3460875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  29000400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            14161870320                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5745534165                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           125054436000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             145000644600                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.748242                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   208036674250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7240220000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1549163250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                33221230                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          17174007                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1583983                       # Number of conditional branches incorrect
@@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct             87.059638                       # BT
 system.cpu.branchPred.usedRAS                 6611215                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -345,15 +382,15 @@ system.cpu.discardedOps                       4064410                       # Nu
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.588265                       # CPI: cycles per instruction
 system.cpu.ipc                               0.629618                       # IPC: instructions per cycle
-system.cpu.tickCycles                       430211091                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3445430                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                       430211127                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3445394                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3086.009332                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          3086.009488                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           168783807                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          37416.051208                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  3086.009332                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  3086.009488                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.753420                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.753420                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
@@ -385,14 +422,14 @@ system.cpu.dcache.demand_misses::cpu.inst         7290                       # n
 system.cpu.dcache.demand_misses::total           7290                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst         7290                       # number of overall misses
 system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst    126122956                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    126122956                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    360338500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    360338500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    486461456                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    486461456                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    486461456                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    486461456                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst    126489706                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    126489706                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    360451750                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    360451750                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    486941456                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    486941456                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    486941456                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    486941456                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst     86716630                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     86716630                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     82052677                       # number of WriteReq accesses(hits+misses)
@@ -413,14 +450,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61135.703345                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61135.703345                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68937.918500                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68937.918500                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66729.966529                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66729.966529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66729.966529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66729.966529                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61313.478429                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68959.584848                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66795.810151                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66795.810151                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66795.810151                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66795.810151                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -447,14 +484,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst         4511
 system.cpu.dcache.demand_mshr_misses::total         4511                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         4511                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     99847542                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     99847542                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    197786250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    197786250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    297633792                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    297633792                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    297633792                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    297633792                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst    100259792                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    100259792                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    197855250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    197855250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    298115042                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    298115042                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    298115042                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    298115042                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for WriteReq accesses
@@ -463,22 +500,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60845.546618                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60845.546618                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68915.069686                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68915.069686                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 65979.559299                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65979.559299                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 65979.559299                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65979.559299                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61096.765387                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68939.111498                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66086.242962                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66086.242962                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             36927                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1924.993605                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            73270396                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1924.993634                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            73270394                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             38864                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1885.302491                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1885.302439                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1924.993605                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1924.993634                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.939938                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.939938                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
@@ -488,44 +525,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2           34
 system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146657386                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146657386                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     73270396                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        73270396                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      73270396                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         73270396                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     73270396                       # number of overall hits
-system.cpu.icache.overall_hits::total        73270396                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         146657382                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146657382                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     73270394                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        73270394                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      73270394                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         73270394                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     73270394                       # number of overall hits
+system.cpu.icache.overall_hits::total        73270394                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        38865                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         38865                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        38865                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          38865                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        38865                       # number of overall misses
 system.cpu.icache.overall_misses::total         38865                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    703294747                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    703294747                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    703294747                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    703294747                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    703294747                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    703294747                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     73309261                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     73309261                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     73309261                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     73309261                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     73309261                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     73309261                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    703218247                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    703218247                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    703218247                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    703218247                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    703218247                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    703218247                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     73309259                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     73309259                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     73309259                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     73309259                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     73309259                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     73309259                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000530                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000530                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000530                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000530                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000530                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000530                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18095.838081                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18095.838081                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18095.838081                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18095.838081                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18095.838081                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18095.838081                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18093.869729                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18093.869729                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        38865
 system.cpu.icache.demand_mshr_misses::total        38865                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        38865                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        38865                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    624165253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    624165253                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    624165253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    624165253                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    624165253                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    624165253                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    624088753                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    624088753                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    624088753                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    624088753                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    624088753                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    624088753                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000530                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000530                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000530                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16059.828972                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16059.828972                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16059.828972                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16059.828972                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4198.559652                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         4198.559801                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              35809                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5647                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             6.341243                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.760812                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3844.798840                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.760842                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3844.798959                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.010796                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.117334                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.128130                       # Average percentage of cache occupancy
@@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         7630                       #
 system.cpu.l2cache.demand_misses::total          7630                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         7630                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    326194750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    326194750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    194720750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    194720750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    520915500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    520915500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    520915500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    520915500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    326530500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    326530500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    194789750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    194789750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    521320250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    521320250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    521320250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    521320250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        40506                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        40506                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
@@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.175904
 system.cpu.l2cache.demand_miss_rate::total     0.175904                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.175904                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.175904                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68298.733250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68298.733250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68227.312544                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68227.312544                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68272.018349                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68272.018349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68272.018349                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68272.018349                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68369.032663                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68251.489138                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68325.065531                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68325.065531                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         7585
 system.cpu.l2cache.demand_mshr_misses::total         7585                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         7585                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7585                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    264387500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    264387500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    158755250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158755250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    423142750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    423142750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    423142750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    423142750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    264479250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    264479250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    158825750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    158825750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    423305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    423305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    423305000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    423305000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.116798                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116798                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994425                       # mshr miss rate for ReadExReq accesses
@@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.174866
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.174866                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.174866                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.174866                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55884.062566                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55884.062566                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55625.525578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55625.525578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55786.783125                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55786.783125                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55786.783125                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55786.783125                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55903.455929                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55650.227751                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55808.174028                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55808.174028                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq          40506                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         40505                       # Transaction distribution
@@ -709,7 +746,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy       23203000                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      58996747                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7500208                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       7500458                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                4731                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4731                       # Transaction distribution
@@ -730,9 +767,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7585                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8963500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8964000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           71030250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           71030500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.201717                       # Nu
 sim_ticks                                201717313500                       # Number of ticks simulated
 final_tick                               201717313500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1306299                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1568357                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              965080142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305108                       # Number of bytes of host memory used
-host_seconds                                   209.02                       # Real time elapsed on the host
+host_inst_rate                                1117455                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1341629                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              825564009                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308812                       # Number of bytes of host memory used
+host_seconds                                   244.34                       # Real time elapsed on the host
 sim_insts                                   273037594                       # Number of instructions simulated
 sim_ops                                     327811949                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total             1983209850                       # Wr
 system.physmem.bw_total::cpu.inst          6913839312                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          4366293422                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            11280132734                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           434895827                       # Transaction distribution
-system.membus.trans_dist::ReadResp          434906722                       # Transaction distribution
-system.membus.trans_dist::WriteReq           82052672                       # Transaction distribution
-system.membus.trans_dist::WriteResp          82052672                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq             54062                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp            54062                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq         10895                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq          10895                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp         10895                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    697320546                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    336728156                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             1034048702                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1394641092                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    880756979                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              2275398071                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         517024351                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.674359                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.468614                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4               168364078     32.56%     32.56% # Request fanout histogram
-system.membus.snoop_fanout::5               348660273     67.44%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total           517024351                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite                82375594     25.13%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812144                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           434895827                       # Transaction distribution
+system.membus.trans_dist::ReadResp          434906722                       # Transaction distribution
+system.membus.trans_dist::WriteReq           82052672                       # Transaction distribution
+system.membus.trans_dist::WriteResp          82052672                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq             54062                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp            54062                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq         10895                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq          10895                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp         10895                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    697320546                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    336728156                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total             1034048702                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   1394641092                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    880756979                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              2275398071                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples         517024351                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.674359                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.468614                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4               168364078     32.56%     32.56% # Request fanout histogram
+system.membus.snoop_fanout::5               348660273     67.44%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total           517024351                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.517235                       # Nu
 sim_ticks                                517235411000                       # Number of ticks simulated
 final_tick                               517235411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 795879                       # Simulator instruction rate (inst/s)
-host_op_rate                                   955482                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1509341441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314596                       # Number of bytes of host memory used
-host_seconds                                   342.69                       # Real time elapsed on the host
+host_inst_rate                                 761441                       # Simulator instruction rate (inst/s)
+host_op_rate                                   914138                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1444030997                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318052                       # Number of bytes of host memory used
+host_seconds                                   358.19                       # Real time elapsed on the host
 sim_insts                                   272739285                       # Number of instructions simulated
 sim_ops                                     327433743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total             322824                       # In
 system.physmem.bw_total::cpu.inst              322824                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data              522532                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 845356                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                3976                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2856                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        13664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  13664                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       437248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  437248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              6833                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    6833    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                6833                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             7260000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           61915000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -198,6 +207,145 @@ system.cpu.op_class::MemWrite                82375599     25.13%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  327812213                       # Class of executed instruction
+system.cpu.dcache.tags.replacements              1332                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3078.445016                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445016                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336732670                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336732670                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86233963                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86233963                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82049805                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        54059                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         54059                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     168283768                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168283768                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168337827                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168337827                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1604                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1604                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         2872                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2872                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         4476                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
+system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     78354000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     78354000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    157425500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    157425500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    235779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    235779500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    235779500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    235779500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        54062                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        54062                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    168288244                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168288244                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168342306                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168342306                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000055                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000027                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 52676.385165                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 52641.102925                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
+system.cpu.dcache.writebacks::total               998                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1603                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1603                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4475                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75108000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75108000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151681500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    151681500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       159000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       159000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    226789500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    226948500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000055                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13796                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1766.007645                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           348644749                       # Total number of references to valid blocks.
@@ -430,145 +578,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements              1332                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3078.445016                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168359617                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4478                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37597.056052                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3078.445016                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.751573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.751573                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           10                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336732670                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336732670                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86233963                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86233963                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82049805                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        54059                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         54059                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168283768                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168283768                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168337827                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168337827                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1604                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1604                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         2872                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2872                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            3                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            3                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         4476                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           4476                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         4479                       # number of overall misses
-system.cpu.dcache.overall_misses::total          4479                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     78354000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     78354000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    157425500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    157425500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    235779500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    235779500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    235779500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    235779500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86235567                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86235567                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        54062                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        54062                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168288244                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168288244                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168342306                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168342306                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000055                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.000055                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000027                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000027                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000027                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000027                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 52676.385165                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52641.102925                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
-system.cpu.dcache.writebacks::total               998                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1603                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1603                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2872                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2872                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4475                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4475                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75108000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     75108000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151681500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    151681500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       159000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       159000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    226789500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226948500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    226948500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000055                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000055                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq          17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         17209                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          998                       # Transaction distribution
@@ -602,5 +611,28 @@ system.cpu.toL2Bus.respLayer0.occupancy      23404500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6717000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                3976                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3976                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2856                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2856                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        13664                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  13664                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       437248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  437248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              6833                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    6833    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                6833                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             7260000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           61915000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt

@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.559967                       # Number of seconds simulated
-sim_ticks                                559966999500                       # Number of ticks simulated
-final_tick                               559966999500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.559962                       # Number of seconds simulated
+sim_ticks                                559961514500                       # Number of ticks simulated
+final_tick                               559961514500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 393705                       # Simulator instruction rate (inst/s)
-host_op_rate                                   393705                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              237364888                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245892                       # Number of bytes of host memory used
-host_seconds                                  2359.10                       # Real time elapsed on the host
+host_inst_rate                                 343254                       # Simulator instruction rate (inst/s)
+host_op_rate                                   343254                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              206945650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305268                       # Number of bytes of host memory used
+host_seconds                                  2705.84                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -23,33 +23,33 @@ system.physmem.num_reads::cpu.inst             291519                       # Nu
 system.physmem.num_reads::total                291519                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             33318421                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33318421                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          333620                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             333620                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7621363                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7621363                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7621363                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            33318421                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40939784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             33318747                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                33318747                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          333623                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             333623                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7621438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7621438                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7621438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            33318747                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               40940185                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        291519                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
 system.physmem.readBursts                      291519                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18639936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     17280                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                 18640064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     17152                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                   4266560                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  18657216                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      270                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      268                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               17935                       # Per bank write bursts
 system.physmem.perBankRdBursts::1               18289                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               18306                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18248                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18163                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18239                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18250                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18167                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18240                       # Per bank write bursts
 system.physmem.perBankRdBursts::6               18320                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               18299                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               18230                       # Per bank write bursts
@@ -59,7 +59,7 @@ system.physmem.perBankRdBursts::11              18391                       # Pe
 system.physmem.perBankRdBursts::12              18259                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              18042                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              17977                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18106                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18101                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    559966923500                       # Total gap between requests
+system.physmem.totGap                    559961438500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -93,8 +93,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290734                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       486                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       104630                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      218.912664                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     140.833166                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     269.609760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          39535     37.79%     37.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43904     41.96%     79.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8672      8.29%     88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          695      0.66%     88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          728      0.70%     89.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          763      0.73%     90.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1332      1.27%     91.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          808      0.77%     92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8193      7.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         104630                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       104680                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      218.802598                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     140.854989                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     269.267896                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          39513     37.75%     37.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43924     41.96%     79.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8711      8.32%     88.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          724      0.69%     88.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          705      0.67%     89.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          815      0.78%     90.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1323      1.26%     91.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          784      0.75%     92.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8181      7.82%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         104680                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          4042                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.196437                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.192949                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      784.958027                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        71.196932                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.193109                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      784.958037                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-2047           4035     99.83%     99.83% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::12288-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14336-16383            4      0.10%     99.95% # Reads before turning the bus around for writes
@@ -221,12 +221,12 @@ system.physmem.wrPerTurnAround::16               3047     75.38%     75.38% # Wr
 system.physmem.wrPerTurnAround::18                992     24.54%     99.93% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            4042                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2990654250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8451573000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1456245000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10268.38                       # Average queueing delay per DRAM burst
+system.physmem.totQLat                     2985206750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8446163000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1456255000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10249.60                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29018.38                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28999.60                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          33.29                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.62                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       33.32                       # Average system read bandwidth in MiByte/s
@@ -237,35 +237,40 @@ system.physmem.busUtilRead                       0.26                       # Da
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.50                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202814                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50461                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.64                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1563271.35                       # Average gap between requests
-system.physmem.pageHitRate                      70.76                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     275670988500                       # Time in different power states
-system.physmem.memoryStateTime::REF       18698420000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      265594606500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 393989400                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 396952920                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 214974375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 216591375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1136974800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1134400800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               216438480                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               215550720                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           36574109520                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           36574109520                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          108415975050                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          108760602465                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          240876668250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          240574363500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            387829129875                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            387872571300                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             692.596540                       # Core power per rank (mW)
-system.physmem.averagePower::1             692.674119                       # Core power per rank (mW)
+system.physmem.readRowHits                     202789                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50437                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.63                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1563256.04                       # Average gap between requests
+system.physmem.pageHitRate                      70.75                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  394057440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  215011500                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1136889000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            36573600960                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           108420572385                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           240867963750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             387824533515                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              692.597962                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   400029552000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18698160000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    141228516750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  397232640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  216744000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1134299400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215550720                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            36573600960                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           108773347950                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           240558511500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             387869287170                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.677886                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   399509975000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18698160000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    141748516500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups               125749069                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          81144276                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          12157130                       # Number of conditional branches incorrect
@@ -309,24 +314,24 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1119933999                       # number of cpu cycles simulated
+system.cpu.numCycles                       1119923029                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                      27043480                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.205800                       # CPI: cycles per instruction
-system.cpu.ipc                               0.829325                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1060170405                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        59763594                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.205788                       # CPI: cycles per instruction
+system.cpu.ipc                               0.829333                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1060170406                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        59752623                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            776532                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.890193                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4092.890165                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           323503178                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780628                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            414.414008                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         845912250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.890193                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.890165                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999241                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999241                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -354,14 +359,14 @@ system.cpu.dcache.demand_misses::cpu.inst       849082                       # n
 system.cpu.dcache.demand_misses::total         849082                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst       849082                       # number of overall misses
 system.cpu.dcache.overall_misses::total        849082                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23415653250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  23415653250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9042894000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9042894000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  32458547250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  32458547250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  32458547250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  32458547250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23417135750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  23417135750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9028767000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9028767000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  32445902750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32445902750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  32445902750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32445902750                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst    226051060                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    226051060                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     98301200                       # number of WriteReq accesses(hits+misses)
@@ -378,14 +383,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.002618
 system.cpu.dcache.demand_miss_rate::total     0.002618                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.002618                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002618                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38227.812214                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38227.812214                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38212.920248                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38212.920248                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -412,14 +417,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst       780628
 system.cpu.dcache.demand_mshr_misses::total       780628                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst       780628                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780628                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21914188000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21914188000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4452805750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4452805750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26366993750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26366993750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26366993750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26366993750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21915650000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21915650000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4445743250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4445743250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26361393250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26361393250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26361393250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26361393250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.003148                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003148                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for WriteReq accesses
@@ -428,22 +433,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002407
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002407                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002407                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002407                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10606                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1687.447542                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1687.447497                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           317126411                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             12349                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          25680.331282                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1687.447542                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1687.447497                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.823949                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.823949                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1743                       # Occupied blocks per task id
@@ -467,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst        12350                       # n
 system.cpu.icache.demand_misses::total          12350                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        12350                       # number of overall misses
 system.cpu.icache.overall_misses::total         12350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    333735500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    333735500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    333735500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    333735500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    333735500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    333735500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    333924000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    333924000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    333924000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    333924000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    333924000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    333924000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    317138761                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    317138761                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    317138761                       # number of demand (read+write) accesses
@@ -485,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000039
 system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27023.117409                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27023.117409                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 27038.380567                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 27038.380567                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -505,41 +510,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        12350
 system.cpu.icache.demand_mshr_misses::total        12350                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        12350                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        12350                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    307779500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    307779500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    307779500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    307779500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    307779500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    307779500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    307968000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    307968000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    307968000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    307968000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    307968000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    307968000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           258740                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32601.453126                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        32601.451844                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             523849                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           291476                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             1.797229                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2865.906217                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks  2865.934205                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.087461                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907457                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907456                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.994917                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          274                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2658                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          275                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2657                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29474                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          7436223                       # Number of tag accesses
@@ -562,14 +567,14 @@ system.cpu.l2cache.demand_misses::cpu.inst       291520                       #
 system.cpu.l2cache.demand_misses::total        291520                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst       291520                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       291520                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16507068000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  16507068000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4360106750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4360106750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  20867174750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  20867174750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  20867174750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20867174750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16508718500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  16508718500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4353044250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4353044250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  20861762750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20861762750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  20861762750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20861762750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       723967                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       723967                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks        91489                       # number of Writeback accesses(hits+misses)
@@ -588,14 +593,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.367627
 system.cpu.l2cache.demand_miss_rate::total     0.367627                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.367627                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.367627                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -614,14 +619,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst       291520
 system.cpu.l2cache.demand_mshr_misses::total       291520                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst       291520                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       291520                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13668599500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13668599500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3526847250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3526847250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  17195446750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  17195446750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  17195446750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  17195446750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13670285000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13670285000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3519774750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3519774750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  17190059750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  17190059750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  17190059750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  17190059750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.310615                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.310615                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.965716                       # mshr miss rate for ReadExReq accesses
@@ -630,14 +635,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.367627
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.367627                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.367627                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.367627                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         723967                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        723966                       # Transaction distribution
@@ -666,7 +671,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy      533722500                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      19152500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1222199250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1222191750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq              224874                       # Transaction distribution
 system.membus.trans_dist::ReadResp             224874                       # Transaction distribution
@@ -688,9 +693,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              358202                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           975509000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           975503000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2745284750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2745267250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.541781                       # Number of seconds simulated
-sim_ticks                                541781076000                       # Number of ticks simulated
-final_tick                               541781076000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.541786                       # Number of seconds simulated
+sim_ticks                                541786101000                       # Number of ticks simulated
+final_tick                               541786101000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140173                       # Simulator instruction rate (inst/s)
-host_op_rate                                   172571                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              118539448                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261676                       # Number of bytes of host memory used
-host_seconds                                  4570.47                       # Real time elapsed on the host
+host_inst_rate                                 183531                       # Simulator instruction rate (inst/s)
+host_op_rate                                   225950                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              155207340                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320704                       # Number of bytes of host memory used
+host_seconds                                  3490.72                       # Real time elapsed on the host
 sim_insts                                   640655084                       # Number of instructions simulated
 sim_ops                                     788730743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst             290529                       # Nu
 system.physmem.num_reads::total                290529                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             34319870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34319870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          303946                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             303946                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7808084                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7808084                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7808084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            34319870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42127954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             34319552                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                34319552                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          303943                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             303943                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7808011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                7808011                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7808011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            34319552                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42127563                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        290529                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
 system.physmem.readBursts                      290529                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18573248                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20608                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                 18572736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21120                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                   4228480                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  18593856                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      322                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      330                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18288                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18139                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18224                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18182                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18264                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18315                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18098                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18289                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18137                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18222                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18184                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18266                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18308                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18094                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               17914                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               17936                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               17963                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18015                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               17939                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               17962                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18018                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              18110                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18146                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18075                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18267                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18143                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18270                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18266                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4101                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
@@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    541780987500                       # Total gap between requests
+system.physmem.totGap                    541786012500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -93,9 +93,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    289809                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       381                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    289803                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       380                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      986                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      989                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4007                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4007                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                     4008                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4007                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4007                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4006                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4006                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -189,42 +189,44 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       111520                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      204.445337                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     132.546078                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.289579                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          46919     42.07%     42.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43694     39.18%     81.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8696      7.80%     89.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          722      0.65%     89.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1258      1.13%     90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1255      1.13%     91.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          576      0.52%     92.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          502      0.45%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         7898      7.08%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         111520                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.543798                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       36.072613                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      507.664819                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       111554                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      204.382452                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     132.554579                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     255.928936                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          47007     42.14%     42.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43571     39.06%     81.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8721      7.82%     89.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          769      0.69%     89.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1361      1.22%     90.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1221      1.09%     92.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          537      0.48%     92.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          497      0.45%     92.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7870      7.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         111554                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4006                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.553919                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.073633                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      507.732262                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4003     99.93%     99.93% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.488645                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.467122                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.859477                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3028     75.57%     75.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                979     24.43%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2702187250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8143568500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1451035000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9311.24                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4006                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4006                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.492761                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.471115                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.861913                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3018     75.34%     75.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     75.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                984     24.56%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4006                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2707676000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8148907250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1450995000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9330.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28061.24                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  28080.41                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          34.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       34.32                       # Average system read bandwidth in MiByte/s
@@ -235,35 +237,40 @@ system.physmem.busUtilRead                       0.27                       # Da
 system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        26.42                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194639                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     50105                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   67.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  75.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1519181.07                       # Average gap between requests
-system.physmem.pageHitRate                      68.69                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     263887343000                       # Time in different power states
-system.physmem.memoryStateTime::REF       18091060000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT      259796939500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                 421530480                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                 421462440                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                 230001750                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                 229964625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0               1134174600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1               1128987600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0               215628480                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1               212505120                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0           35386113360                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1           35386113360                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0          105979651695                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1          105556941405                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0          232100586000                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1          232471384500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0            375467686365                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1            375407359050                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             693.032096                       # Core power per rank (mW)
-system.physmem.averagePower::1             692.920745                       # Core power per rank (mW)
+system.physmem.readRowHits                     194608                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50098                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   67.06                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1519195.16                       # Average gap between requests
+system.physmem.pageHitRate                      68.68                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  421810200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  230154375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1134190200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215628480                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            35386621920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           106352983170                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           231777774000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             375519162345                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              693.117148                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   384873582500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     18091320000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    138818819500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                  421477560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  229972875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1129034400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212505120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            35386621920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           105425199585                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           232591619250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             375396430710                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              692.890615                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   386233048000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     18091320000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    137458753250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups               156937341                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         106680042                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          12891228                       # Number of conditional branches incorrect
@@ -274,6 +281,14 @@ system.cpu.branchPred.BTBHitPct             83.942615                       # BT
 system.cpu.branchPred.usedRAS                19487919                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               1320                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -295,6 +310,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -316,6 +339,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -337,6 +368,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -359,24 +398,24 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1083562152                       # number of cpu cycles simulated
+system.cpu.numCycles                       1083572202                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655084                       # Number of instructions committed
 system.cpu.committedOps                     788730743                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                      22655429                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.691335                       # CPI: cycles per instruction
-system.cpu.ipc                               0.591249                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1029140125                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        54422027                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.691350                       # CPI: cycles per instruction
+system.cpu.ipc                               0.591244                       # IPC: instructions per cycle
+system.cpu.tickCycles                      1029141566                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        54430636                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            778221                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.644165                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4092.645412                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs           378457747                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            782317                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            483.765209                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         752182250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.644165                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         751751250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst  4092.645412                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.999181                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999181                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -408,14 +447,14 @@ system.cpu.dcache.demand_misses::cpu.inst       851460                       # n
 system.cpu.dcache.demand_misses::total         851460                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst       851460                       # number of overall misses
 system.cpu.dcache.overall_misses::total        851460                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23050728217                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  23050728217                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9196889000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9196889000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  32247617217                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  32247617217                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  32247617217                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  32247617217                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst  23055853217                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  23055853217                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst   9199211000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9199211000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst  32255064217                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32255064217                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst  32255064217                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32255064217                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst    250346252                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    250346252                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst    128951477                       # number of WriteReq accesses(hits+misses)
@@ -436,14 +475,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.002245
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.002245                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32295.376677                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32295.376677                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66783.012497                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66783.012497                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37873.320199                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37873.320199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37873.320199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37873.320199                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32302.557092                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66799.873650                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37882.066353                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37882.066353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37882.066353                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37882.066353                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -470,14 +509,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst       782317
 system.cpu.dcache.demand_mshr_misses::total       782317                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst       782317                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       782317                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21540338778                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21540338778                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4529678750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4529678750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26070017528                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26070017528                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26070017528                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26070017528                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst  21545578028                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21545578028                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst   4531082000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4531082000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  26076660028                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26076660028                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  26076660028                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26076660028                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000538                       # mshr miss rate for WriteReq accesses
@@ -486,22 +525,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.002063
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30211.065685                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30211.065685                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65342.586048                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65342.586048                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33324.109700                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 33324.109700                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33324.109700                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 33324.109700                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30218.413913                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65362.828539                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33332.600503                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33332.600503                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             23590                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1712.180354                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           289921724                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1712.180561                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           289921723                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             25341                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11440.816227                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11440.816187                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1712.180354                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1712.180561                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.836026                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.836026                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
@@ -509,44 +548,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0           57
 system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1602                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         579919473                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        579919473                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    289921724                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       289921724                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     289921724                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        289921724                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    289921724                       # number of overall hits
-system.cpu.icache.overall_hits::total       289921724                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         579919471                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        579919471                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    289921723                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       289921723                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     289921723                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        289921723                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    289921723                       # number of overall hits
+system.cpu.icache.overall_hits::total       289921723                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        25342                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         25342                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        25342                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          25342                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        25342                       # number of overall misses
 system.cpu.icache.overall_misses::total         25342                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    481750746                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    481750746                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    481750746                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    481750746                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    481750746                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    481750746                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    289947066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    289947066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    289947066                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    289947066                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    289947066                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    289947066                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    480693746                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    480693746                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    480693746                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    480693746                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    480693746                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    480693746                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    289947065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    289947065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    289947065                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    289947065                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    289947065                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    289947065                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19009.973404                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19009.973404                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19009.973404                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19009.973404                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19009.973404                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19009.973404                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18968.263989                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18968.263989                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -561,36 +600,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        25342
 system.cpu.icache.demand_mshr_misses::total        25342                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        25342                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        25342                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429966254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    429966254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429966254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    429966254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429966254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    429966254                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    428909254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    428909254                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    428909254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    428909254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    428909254                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    428909254                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16966.547786                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16966.547786                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16966.547786                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16966.547786                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           257749                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32583.074549                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        32583.111771                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             539070                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           290493                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             1.855707                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2860.585859                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.488690                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.087298                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907058                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994357                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2860.665235                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 29722.446536                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.087301                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.907057                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994358                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
@@ -618,14 +657,14 @@ system.cpu.l2cache.demand_misses::cpu.inst       290562                       #
 system.cpu.l2cache.demand_misses::total        290562                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst       290562                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       290562                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16093224000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  16093224000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4428044750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4428044750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  20521268750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  20521268750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  20521268750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20521268750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst  16097406250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  16097406250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   4429448000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4429448000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst  20526854250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20526854250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst  20526854250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20526854250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       738337                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       738337                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks        91420                       # number of Writeback accesses(hits+misses)
@@ -644,14 +683,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.359758
 system.cpu.l2cache.demand_miss_rate::total     0.359758                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.359758                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.359758                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71694.000561                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71694.000561                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66999.209423                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66999.209423                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70626.127126                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70626.127126                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70626.127126                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70626.127126                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71712.632144                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67020.441512                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70645.350218                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70645.350218                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -676,14 +715,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst       290530
 system.cpu.l2cache.demand_mshr_misses::total       290530                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst       290530                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       290530                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13281416250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13281416250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3575940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3575940250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  16857356500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  16857356500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  16857356500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  16857356500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst  13285316750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13285316750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   3577310000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3577310000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  16862626750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  16862626750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  16862626750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  16862626750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.303979                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.303979                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.953391                       # mshr miss rate for ReadExReq accesses
@@ -692,14 +731,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.359719
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.359719                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.359719                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.359719                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59176.062315                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59176.062315                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54106.311752                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54106.311752                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58022.773896                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58022.773896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58022.773896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58022.773896                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59193.441202                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54127.036964                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58040.914019                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58040.914019                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         738337                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        738336                       # Transaction distribution
@@ -732,7 +771,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy      540959500                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy      38562746                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1224341972                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1224351972                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq              224438                       # Transaction distribution
 system.membus.trans_dist::ReadResp             224438                       # Transaction distribution
@@ -754,9 +793,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total              356627                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           983533000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           983550500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2738969000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2739032750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.395727                       # Nu
 sim_ticks                                395726778000                       # Number of ticks simulated
 final_tick                               395726778000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1695212                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2087030                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1047118075                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304696                       # Number of bytes of host memory used
-host_seconds                                   377.92                       # Real time elapsed on the host
+host_inst_rate                                1395078                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1717525                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              861727739                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309420                       # Number of bytes of host memory used
+host_seconds                                   459.22                       # Real time elapsed on the host
 sim_insts                                   640654410                       # Number of instructions simulated
 sim_ops                                     788730069                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total             1322421029                       # Wr
 system.physmem.bw_total::cpu.inst          6503253596                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          4215120183                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            10718373779                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           893703777                       # Transaction distribution
-system.membus.trans_dist::ReadResp          893709516                       # Transaction distribution
-system.membus.trans_dist::WriteReq          128951477                       # Transaction distribution
-system.membus.trans_dist::WriteResp         128951477                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq              3620                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp             3620                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq          5739                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq           5739                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp          5739                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1286755796                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    758584908                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             2045340704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2573511592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1668035929                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              4241547521                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples        1022670352                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.629116                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.483042                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4               379292454     37.09%     37.09% # Request fanout histogram
-system.membus.snoop_fanout::5               643377898     62.91%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total          1022670352                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  788730743                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           893703777                       # Transaction distribution
+system.membus.trans_dist::ReadResp          893709516                       # Transaction distribution
+system.membus.trans_dist::WriteReq          128951477                       # Transaction distribution
+system.membus.trans_dist::WriteResp         128951477                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq              3620                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp             3620                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq          5739                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq           5739                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp          5739                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   1286755796                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port    758584908                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total             2045340704                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   2573511592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   1668035929                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              4241547521                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples        1022670352                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.629116                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.483042                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4               379292454     37.09%     37.09% # Request fanout histogram
+system.membus.snoop_fanout::5               643377898     62.91%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total          1022670352                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  1.043695                       # Nu
 sim_ticks                                1043695084000                       # Number of ticks simulated
 final_tick                               1043695084000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 974812                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1197616                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1591272225                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314196                       # Number of bytes of host memory used
-host_seconds                                   655.89                       # Real time elapsed on the host
+host_inst_rate                                 894518                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1098969                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1460200235                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317628                       # Number of bytes of host memory used
+host_seconds                                   714.76                       # Real time elapsed on the host
 sim_insts                                   639366786                       # Number of instructions simulated
 sim_ops                                     785501034                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks           4053168                       # To
 system.physmem.bw_total::cpu.inst              108537                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            17656774                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               21818480                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq              223619                       # Transaction distribution
-system.membus.trans_dist::ReadResp             223619                       # Transaction distribution
-system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       645522                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 645522                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22771840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22771840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            355811                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  355811    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              355811                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           884977500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2607766500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -206,6 +214,145 @@ system.cpu.op_class::MemWrite               128980497     16.35%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  788730743                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            778046                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4093.640576                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         996417000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640576                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          591                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1036                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         759367050                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759367050                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249613198                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249613198                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128882154                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128882154                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3481                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3481                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     378495352                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378495352                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378498833                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378498833                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       712681                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        712681                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        69323                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        69323                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          139                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          139                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       782004                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
+system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582698000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18582698000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677152000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3677152000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22259850000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22259850000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22259850000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22259850000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3620                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3620                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    379277356                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379277356                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379280976                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379280976                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002847                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002847                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000538                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000538                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038398                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038398                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 28465.135728                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 28460.076994                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks        91561                       # number of writebacks
+system.cpu.dcache.writebacks::total             91561                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712680                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712680                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        69323                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       782003                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17157298000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17157298000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3538506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3538506000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1613000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1613000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20695804000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  20695804000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20697417000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  20697417000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038398                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038398                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              8769                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1391.464499                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           643367691                       # Total number of references to valid blocks.
@@ -438,145 +585,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            778046                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4093.640576                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378510311                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782142                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.940654                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         996417000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4093.640576                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999424                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999424                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          123                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          591                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1036                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2319                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759367050                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759367050                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249613198                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249613198                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128882154                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128882154                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3481                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3481                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378495352                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378495352                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378498833                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378498833                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       712681                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        712681                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        69323                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        69323                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          139                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          139                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       782004                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         782004                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       782143                       # number of overall misses
-system.cpu.dcache.overall_misses::total        782143                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18582698000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18582698000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   3677152000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   3677152000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22259850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22259850000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22259850000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22259850000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250325879                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250325879                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3620                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3620                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379277356                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379277356                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379280976                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379280976                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002847                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002847                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000538                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000538                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038398                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.038398                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002062                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002062                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002062                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002062                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28465.135728                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28460.076994                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        91561                       # number of writebacks
-system.cpu.dcache.writebacks::total             91561                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712680                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712680                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69323                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        69323                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782003                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782003                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782142                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17157298000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17157298000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3538506000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3538506000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1613000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1613000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  20695804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  20695804000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  20697417000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  20697417000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038398                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038398                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq         723027                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp        723027                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback        91561                       # Transaction distribution
@@ -610,5 +618,29 @@ system.cpu.toL2Bus.respLayer0.occupancy      15312000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1173213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq              223619                       # Transaction distribution
+system.membus.trans_dist::ReadResp             223619                       # Transaction distribution
+system.membus.trans_dist::Writeback             66098                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66093                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66093                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       645522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 645522                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22771840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22771840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            355811                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  355811    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              355811                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           884977500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2607766500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.048960                       # Nu
 sim_ticks                                 48960011000                       # Number of ticks simulated
 final_tick                                48960011000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 264072                       # Simulator instruction rate (inst/s)
-host_op_rate                                   337712                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              182321320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304496                       # Number of bytes of host memory used
-host_seconds                                   268.54                       # Real time elapsed on the host
+host_inst_rate                                1376675                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1760576                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              950486092                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308184                       # Number of bytes of host memory used
+host_seconds                                    51.51                       # Real time elapsed on the host
 sim_insts                                    70913181                       # Number of instructions simulated
 sim_ops                                      90688136                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total             1606621596                       # Wr
 system.physmem.bw_total::cpu.inst          6384399546                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3783364264                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            10167763810                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           100925135                       # Transaction distribution
-system.membus.trans_dist::ReadResp          100941054                       # Transaction distribution
-system.membus.trans_dist::WriteReq           19849901                       # Transaction distribution
-system.membus.trans_dist::WriteResp          19849901                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq            123744                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp           123744                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq         15919                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq          15919                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp         15919                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    156290136                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     85571100                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              241861236                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    312580272                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    185233556                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               497813828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         120930618                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.646198                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.478149                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                42785550     35.38%     35.38% # Request fanout histogram
-system.membus.snoop_fanout::5                78145068     64.62%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total           120930618                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   90690083                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           100925135                       # Transaction distribution
+system.membus.trans_dist::ReadResp          100941054                       # Transaction distribution
+system.membus.trans_dist::WriteReq           19849901                       # Transaction distribution
+system.membus.trans_dist::WriteResp          19849901                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq            123744                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp           123744                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq         15919                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq          15919                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp         15919                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    156290136                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     85571100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total              241861236                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    312580272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    185233556                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               497813828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples         120930618                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.646198                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.478149                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                42785550     35.38%     35.38% # Request fanout histogram
+system.membus.snoop_fanout::5                78145068     64.62%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total           120930618                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.127294                       # Nu
 sim_ticks                                127293983000                       # Number of ticks simulated
 final_tick                               127293983000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 949441                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1212170                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1717378261                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 313972                       # Number of bytes of host memory used
-host_seconds                                    74.12                       # Real time elapsed on the host
+host_inst_rate                                 894668                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1142240                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1618302823                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317432                       # Number of bytes of host memory used
+host_seconds                                    78.66                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
 sim_ops                                      89847362                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks          42187194                       # To
 system.physmem.bw_total::cpu.inst             2007071                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            62253375                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              106447639                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq               25532                       # Transaction distribution
-system.membus.trans_dist::ReadResp              25532                       # Transaction distribution
-system.membus.trans_dist::Writeback             83909                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       339533                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 339533                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13550144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13550144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            214631                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  214631    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              214631                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           895030780                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1156019000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -206,6 +214,143 @@ system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   90690083                       # Class of executed instruction
+system.cpu.dcache.tags.replacements            155902                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4076.389354                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42608166                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            266.304366                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1061073000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389354                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995212                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995212                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3191                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22749836                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22749836                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83623                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83623                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      42492705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42492705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42576328                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42576328                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        30231                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         30231                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        40121                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        40121                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       137263                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         137263                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       177384                       # number of overall misses
+system.cpu.dcache.overall_misses::total        177384                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    516746500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    516746500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689859500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5689859500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   6206606000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   6206606000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   6206606000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   6206606000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       123744                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       123744                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     42629968                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42629968                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42753712                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42753712                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001327                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.001327                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324226                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.324226                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003220                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.003220                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004149                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.004149                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45216.890203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34989.660849                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       128239                       # number of writebacks
+system.cpu.dcache.writebacks::total            128239                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1123                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1123                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1123                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1123                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1123                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1123                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23858                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23858                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136140                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    443576500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    443576500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5475795500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5475795500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1053888500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1053888500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5919372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5919372000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6973260500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6973260500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.192801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.192801                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             16890                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1733.675052                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126161                       # Total number of references to valid blocks.
@@ -439,143 +584,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            155902                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.389354                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42608166                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            159998                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            266.304366                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1061073000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.389354                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995212                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995212                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          856                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3191                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22749836                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22749836                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83623                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83623                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42492705                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42492705                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42576328                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42576328                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        30231                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         30231                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        40121                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        40121                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       137263                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         137263                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       177384                       # number of overall misses
-system.cpu.dcache.overall_misses::total        177384                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    516746500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    516746500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   5689859500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   5689859500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   6206606000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   6206606000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   6206606000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   6206606000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22780067                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22780067                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       123744                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       123744                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42629968                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42629968                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42753712                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42753712                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001327                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.001327                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.324226                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.324226                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.003220                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.003220                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.004149                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.004149                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45216.890203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34989.660849                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128239                       # number of writebacks
-system.cpu.dcache.writebacks::total            128239                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1123                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1123                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1123                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1123                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1123                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1123                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29108                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29108                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23858                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23858                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136140                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136140                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    443576500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    443576500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5475795500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5475795500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1053888500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1053888500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5919372000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5919372000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6973260500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6973260500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001278                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.192801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.192801                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003194                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003194                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq          71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       128239                       # Transaction distribution
@@ -609,5 +617,29 @@ system.cpu.toL2Bus.respLayer0.occupancy      28362000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     239997000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq               25532                       # Transaction distribution
+system.membus.trans_dist::ReadResp              25532                       # Transaction distribution
+system.membus.trans_dist::Writeback             83909                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102280                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102280                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       339533                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 339533                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13550144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13550144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples            214631                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  214631    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total              214631                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           895030780                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1156019000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.832017                       # Nu
 sim_ticks                                832017490000                       # Number of ticks simulated
 final_tick                               832017490000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2048371                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2206809                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1103406177                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296712                       # Number of bytes of host memory used
-host_seconds                                   754.04                       # Real time elapsed on the host
+host_inst_rate                                1680600                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1810592                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              905297170                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 301428                       # Number of bytes of host memory used
+host_seconds                                   919.05                       # Real time elapsed on the host
 sim_insts                                  1544563041                       # Number of instructions simulated
 sim_ops                                    1664032433                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total              750174605                       # Wr
 system.physmem.bw_total::cpu.inst          7425640002                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          2650840985                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            10076480987                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq          1999474724                       # Transaction distribution
-system.membus.trans_dist::ReadResp         1999474785                       # Transaction distribution
-system.membus.trans_dist::WriteReq          172586047                       # Transaction distribution
-system.membus.trans_dist::WriteResp         172586047                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq                 1                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp                1                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq            61                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq             61                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp            61                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   3089131178                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port   1254990610                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total             4344121788                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   6178262356                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   2205546063                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total              8383808419                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples        2172060894                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.711106                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.453249                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4               627495305     28.89%     28.89% # Request fanout histogram
-system.membus.snoop_fanout::5              1544565589     71.11%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total          2172060894                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032480                       # Class of executed instruction
+system.membus.trans_dist::ReadReq          1999474724                       # Transaction distribution
+system.membus.trans_dist::ReadResp         1999474785                       # Transaction distribution
+system.membus.trans_dist::WriteReq          172586047                       # Transaction distribution
+system.membus.trans_dist::WriteResp         172586047                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq                 1                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp                1                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq            61                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq             61                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp            61                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port   3089131178                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port   1254990610                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total             4344121788                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port   6178262356                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port   2205546063                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total              8383808419                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples        2172060894                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.711106                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.453249                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4               627495305     28.89%     28.89% # Request fanout histogram
+system.membus.snoop_fanout::5              1544565589     71.11%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total          2172060894                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  2.363671                       # Nu
 sim_ticks                                2363670998000                       # Number of ticks simulated
 final_tick                               2363670998000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1205605                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1299208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1851916301                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306192                       # Number of bytes of host memory used
-host_seconds                                  1276.34                       # Real time elapsed on the host
+host_inst_rate                                1113267                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1199701                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1710076181                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309628                       # Number of bytes of host memory used
+host_seconds                                  1382.20                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
 sim_ops                                    1658228914                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks          27542188                       # To
 system.physmem.bw_total::cpu.inst               16679                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            53020117                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               80578984                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq             1177898                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1177898                       # Transaction distribution
-system.membus.trans_dist::Writeback           1017198                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780876                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780876                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4934746                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4934746                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190462208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190462208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           2975972                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2975972    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             2975972                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         11138507500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        17642613000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -206,6 +214,137 @@ system.cpu.op_class::MemWrite               174847046     10.51%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 1664032480                       # Class of executed instruction
+system.cpu.dcache.tags.replacements           9111140                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4083.733705                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       25164666000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733705                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1213                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1264105846                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1264105846                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    447683049                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       447683049                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170696898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     618379947                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        618379947                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    618379947                       # number of overall hits
+system.cpu.dcache.overall_hits::total       618379947                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7226086                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7226086                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1889149                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1889149                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      9115235                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9115235                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143405400500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57359071000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57359071000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200764471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200764471500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200764471500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200764471500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    454909135                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data            1                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total            1                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    627495182                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    627495182                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    627495183                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    627495183                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015885                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.015885                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.014526                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.014526                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.014526                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22025.155852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22025.153435                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks      3697418                       # number of writebacks
+system.cpu.dcache.writebacks::total           3697418                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7226086                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9115235                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9115235                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53580773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  53580773000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182534001500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182534054500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total            1                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 7                       # number of replacements
 system.cpu.icache.tags.tagsinuse           515.012865                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1544564952                       # Total number of references to valid blocks.
@@ -438,137 +577,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9111140                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4083.733705                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           618380069                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9115236                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.840270                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       25164666000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4083.733705                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997005                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997005                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1213                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1264105846                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1264105846                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    447683049                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       447683049                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170696898                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     618379947                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        618379947                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    618379947                       # number of overall hits
-system.cpu.dcache.overall_hits::total       618379947                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7226086                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7226086                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1889149                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1889149                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9115235                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9115235                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143405400500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57359071000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57359071000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200764471500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200764471500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200764471500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200764471500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    454909135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    454909135                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data            1                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total            1                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    627495182                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    627495182                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    627495183                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    627495183                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015885                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.015885                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010946                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.014526                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.014526                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.014526                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.014526                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22025.155852                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22025.153435                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3697418                       # number of writebacks
-system.cpu.dcache.writebacks::total           3697418                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226086                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7226086                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1889149                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9115235                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9115235                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  53580773000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  53580773000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182534001500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182534054500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015885                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015885                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total            1                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014526                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014526                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014526                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq        7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp       7226725                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback      3697418                       # Transaction distribution
@@ -602,5 +610,29 @@ system.cpu.toL2Bus.respLayer0.occupancy        957000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy   13672854000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.6                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq             1177898                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1177898                       # Transaction distribution
+system.membus.trans_dist::Writeback           1017198                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780876                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780876                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4934746                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4934746                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190462208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190462208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples           2975972                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 2975972    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total             2975972                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         11138507500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy        17642613000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.052167                       # Nu
 sim_ticks                                 52167245000                       # Number of ticks simulated
 final_tick                                52167245000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 231551                       # Simulator instruction rate (inst/s)
-host_op_rate                                   231551                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              131435822                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240584                       # Number of bytes of host memory used
-host_seconds                                   396.90                       # Real time elapsed on the host
+host_inst_rate                                 368966                       # Simulator instruction rate (inst/s)
+host_op_rate                                   368966                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              209437459                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299464                       # Number of bytes of host memory used
+host_seconds                                   249.08                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -86,8 +86,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4913                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       386                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          974                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      348.254620                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     211.254822                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.143137                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            322     33.06%     33.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          190     19.51%     52.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           96      9.86%     62.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          102     10.47%     72.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           61      6.26%     79.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           36      3.70%     82.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           25      2.57%     85.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           25      2.57%     87.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          117     12.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            974                       # Bytes accessed per row activation
-system.physmem.totQLat                       31955000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 131667500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          972                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.971193                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     211.834828                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     332.374999                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            320     32.92%     32.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          191     19.65%     52.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           96      9.88%     62.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           99     10.19%     72.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           63      6.48%     79.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           36      3.70%     82.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           24      2.47%     85.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           26      2.67%     87.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          117     12.04%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            972                       # Bytes accessed per row activation
+system.physmem.totQLat                       32099750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 131812250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26590000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6008.84                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6036.06                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24758.84                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24786.06                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.52                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.52                       # Average system read bandwidth in MiByte/s
@@ -212,43 +212,48 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4336                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4338                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.53                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.57                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                      9809545.60                       # Average gap between requests
-system.physmem.pageHitRate                      81.53                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      49062382500                       # Time in different power states
-system.physmem.memoryStateTime::REF        1741740000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1356240000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   3530520                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   3787560                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   1926375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2066625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 19827600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 21216000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            3406843440                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            3406843440                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            1740241350                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            1807017705                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           29769681750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           29711106000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             34942051035                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             34952037330                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             669.896806                       # Core power per rank (mW)
-system.physmem.averagePower::1             670.088260                       # Core power per rank (mW)
-system.cpu.branchPred.lookups                11476347                       # Number of BP lookups
+system.physmem.pageHitRate                      81.57                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3530520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1926375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19827600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3406843440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1740830445                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29769165000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34942123380                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.898193                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49520504500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1741740000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       898118000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    3772440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2058375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3406843440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1807143390                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29710995750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34952029395                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.088108                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49425818250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1741740000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       995309750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.cpu.branchPred.lookups                11476348                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           8235349                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            785844                       # Number of conditional branches incorrect
 system.cpu.branchPred.BTBLookups              6672654                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                 5371509                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.branchPred.BTBHitPct             80.500338                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1176736                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.usedRAS                 1176737                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
@@ -267,10 +272,10 @@ system.cpu.dtb.data_hits                     26977004                       # DT
 system.cpu.dtb.data_misses                      47407                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
 system.cpu.dtb.data_accesses                 27024411                       # DTB accesses
-system.cpu.itb.fetch_hits                    23068125                       # ITB hits
+system.cpu.itb.fetch_hits                    23068130                       # ITB hits
 system.cpu.itb.fetch_misses                        88                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                23068213                       # ITB accesses
+system.cpu.itb.fetch_accesses                23068218                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,15 +298,15 @@ system.cpu.discardedOps                       2153944                       # Nu
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
 system.cpu.cpi                               1.135266                       # CPI: cycles per instruction
 system.cpu.ipc                               0.880851                       # IPC: instructions per cycle
-system.cpu.tickCycles                       102681426                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         1653064                       # Total number of cycles that the object has spent stopped
+system.cpu.tickCycles                       102681434                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1653056                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1448.700924                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1448.700214                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            26568138                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          11913.963229                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.700924                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1448.700214                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.353687                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.353687                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
@@ -329,14 +334,14 @@ system.cpu.dcache.demand_misses::cpu.inst         3430                       # n
 system.cpu.dcache.demand_misses::total           3430                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst         3430                       # number of overall misses
 system.cpu.dcache.overall_misses::total          3430                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst     37712750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     37712750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    194587500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    194587500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    232300250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    232300250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    232300250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    232300250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst     37684500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     37684500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    195045500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    195045500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    232730000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    232730000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    232730000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    232730000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst     20070465                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20070465                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst      6501103                       # number of WriteReq accesses(hits+misses)
@@ -353,14 +358,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.000129
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72664.258189                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72664.258189                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66845.585709                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66845.585709                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67726.020408                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 67726.020408                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67726.020408                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 67726.020408                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67002.919959                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67851.311953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67851.311953                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -387,14 +392,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     34134000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34134000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    117191500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    117191500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    151325500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    151325500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    151325500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    151325500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     34103500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34103500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    117640500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    117640500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    151744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    151744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    151744000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    151744000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000268                       # mshr miss rate for WriteReq accesses
@@ -403,24 +408,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70379.381443                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70379.381443                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67158.452722                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67158.452722                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67858.968610                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67858.968610                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67858.968610                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67858.968610                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67415.759312                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             13871                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.666168                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            23052289                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1640.665289                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            23052294                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             15835                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1455.780802                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1455.781118                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.666168                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801107                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801107                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.665289                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801106                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801106                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1964                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
@@ -428,44 +433,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          669
 system.cpu.icache.tags.age_task_id_blocks_1024::3          148                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          948                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.958984                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          46152085                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         46152085                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     23052289                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        23052289                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      23052289                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         23052289                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     23052289                       # number of overall hits
-system.cpu.icache.overall_hits::total        23052289                       # number of overall hits
+system.cpu.icache.tags.tag_accesses          46152095                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         46152095                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     23052294                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        23052294                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      23052294                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         23052294                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     23052294                       # number of overall hits
+system.cpu.icache.overall_hits::total        23052294                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        15836                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         15836                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        15836                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          15836                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        15836                       # number of overall misses
 system.cpu.icache.overall_misses::total         15836                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    386603500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    386603500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    386603500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    386603500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    386603500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    386603500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     23068125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     23068125                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     23068125                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     23068125                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     23068125                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     23068125                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    386327750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    386327750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    386327750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    386327750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    386327750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    386327750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     23068130                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     23068130                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     23068130                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     23068130                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     23068130                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     23068130                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000686                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000686                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000686                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000686                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000686                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000686                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24412.951503                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24412.951503                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24412.951503                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24412.951503                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24412.951503                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24412.951503                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24395.538646                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24395.538646                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,33 +485,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        15836
 system.cpu.icache.demand_mshr_misses::total        15836                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        15836                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        15836                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353567500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    353567500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353567500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    353567500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353567500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    353567500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    353292250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    353292250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    353292250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    353292250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    353292250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    353292250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000686                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000686                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000686                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000686                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22326.818641                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22326.818641                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22326.818641                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22326.818641                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2479.834280                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2479.833240                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs              12735                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3665                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             3.474761                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks    17.780071                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2462.054210                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2462.053168                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.075136                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.075679                       # Average percentage of cache occupancy
@@ -537,14 +542,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         5318                       #
 system.cpu.l2cache.demand_misses::total          5318                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         5318                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5318                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    244164500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    244164500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    115186000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    115186000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    359350500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    359350500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    359350500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    359350500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    243859250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    243859250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    115635000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    115635000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    359494250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    359494250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    359494250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    359494250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        16320                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        16320                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
@@ -563,14 +568,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.294381
 system.cpu.l2cache.demand_miss_rate::total     0.294381                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.294381                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.294381                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67842.317310                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 67842.317310                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67007.562536                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67007.562536                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67572.489658                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 67572.489658                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67572.489658                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 67572.489658                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67757.502084                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67268.760908                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67599.520496                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67599.520496                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -587,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         5318
 system.cpu.l2cache.demand_mshr_misses::total         5318                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         5318                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5318                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    198927000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    198927000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     93369000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     93369000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    292296000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    292296000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    292296000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    292296000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    198623250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    198623250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     93817500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     93817500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    292440750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    292440750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    292440750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    292440750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.220527                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.220527                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.985100                       # mshr miss rate for ReadExReq accesses
@@ -603,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.294381
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.294381                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.294381                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.294381                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55272.853570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.853570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54315.881326                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54315.881326                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54963.520120                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54963.520120                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54963.520120                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54963.520120                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55188.455126                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54576.788831                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54990.739000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54990.739000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq          16320                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp         16320                       # Transaction distribution
@@ -637,9 +642,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total          18172                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy        9193000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24435500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      24435250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3734500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3734000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                3599                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3599                       # Transaction distribution
@@ -660,9 +665,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                5318                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6477500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6478000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           50028000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           50027750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.022159                       # Nu
 sim_ticks                                 22159411000                       # Number of ticks simulated
 final_tick                                22159411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173006                       # Simulator instruction rate (inst/s)
-host_op_rate                                   173006                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45541949                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243048                       # Number of bytes of host memory used
-host_seconds                                   486.57                       # Real time elapsed on the host
+host_inst_rate                                 210811                       # Simulator instruction rate (inst/s)
+host_op_rate                                   210811                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               55493646                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299980                       # Number of bytes of host memory used
+host_seconds                                   399.31                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895           35      4.04%     80.48% # By
 system.physmem.bytesPerActivate::896-1023           46      5.31%     85.80% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151          123     14.20%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            866                       # Bytes accessed per row activation
-system.physmem.totQLat                       41291750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 139391750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       41292000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 139392000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26160000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7892.15                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7892.20                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26642.15                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26642.20                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          15.11                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       15.11                       # Average system read bandwidth in MiByte/s
@@ -222,53 +222,34 @@ system.physmem.readRowHitRate                   83.22                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                      4235344.32                       # Average gap between requests
 system.physmem.pageHitRate                      83.22                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE      20543925500                       # Time in different power states
-system.physmem.memoryStateTime::REF         739700000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT         868697500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   3137400                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   3341520                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   1711875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   1823250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 19453200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 20802600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            1446853200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            1446853200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0             893934990                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1             919865430                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           12507131250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           12484385250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             14872221915                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             14877071250                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             671.367239                       # Core power per rank (mW)
-system.physmem.averagePower::1             671.586150                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                3523                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1709                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1709                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10464                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10464                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334848                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5232                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5232    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5232                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6530000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           48921000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                    3137400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1711875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19453200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1446853200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              894020490                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12507056250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14872232415                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.367713                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20804380500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       739700000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       608242500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20802600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1446853200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              920005650                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12484262250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14877088470                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.586927                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20766250250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       739700000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       646430250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                16298030                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          11843884                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            974423                       # Number of conditional branches incorrect
@@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             85.866424                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1608574                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                439                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -314,22 +296,22 @@ system.cpu.workload.num_syscalls                  389                       # Nu
 system.cpu.numCycles                         44318823                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16859440                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles           16859439                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                      139373095                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                    16298030                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches            9227373                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      26218420                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Cycles                      26218422                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                 2029202                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  113                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          2359                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                  16127186                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                380559                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           44094962                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           44094963                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::mean              3.160749                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::stdev             3.432020                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19653197     44.57%     44.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19653198     44.57%     44.57% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                  2660337      6.03%     50.60% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                  1339868      3.04%     53.64% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                  1948475      4.42%     58.06% # Number of instructions fetched each cycle (Total)
@@ -341,11 +323,11 @@ system.cpu.fetch.rateDist::8                 11866174     26.91%    100.00% # Nu
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44094962                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total             44094963                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.branchRate                  0.367745                       # Number of branch fetches per cycle
 system.cpu.fetch.rate                        3.144783                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 13063436                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8246929                       # Number of cycles decode is blocked
+system.cpu.decode.IdleCycles                 13063435                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8246931                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                  19674377                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles               2107337                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                1002883                       # Number of cycles decode is squashing
@@ -354,16 +336,16 @@ system.cpu.decode.BranchMispred                 12053                       # Nu
 system.cpu.decode.DecodedInsts              133445502                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                 49010                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                1002883                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 14206626                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4728528                       # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles                 14206625                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4728440                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           8922                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                  20521133                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3626870                       # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles               3626960                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts              129917938                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                 71936                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                1987853                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LQFullEvents                1348485                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  46116                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents                  46206                       # Number of times rename has blocked due to SQ full
 system.cpu.rename.RenamedOperands            95420653                       # Number of destination operands rename has renamed
 system.cpu.rename.RenameLookups             168813407                       # Number of register rename lookups that rename has made
 system.cpu.rename.int_rename_lookups        161260201                       # Number of integer rename lookups
@@ -384,23 +366,23 @@ system.cpu.iq.iqSquashedInstsIssued            120259                       # Nu
 system.cpu.iq.iqSquashedInstsExamined        27967887                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined     21886191                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved           1551                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44094962                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples      44094963                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::mean         2.270157                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::stdev        2.096378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::0            11535006     26.16%     26.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7754469     17.59%     43.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7754470     17.59%     43.75% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::2             7555421     17.13%     60.88% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::3             5737104     13.01%     73.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4489383     10.18%     84.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2977389      6.75%     90.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4489384     10.18%     84.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2977388      6.75%     90.82% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6             2013844      4.57%     95.39% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7             1160432      2.63%     98.02% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8              871914      1.98%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44094962                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44094963                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                  479018     20.14%     20.14% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     20.14% # attempts to use FU when none available
@@ -473,7 +455,7 @@ system.cpu.iq.FU_type_0::total              100102500                       # Ty
 system.cpu.iq.rate                           2.258690                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                     2377986                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.023756                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          231175585                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads          231175586                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes         131029945                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses     90008848                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads            15622622                       # Number of floating instruction queue reads
@@ -493,15 +475,15 @@ system.cpu.iew.lsq.thread0.rescheduledLoads        42761                       #
 system.cpu.iew.lsq.thread0.cacheBlocked          2468                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                1002883                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3707628                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                461879                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewBlockCycles                 3707612                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                461807                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts           123638491                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts            278104                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts              27105677                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts              8747640                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts               1940                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                  39979                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                414957                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                414885                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          42241                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect         554445                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect       525545                       # Number of branches that were predicted not taken incorrectly
@@ -517,8 +499,8 @@ system.cpu.iew.exec_stores                    7162603                       # Nu
 system.cpu.iew.exec_rate                     2.227716                       # Inst execution rate
 system.cpu.iew.wb_sent                       97918369                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                      97175588                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  67088119                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95122375                       # num instructions consuming a value
+system.cpu.iew.wb_producers                  67088120                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95122376                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_rate                       2.192648                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.705282                       # average fanout of values written-back
@@ -526,11 +508,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts        31736961                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            962705                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39466886                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples     39466887                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     2.328612                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     2.908948                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14969499     37.93%     37.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14969500     37.93%     37.93% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1      8597582     21.78%     59.71% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2      3898491      9.88%     69.59% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3      1956472      4.96%     74.55% # Number of insts commited each cycle
@@ -542,7 +524,7 @@ system.cpu.commit.committed_per_cycle::8      6211472     15.74%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39466886                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39466887                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -590,10 +572,10 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
 system.cpu.commit.bw_lim_events               6211472                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    156894390                       # The number of ROB reads
+system.cpu.rob.rob_reads                    156894391                       # The number of ROB reads
 system.cpu.rob.rob_writes                   251967276                       # The number of ROB writes
 system.cpu.timesIdled                            4539                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          223861                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                          223860                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
 system.cpu.cpi                               0.526479                       # CPI: Cycles Per Instruction
@@ -606,42 +588,149 @@ system.cpu.fp_regfile_reads                   6250590                       # nu
 system.cpu.fp_regfile_writes                  6153622                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  718773                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq          12032                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         12032                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          110                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1735                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1735                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23038                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4606                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             27644                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       737216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150912                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             888128                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13877                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              13877    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13877                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7048500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17856500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3547750                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements               160                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1457.564933                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28680753                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2248                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12758.342082                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.564933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355851                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355851                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1388                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57382576                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57382576                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22187756                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22187756                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492735                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492735                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          262                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          262                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28680491                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28680491                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28680491                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28680491                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1042                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1042                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8368                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8368                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data         9410                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9410                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9410                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9410                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     65475750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     65475750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    523849968                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    523849968                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        92750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    589325718                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    589325718                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    589325718                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    589325718                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22188798                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22188798                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          263                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          263                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28689901                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28689901                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28689901                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28689901                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001287                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001287                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003802                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003802                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000328                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000328                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000328                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000328                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62627.600213                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62627.600213                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        29227                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          416                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               894                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    32.692394                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          208                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks          110                       # number of writebacks
+system.cpu.dcache.writebacks::total               110                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          529                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6634                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6634                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7163                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7163                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7163                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7163                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          513                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          513                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1734                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1734                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2247                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2247                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2247                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36153000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36153000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    125731745                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    125731745                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161884745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    161884745                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161884745                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    161884745                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003802                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003802                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9583                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1600.631019                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1600.631053                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            16112652                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             11519                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1398.789131                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1600.631019                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1600.631053                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.781558                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.781558                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
@@ -665,12 +754,12 @@ system.cpu.icache.demand_misses::cpu.inst        14533                       # n
 system.cpu.icache.demand_misses::total          14533                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        14533                       # number of overall misses
 system.cpu.icache.overall_misses::total         14533                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    419606250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    419606250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    419606250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    419606250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    419606250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    419606250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    419570250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    419570250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    419570250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    419570250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    419570250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    419570250                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     16127185                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     16127185                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     16127185                       # number of demand (read+write) accesses
@@ -683,12 +772,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000901
 system.cpu.icache.demand_miss_rate::total     0.000901                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000901                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000901                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28872.651896                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28872.651896                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28870.174775                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28870.174775                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          196                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
@@ -709,34 +798,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11519
 system.cpu.icache.demand_mshr_misses::total        11519                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11519                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11519                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    306578000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    306578000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    306578000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    306578000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    306578000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    306578000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    306551250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    306551250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    306551250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    306551250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    306551250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    306551250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000714                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000714                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000714                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000714                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000714                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000714                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2401.991277                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2401.991328                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               8524                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3591                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.373712                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.703654                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.347182                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   376.940441                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.703660                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.347225                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   376.940444                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061259                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.011503                       # Average percentage of cache occupancy
@@ -774,17 +863,17 @@ system.cpu.l2cache.demand_misses::total          5232                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3065                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2167                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5232                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    210511250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     35108000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    245619250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    123622250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    123622250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    210511250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    158730250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    369241500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    210511250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    158730250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    369241500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    210484500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     35100000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    245584500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    123658250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    123658250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    210484500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    158758250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    369242750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    210484500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    158758250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    369242750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        11519                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          513                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total        12032                       # number of ReadReq accesses(hits+misses)
@@ -809,17 +898,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.380039                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.266082                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963968                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.380039                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -839,17 +928,17 @@ system.cpu.l2cache.demand_mshr_misses::total         5232
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3065                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2167                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5232                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    171684750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     29423500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    201108250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    102762250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    102762250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171684750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    132185750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    303870500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171684750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    132185750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    303870500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    171659500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     29415000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    201074500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    102798250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    102798250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171659500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    132213250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    303872750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171659500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    132213250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    303872750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.266082                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.892788                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.292803                       # mshr miss rate for ReadReq accesses
@@ -861,153 +950,69 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.380039
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.266082                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963968                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.380039                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements               160                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1457.564755                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28680753                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2248                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12758.342082                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1457.564755                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355851                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355851                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1388                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57382576                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57382576                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22187756                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22187756                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492735                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492735                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          262                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          262                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28680491                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28680491                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28680491                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28680491                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1042                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1042                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8368                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8368                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9410                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9410                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9410                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9410                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     65491750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     65491750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    523624968                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    523624968                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        92750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    589116718                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    589116718                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    589116718                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    589116718                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22188798                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22188798                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          263                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          263                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28689901                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28689901                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28689901                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28689901                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000047                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000047                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001287                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001287                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003802                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003802                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000328                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000328                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000328                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000328                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62605.389798                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62605.389798                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        29209                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          416                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               894                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    32.672260                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          208                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          110                       # number of writebacks
-system.cpu.dcache.writebacks::total               110                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          529                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6634                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6634                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7163                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7163                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7163                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7163                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          513                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          513                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1734                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1734                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2247                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2247                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2247                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2247                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36161000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36161000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    125695745                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    125695745                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161856745                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    161856745                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161856745                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    161856745                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003802                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003802                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq          12032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         12032                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          110                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1735                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1735                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23038                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4606                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             27644                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       737216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             888128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        13877                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13877    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total          13877                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7048500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      17856250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy       3547750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                3523                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1709                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1709                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10464                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10464                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334848                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              5232                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5232    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                5232                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6529000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           48920250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.131746                       # Nu
 sim_ticks                                131745950000                       # Number of ticks simulated
 final_tick                               131745950000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 190259                       # Simulator instruction rate (inst/s)
-host_op_rate                                   200564                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              145463120                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256996                       # Number of bytes of host memory used
-host_seconds                                   905.70                       # Real time elapsed on the host
+host_inst_rate                                 246838                       # Simulator instruction rate (inst/s)
+host_op_rate                                   260207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188720644                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 315756                       # Number of bytes of host memory used
+host_seconds                                   698.10                       # Real time elapsed on the host
 sim_insts                                   172317809                       # Number of instructions simulated
 sim_ops                                     181650742                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895           14      1.54%     91.67% # By
 system.physmem.bytesPerActivate::896-1023           19      2.08%     93.75% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           57      6.25%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            912                       # Bytes accessed per row activation
-system.physmem.totQLat                       28129500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100635750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                       28130750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100637000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19335000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7274.24                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7274.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26024.24                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26024.57                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           1.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        1.88                       # Average system read bandwidth in MiByte/s
@@ -218,29 +218,34 @@ system.physmem.readRowHitRate                   76.29                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                     34069268.55                       # Average gap between requests
 system.physmem.pageHitRate                      76.29                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE     125856871250                       # Time in different power states
-system.physmem.memoryStateTime::REF        4399200000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT        1487617250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                   3092040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                   3787560                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                   1687125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                   2066625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                 16177200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                 13767000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0            8604835200                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1            8604835200                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0            3575888730                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1            3595740120                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0           75909421500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1           75892008000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0             88111101795                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1             88112204505                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             668.807404                       # Core power per rank (mW)
-system.physmem.averagePower::1             668.815774                       # Core power per rank (mW)
+system.physmem_0.actEnergy                    3092040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1687125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16177200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             8604835200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3575900700                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75909402750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              88111095015                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.807422                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   126280313250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4399200000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1064296750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                    3787560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2066625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13767000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             8604835200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3595739265                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75892008750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              88112204400                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.815773                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   126251429250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4399200000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1093059250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                49935043                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          39664695                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           5744224                       # Number of conditional branches incorrect
@@ -251,6 +256,14 @@ system.cpu.branchPred.BTBHitPct             95.508866                       # BT
 system.cpu.branchPred.usedRAS                 1908457                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                139                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -272,6 +285,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -293,6 +314,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -314,6 +343,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -348,12 +385,12 @@ system.cpu.ipc                               0.653978                       # IP
 system.cpu.tickCycles                       257145198                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                         6346702                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.772721                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1377.772724                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            40762987                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          22520.987293                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst  1377.772721                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.inst  1377.772724                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.inst     0.336370                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.336370                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
@@ -387,12 +424,12 @@ system.cpu.dcache.overall_misses::cpu.inst         2436                       #
 system.cpu.dcache.overall_misses::total          2436                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.inst     54011984                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     54011984                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115580250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    115580250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst    169592234                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    169592234                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst    169592234                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    169592234                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst    115610250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    115610250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst    169622234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    169622234                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst    169622234                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    169622234                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst     28356322                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     28356322                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst     12364287                       # number of WriteReq accesses(hits+misses)
@@ -415,12 +452,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst     0.000060
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68196.949495                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70304.288321                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70304.288321                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69619.143678                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69619.143678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69619.143678                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69619.143678                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70322.536496                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69631.458949                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69631.458949                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69631.458949                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69631.458949                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -449,12 +486,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst         1810
 system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst     47293264                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total     47293264                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     76493500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     76493500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    123786764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    123786764                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    123786764                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    123786764                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst     76508500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     76508500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    123801764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    123801764                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    123801764                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    123801764                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000089                       # mshr miss rate for WriteReq accesses
@@ -465,20 +502,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000044
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66423.123596                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69666.211293                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69666.211293                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68390.477348                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68390.477348                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68390.477348                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68390.477348                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69679.872495                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68398.764641                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68398.764641                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              2909                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1424.880839                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1424.880841                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            71614329                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              4705                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          15220.898831                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1424.880839                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst  1424.880841                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.695743                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.695743                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
@@ -502,12 +539,12 @@ system.cpu.icache.demand_misses::cpu.inst         4706                       # n
 system.cpu.icache.demand_misses::total           4706                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         4706                       # number of overall misses
 system.cpu.icache.overall_misses::total          4706                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    186392247                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    186392247                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    186392247                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    186392247                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    186392247                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    186392247                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    186377497                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    186377497                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    186377497                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    186377497                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    186377497                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    186377497                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     71619035                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     71619035                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     71619035                       # number of demand (read+write) accesses
@@ -520,12 +557,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000066
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39607.362303                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39607.362303                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39607.362303                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39607.362303                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39607.362303                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39607.362303                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39604.228007                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39604.228007                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -540,33 +577,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         4706
 system.cpu.icache.demand_mshr_misses::total         4706                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         4706                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         4706                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    176061753                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    176061753                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    176061753                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    176061753                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    176061753                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    176061753                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    176047503                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    176047503                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    176047503                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    176047503                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    176047503                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    176047503                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37412.187208                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 37412.187208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37412.187208                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 37412.187208                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2001.520468                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2001.520471                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               2624                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             2785                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.942190                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks     3.029184                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1998.491284                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1998.491287                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.060989                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.061082                       # Average percentage of cache occupancy
@@ -597,14 +634,14 @@ system.cpu.l2cache.demand_misses::cpu.inst         3885                       #
 system.cpu.l2cache.demand_misses::total          3885                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         3885                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3885                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191698500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    191698500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75314000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     75314000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    267012500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    267012500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    267012500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    267012500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191684250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    191684250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst     75329000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     75329000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    267013250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    267013250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    267013250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    267013250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         5418                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         5418                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
@@ -623,14 +660,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.596225
 system.cpu.l2cache.demand_miss_rate::total     0.596225                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.596225                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.596225                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68586.225403                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68586.225403                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.412844                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.412844                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.086229                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68729.086229                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.086229                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68729.086229                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68581.127013                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69109.174312                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68729.279279                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68729.279279                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -653,14 +690,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst         3868
 system.cpu.l2cache.demand_mshr_misses::total         3868                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3868                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3868                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    155803750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    155803750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     61486500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     61486500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    217290250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    217290250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    217290250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    217290250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    155790000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    155790000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst     61501500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     61501500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    217291500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    217291500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    217291500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    217291500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.512735                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.512735                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.992714                       # mshr miss rate for ReadExReq accesses
@@ -669,14 +706,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.593616
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.593616                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.593616                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.593616                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56084.863211                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56084.863211                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56409.633028                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56409.633028                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.383144                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.383144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.383144                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.383144                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq           5418                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          5417                       # Transaction distribution
@@ -707,7 +744,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value            5                       #
 system.cpu.toL2Bus.snoop_fanout::total           6532                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy        3282000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7517747                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7517497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2996736                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
@@ -732,7 +769,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                3867                       # Request fanout histogram
 system.membus.reqLayer0.occupancy             4723500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           36361250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           36361000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.099596                       # Nu
 sim_ticks                                 99596491000                       # Number of ticks simulated
 final_tick                                99596491000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2060285                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2171872                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1190808654                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300012                       # Number of bytes of host memory used
-host_seconds                                    83.64                       # Real time elapsed on the host
+host_inst_rate                                1699536                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1791584                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              982302061                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304728                       # Number of bytes of host memory used
+host_seconds                                   101.39                       # Real time elapsed on the host
 sim_insts                                   172317409                       # Number of instructions simulated
 sim_ops                                     181650341                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -35,37 +35,15 @@ system.physmem.bw_write::total              454362795                       # Wr
 system.physmem.bw_total::cpu.inst          7625170288                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          1564177607                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9189347896                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq           217614902                       # Transaction distribution
-system.membus.trans_dist::ReadResp          217637309                       # Transaction distribution
-system.membus.trans_dist::WriteReq           12364287                       # Transaction distribution
-system.membus.trans_dist::WriteResp          12364287                       # Transaction distribution
-system.membus.trans_dist::SoftPFReq               463                       # Transaction distribution
-system.membus.trans_dist::SoftPFResp              463                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq         22407                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq          22407                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp         22407                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    379720102                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     80328830                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total              460048932                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    759440204                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    155786601                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               915226805                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples         230024466                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.825391                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.379633                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                40164415     17.46%     17.46% # Request fanout histogram
-system.membus.snoop_fanout::5               189860051     82.54%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total           230024466                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  181650742                       # Class of executed instruction
+system.membus.trans_dist::ReadReq           217614902                       # Transaction distribution
+system.membus.trans_dist::ReadResp          217637309                       # Transaction distribution
+system.membus.trans_dist::WriteReq           12364287                       # Transaction distribution
+system.membus.trans_dist::WriteResp          12364287                       # Transaction distribution
+system.membus.trans_dist::SoftPFReq               463                       # Transaction distribution
+system.membus.trans_dist::SoftPFResp              463                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq         22407                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq          22407                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp         22407                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port    379720102                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port     80328830                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total              460048932                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port    759440204                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port    155786601                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               915226805                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples         230024466                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.825391                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.379633                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                40164415     17.46%     17.46% # Request fanout histogram
+system.membus.snoop_fanout::5               189860051     82.54%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total           230024466                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.230173                       # Nu
 sim_ticks                                230173357000                       # Number of ticks simulated
 final_tick                               230173357000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1215411                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1281349                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1627973861                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309492                       # Number of bytes of host memory used
-host_seconds                                   141.39                       # Real time elapsed on the host
+host_inst_rate                                1229194                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1295881                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1646435898                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 312932                       # Number of bytes of host memory used
+host_seconds                                   139.80                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     181165370                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total             480751                       # In
 system.physmem.bw_total::cpu.inst              480751                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data              479360                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 960111                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         6906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   6906                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       220992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  220992                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              3453                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    3453    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                3453                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             3596000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           31220000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -198,6 +207,139 @@ system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  181650742                       # Class of executed instruction
+system.cpu.dcache.tags.replacements                40                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1363.619284                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619284                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.332915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.332915                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      40117350                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40117350                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40117812                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40117812                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          688                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           688                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data         1788                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     35469000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     60194500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     95663500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     95663500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     95663500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40119138                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40119601                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53503.076063                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53473.169368                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
+system.cpu.dcache.writebacks::total                16                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          688                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1788                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34093000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     57994500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     92087500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     92140500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1506                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1147.992604                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857001                       # Total number of references to valid blocks.
@@ -430,139 +572,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.619284                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.619284                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332915                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332915                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40117350                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40117350                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40117812                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40117812                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          688                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           688                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         1788                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     35469000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     35469000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     60194500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     60194500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     95663500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     95663500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     95663500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     95663500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          463                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40119138                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40119138                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40119601                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40119601                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000025                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000025                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.002160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.002160                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000045                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53503.076063                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53473.169368                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
-system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          688                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          688                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1788                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34093000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     34093000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57994500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     57994500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        53000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     92087500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92140500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     92140500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.002160                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.002160                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq           3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           16                       # Transaction distribution
@@ -596,5 +605,28 @@ system.cpu.toL2Bus.respLayer0.occupancy       4576500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2683500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                2361                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         6906                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   6906                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       220992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  220992                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              3453                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    3453    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                3453                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             3596000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy           31220000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  2.802895                       # Nu
 sim_ticks                                2802895103500                       # Number of ticks simulated
 final_tick                               2802895103500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 967895                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1179365                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18476638236                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 571628                       # Number of bytes of host memory used
-host_seconds                                   151.70                       # Real time elapsed on the host
+host_inst_rate                                 834307                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1016590                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            15926512431                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 572876                       # Number of bytes of host memory used
+host_seconds                                   175.99                       # Real time elapsed on the host
 sim_insts                                   146829031                       # Number of instructions simulated
 sim_ops                                     178908942                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -93,6 +93,14 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -114,6 +122,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                     7967                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                7967                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         7967                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           7967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         7967                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         5082     77.32%     77.32% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1491     22.68%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         6573                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7967                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7967                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6573                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6573                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        14540                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu0.dtb.read_hits                    20339962                       # DTB read hits
@@ -135,6 +161,14 @@ system.cpu0.dtb.inst_accesses                       0                       # IT
 system.cpu0.dtb.hits                         36731133                       # DTB hits
 system.cpu0.dtb.misses                           7967                       # DTB misses
 system.cpu0.dtb.accesses                     36739100                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -156,6 +190,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.walker.walks                     3358                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0        6702500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         2040     87.11%     87.11% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          302     12.89%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         2342                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3358                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2342                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2342                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         5700                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.inst_hits                    97440315                       # ITB inst hits
 system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -371,15 +423,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu0.l2cache.tags.replacements          252403                       # number of replacements
 system.cpu0.l2cache.tags.tagsinuse       16129.283805                       # Cycle average of tags in use
 system.cpu0.l2cache.tags.total_refs           1810262                       # Total number of references to valid blocks.
@@ -544,6 +593,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% #
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::total       2656528                       # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -565,6 +622,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                     3358                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples  -1804206736                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0    -1804206736    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total  -1804206736                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         1919     74.15%     74.15% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M          669     25.85%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3358                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2588                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total         5946                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu1.dtb.read_hits                    12173884                       # DTB read hits
@@ -586,6 +661,14 @@ system.cpu1.dtb.inst_accesses                       0                       # IT
 system.cpu1.dtb.hits                         19761077                       # DTB hits
 system.cpu1.dtb.misses                           3358                       # DTB misses
 system.cpu1.dtb.accesses                     19764435                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -607,6 +690,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.walker.walks                     1734                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                1734                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walkWaitTime::samples         1734                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           1734    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         1734                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples  -1804209236                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0    -1804209236    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total  -1804209236                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K          935     85.39%     85.39% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          160     14.61%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         1095                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1734                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1734                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1095                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1095                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         2829                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.inst_hits                    53671431                       # ITB inst hits
 system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -820,15 +921,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu1.l2cache.tags.replacements           48598                       # number of replacements
 system.cpu1.l2cache.tags.tagsinuse       15305.342188                       # Cycle average of tags in use
 system.cpu1.l2cache.tags.total_refs            716678                       # Total number of references to valid blocks.

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867165000                       # Number of ticks simulated
 final_tick                               2783867165000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1064003                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1295252                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            20746494205                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 558936                       # Number of bytes of host memory used
-host_seconds                                   134.19                       # Real time elapsed on the host
+host_inst_rate                                1374338                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1673035                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            26797569978                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 615488                       # Number of bytes of host memory used
+host_seconds                                   103.89                       # Real time elapsed on the host
 sim_insts                                   142773109                       # Number of instructions simulated
 sim_ops                                     173803334                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -70,6 +70,14 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -91,6 +99,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                     10029                       # Table walker walks requested
+system.cpu.dtb.walker.walksShort                10029                       # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walkWaitTime::samples        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0           10029    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total        10029                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0         6705500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K          6354     80.79%     80.79% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M          1511     19.21%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total         7865                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data        10029                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total        10029                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data         7865                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7865                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total        17894                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                     31526301                       # DTB read hits
@@ -112,6 +138,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                          54650764                       # DTB hits
 system.cpu.dtb.misses                           10029                       # DTB misses
 system.cpu.dtb.accesses                      54660793                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -133,6 +167,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                      4762                       # Table walker walks requested
+system.cpu.itb.walker.walksShort                 4762                       # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walkWaitTime::samples         4762                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0            4762    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total         4762                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0         6702500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K          2798     90.05%     90.05% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M           309      9.95%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total         3107                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst         4762                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total         4762                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst         3107                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total         3107                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total         7869                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                    147039592                       # ITB inst hits
 system.cpu.itb.inst_misses                       4762                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits

tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  2.783867                       # Nu
 sim_ticks                                2783867165000                       # Number of ticks simulated
 final_tick                               2783867165000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1108011                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1348825                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            21604583679                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 560868                       # Number of bytes of host memory used
-host_seconds                                   128.86                       # Real time elapsed on the host
+host_inst_rate                                1311458                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1596489                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25571502260                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 616488                       # Number of bytes of host memory used
+host_seconds                                   108.87                       # Real time elapsed on the host
 sim_insts                                   142773109                       # Number of instructions simulated
 sim_ops                                     173803334                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages                   540                       # Nu
 system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                     5682                       # Table walker walks requested
+system.cpu0.dtb.walker.walksShort                5682                       # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples         5682                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0           5682    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total         5682                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K         3049     65.42%     65.42% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M         1612     34.58%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total         4661                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5682                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5682                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4661                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4661                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total        10343                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu0.dtb.read_hits                    15994592                       # DTB read hits
@@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses                       0                       # IT
 system.cpu0.dtb.hits                         27280368                       # DTB hits
 system.cpu0.dtb.misses                           5682                       # DTB misses
 system.cpu0.dtb.accesses                     27286050                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.walker.walks                     2611                       # Table walker walks requested
+system.cpu0.itb.walker.walksShort                2611                       # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples         2611                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0           2611    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total         2611                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0        6702500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K         1374     72.85%     72.85% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M          512     27.15%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total         1886                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2611                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2611                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         1886                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total         1886                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total         4497                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.inst_hits                    74779253                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2611                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                     6203                       # Table walker walks requested
+system.cpu1.dtb.walker.walksShort                6203                       # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples         6203                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0           6203    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total         6203                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples   1000002000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1000002000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1000002000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K         3703     73.18%     73.18% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M         1357     26.82%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total         5060                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         6203                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         6203                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         5060                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         5060                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total        11263                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu1.dtb.read_hits                    15530019                       # DTB read hits
@@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses                       0                       # IT
 system.cpu1.dtb.hits                         27368468                       # DTB hits
 system.cpu1.dtb.misses                           6203                       # DTB misses
 system.cpu1.dtb.accesses                     27374671                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.walker.walks                     3040                       # Table walker walks requested
+system.cpu1.itb.walker.walksShort                3040                       # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walkWaitTime::samples         3040                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0           3040    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total         3040                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K         1720     81.52%     81.52% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M          390     18.48%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total         2110                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         3040                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total         3040                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         2110                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total         2110                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total         5150                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.inst_hits                    72259450                       # ITB inst hits
 system.cpu1.itb.inst_misses                      3040                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits

tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                 47.177080                       # Nu
 sim_ticks                                47177080006500                       # Number of ticks simulated
 final_tick                               47177080006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1024538                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1205255                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            49483118923                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 669884                       # Number of bytes of host memory used
-host_seconds                                   953.40                       # Real time elapsed on the host
+host_inst_rate                                1049876                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1235062                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            50706899360                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 670076                       # Number of bytes of host memory used
+host_seconds                                   930.39                       # Real time elapsed on the host
 sim_insts                                   976792036                       # Number of instructions simulated
 sim_ops                                    1149086878                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages                  1667                       # Nu
 system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   123914                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               123914                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples       123914                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         123914    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       123914                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K        95376     89.74%     89.74% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        10905     10.26%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       106281                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       123914                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       123914                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       106281                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       106281                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       230195                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu0.dtb.read_hits                    91355479                       # DTB read hits
@@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses                       0                       # IT
 system.cpu0.dtb.hits                        175957422                       # DTB hits
 system.cpu0.dtb.misses                         123914                       # DTB misses
 system.cpu0.dtb.accesses                    176081336                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.walker.walks                    60226                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                60226                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        60226                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          60226    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        60226                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        54190     98.81%     98.81% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M          654      1.19%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        54844                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        60226                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        60226                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        54844                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        54844                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       115070                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.inst_hits                   491372488                       # ITB inst hits
 system.cpu0.itb.inst_misses                     60226                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
+system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
+system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu0.l2cache.tags.replacements         2648971                       # number of replacements
 system.cpu0.l2cache.tags.tagsinuse       16219.904236                       # Cycle average of tags in use
 system.cpu0.l2cache.tags.total_refs          11415809                       # Total number of references to valid blocks.
@@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% #
 system.cpu0.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
 system.cpu0.toL2Bus.snoop_fanout::total      20196192                       # Request fanout histogram
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   144852                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               144852                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples       144852                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         144852    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       144852                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples   -274403872                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     -274403872    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   -274403872                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K       112422     89.02%     89.02% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        13865     10.98%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       126287                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       144852                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       144852                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       126287                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       126287                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       271139                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu1.dtb.read_hits                    91720002                       # DTB read hits
@@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses                       0                       # IT
 system.cpu1.dtb.hits                        174219015                       # DTB hits
 system.cpu1.dtb.misses                         144852                       # DTB misses
 system.cpu1.dtb.accesses                    174363867                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.walker.walks                    61939                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                61939                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples        61939                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          61939    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        61939                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples   -274404872                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     -274404872    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   -274404872                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        54929     99.06%     99.06% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M          521      0.94%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        55450                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        61939                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        61939                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55450                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55450                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       117389                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.inst_hits                   485906850                       # ITB inst hits
 system.cpu1.itb.inst_misses                     61939                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
@@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
+system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
+system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
+system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
 system.cpu1.l2cache.tags.replacements         2333825                       # number of replacements
 system.cpu1.l2cache.tags.tagsinuse       13484.024344                       # Cycle average of tags in use
 system.cpu1.l2cache.tags.total_refs          11006559                       # Total number of references to valid blocks.

tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                 51.111151                       # Nu
 sim_ticks                                51111150553500                       # Number of ticks simulated
 final_tick                               51111150553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1176583                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1382679                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            61065327647                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 656288                       # Number of bytes of host memory used
-host_seconds                                   836.99                       # Real time elapsed on the host
+host_inst_rate                                1336104                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1570142                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            69344550867                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 712616                       # Number of bytes of host memory used
+host_seconds                                   737.06                       # Real time elapsed on the host
 sim_insts                                   984789519                       # Number of instructions simulated
 sim_ops                                    1157289961                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -74,6 +74,14 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -95,6 +103,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                    265618                       # Table walker walks requested
+system.cpu.dtb.walker.walksLong                265618                       # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples       265618                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0          265618    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total       265618                       # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0        22846000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K        204344     89.54%     89.54% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M         23878     10.46%    100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total       228222                       # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       265618                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total       265618                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       228222                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total       228222                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total       493840                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                    184057973                       # DTB read hits
@@ -116,6 +142,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                         352334273                       # DTB hits
 system.cpu.dtb.misses                          265618                       # DTB misses
 system.cpu.dtb.accesses                     352599891                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -137,6 +171,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                    126829                       # Table walker walks requested
+system.cpu.itb.walker.walksLong                126829                       # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples       126829                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0          126829    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total       126829                       # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0        22844500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K        113566     99.02%     99.02% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M          1125      0.98%    100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total       114691                       # Table walker page sizes translated
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       126829                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total       126829                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       114691                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total       114691                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total       241520                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                    985266544                       # ITB inst hits
 system.cpu.itb.inst_misses                     126829                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits

tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                 51.111151                       # Nu
 sim_ticks                                51111150553500                       # Number of ticks simulated
 final_tick                               51111150553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1088550                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1279225                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            56496360239                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 672572                       # Number of bytes of host memory used
-host_seconds                                   904.68                       # Real time elapsed on the host
+host_inst_rate                                1151312                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1352981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            59753764865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 728116                       # Number of bytes of host memory used
+host_seconds                                   855.36                       # Real time elapsed on the host
 sim_insts                                   984789519                       # Number of instructions simulated
 sim_ops                                    1157289961                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -92,6 +92,14 @@ system.cf0.dma_write_full_pages                  1666                       # Nu
 system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -113,6 +121,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.dtb.walker.walks                   144982                       # Table walker walks requested
+system.cpu0.dtb.walker.walksLong               144982                       # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples       144982                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0         144982    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total       144982                       # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K       108340     85.69%     85.69% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M        18088     14.31%    100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total       126428                       # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       144982                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       144982                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       126428                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       126428                       # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total       271410                       # Table walker requests started/completed, data/inst
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu0.dtb.read_hits                    91965302                       # DTB read hits
@@ -134,6 +160,14 @@ system.cpu0.dtb.inst_accesses                       0                       # IT
 system.cpu0.dtb.hits                        176331252                       # DTB hits
 system.cpu0.dtb.misses                         144982                       # DTB misses
 system.cpu0.dtb.accesses                    176476234                       # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -155,6 +189,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu0.itb.walker.walks                    70785                       # Table walker walks requested
+system.cpu0.itb.walker.walksLong                70785                       # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples        70785                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0          70785    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total        70785                       # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K        62159     96.07%     96.07% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M         2545      3.93%    100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total        64704                       # Table walker page sizes translated
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        70785                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total        70785                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64704                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64704                       # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total       135489                       # Table walker requests started/completed, data/inst
 system.cpu0.itb.inst_hits                   493804573                       # ITB inst hits
 system.cpu0.itb.inst_misses                     70785                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
@@ -424,6 +476,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -445,6 +505,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.dtb.walker.walks                   143312                       # Table walker walks requested
+system.cpu1.dtb.walker.walksLong               143312                       # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples       143312                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0         143312    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total       143312                       # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walksPending::samples   1000001000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0     1000001000    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total   1000001000                       # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K       106567     85.62%     85.62% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M        17903     14.38%    100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total       124470                       # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       143312                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       143312                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       124470                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       124470                       # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total       267782                       # Table walker requests started/completed, data/inst
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu1.dtb.read_hits                    92072581                       # DTB read hits
@@ -466,6 +544,14 @@ system.cpu1.dtb.inst_accesses                       0                       # IT
 system.cpu1.dtb.hits                        175979862                       # DTB hits
 system.cpu1.dtb.misses                         143312                       # DTB misses
 system.cpu1.dtb.accesses                    176123174                       # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -487,6 +573,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu1.itb.walker.walks                    69790                       # Table walker walks requested
+system.cpu1.itb.walker.walksLong                69790                       # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples        69790                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0          69790    100.00%    100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total        69790                       # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K        61179     95.99%     95.99% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M         2554      4.01%    100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total        63733                       # Table walker page sizes translated
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69790                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69790                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63733                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63733                       # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total       133523                       # Table walker requests started/completed, data/inst
 system.cpu1.itb.inst_hits                   491448225                       # ITB inst hits
 system.cpu1.itb.inst_misses                     69790                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits

tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt

@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000035                       # Number of seconds simulated
-sim_ticks                                    35022500                       # Number of ticks simulated
-final_tick                                   35022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    34993500                       # Number of ticks simulated
+final_tick                                   34993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71946                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              393524726                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237176                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                 162128                       # Simulator instruction rate (inst/s)
+host_op_rate                                   162075                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              885888965                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292456                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst        23296                       # Nu
 system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            974002427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               974002427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       665172389                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          665172389                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           974002427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              974002427                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            974809607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               974809607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       665723634                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          665723634                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           974809607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              974809607                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         533                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        34924000                       # Total gap between requests
+system.physmem.totGap                        34895000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -196,19 +196,19 @@ system.physmem.bytesPerActivate::768-895            1      1.11%     84.44% # By
 system.physmem.bytesPerActivate::896-1023            4      4.44%     88.89% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151           10     11.11%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             90                       # Bytes accessed per row activation
-system.physmem.totQLat                        3887500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13881250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        3849750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13843500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2665000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7293.62                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7222.80                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26043.62                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         974.00                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25972.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         974.81                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      974.00                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      974.81                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.61                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.61                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.62                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.62                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -216,31 +216,36 @@ system.physmem.readRowHits                        435                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   81.61                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        65523.45                       # Average gap between requests
+system.physmem.avgGap                        65469.04                       # Average gap between requests
 system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
-system.physmem.memoryStateTime::REF           1040000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          30393500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    257040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    385560                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    140250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    210375                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                  2082600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  1677000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               2034240                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              21425445                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              20164320                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 67500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1               1173750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                26007075                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                25645245                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             827.295718                       # Core power per rank (mW)
-system.physmem.averagePower::1             815.785757                       # Core power per rank (mW)
+system.physmem_0.actEnergy                     257040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     140250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2082600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               21404070                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  67500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 25985700                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              827.438306                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          15500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        30363250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     385560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     210375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1677000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                2034240                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               20164320                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                1173750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 25645245                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              815.785757                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        2149750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF         1040000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        28549750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    1972                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1208                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               368                       # Number of conditional branches incorrect
@@ -284,26 +289,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            70045                       # number of cpu cycles simulated
+system.cpu.numCycles                            69987                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        6400                       # Number of instructions committed
 system.cpu.committedOps                          6400                       # Number of ops (including micro ops) committed
 system.cpu.discardedOps                          1109                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                              10.944531                       # CPI: cycles per instruction
-system.cpu.ipc                               0.091370                       # IPC: instructions per cycle
-system.cpu.tickCycles                           12615                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                           57430                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                              10.935469                       # CPI: cycles per instruction
+system.cpu.ipc                               0.091446                       # IPC: instructions per cycle
+system.cpu.tickCycles                           12616                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                           57371                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           104.047628                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           104.036694                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1973                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.674556                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   104.047628                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.025402                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025402                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst   104.036694                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.025400                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025400                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
@@ -328,12 +333,12 @@ system.cpu.dcache.overall_misses::cpu.inst          227                       #
 system.cpu.dcache.overall_misses::total           227                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7703250                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      7703250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8679250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      8679250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     16382500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16382500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     16382500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16382500                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8670250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8670250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst     16373500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16373500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst     16373500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16373500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst         1335                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1335                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
@@ -352,12 +357,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst     0.103182
 system.cpu.dcache.overall_miss_rate::total     0.103182                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69434                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        69434                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72169.603524                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72169.603524                       # average overall miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69362                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        69362                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72129.955947                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72129.955947                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -384,12 +389,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst          169
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7131000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      7131000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5128000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5128000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12259000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12259000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12259000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12259000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5119000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5119000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12250000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12250000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12250000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12250000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.071910                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071910                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
@@ -400,25 +405,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076818
 system.cpu.dcache.overall_mshr_miss_rate::total     0.076818                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           176.126032                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           176.047314                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                2277                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               365                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              6.238356                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   176.126032                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.085999                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.085999                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   176.047314                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.085961                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.085961                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          248                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          247                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.178223                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              5649                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             5649                       # Number of data accesses
@@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst          365                       # n
 system.cpu.icache.demand_misses::total            365                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          365                       # number of overall misses
 system.cpu.icache.overall_misses::total           365                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25915750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25915750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25915750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25915750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25915750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25915750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25886500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25886500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25886500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25886500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25886500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25886500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         2642                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         2642                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         2642                       # number of demand (read+write) accesses
@@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.138153
 system.cpu.icache.demand_miss_rate::total     0.138153                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.138153                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.138153                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 71002.054795                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 71002.054795                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70921.917808                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70921.917808                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -472,37 +477,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          365
 system.cpu.icache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          365                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25028250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25028250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25028250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25028250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25028250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25028250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24998500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24998500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24998500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24998500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24998500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24998500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138153                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.138153                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138153                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.138153                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          233.857006                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          233.762820                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.857006                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007137                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.007137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.762820                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.007134                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          325                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.014038                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4805                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4805                       # Number of data accesses
@@ -520,14 +525,14 @@ system.cpu.l2cache.demand_misses::cpu.inst          533                       #
 system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31686750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     31686750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5053000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5053000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36739750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     36739750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36739750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     36739750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31657000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     31657000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5044000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5044000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     36701000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     36701000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     36701000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     36701000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          461                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
@@ -544,14 +549,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127
 system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -568,14 +573,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst          533
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          533                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25921750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25921750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4147500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30069250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     30069250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30069250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     30069250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25891500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25891500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4138000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4138000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30029500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     30029500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30029500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     30029500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
@@ -584,14 +589,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           461                       # Transaction distribution
@@ -617,7 +622,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value            1                       #
 system.cpu.toL2Bus.snoop_fanout::total            534                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy         267000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        626250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        626500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        279000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
@@ -642,7 +647,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 533                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              606000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4967250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4968000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             14.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    20537500                       # Number of ticks simulated
 final_tick                                   20537500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  69014                       # Simulator instruction rate (inst/s)
-host_op_rate                                    69006                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              222388397                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237256                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  92569                       # Simulator instruction rate (inst/s)
+host_op_rate                                    92553                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              298254404                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293992                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -222,53 +222,34 @@ system.physmem.readRowHitRate                   80.08                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        41913.76                       # Average gap between requests
 system.physmem.pageHitRate                      80.08                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
-system.physmem.memoryStateTime::REF            520000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15339250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    234360                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    332640                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    127875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    181500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                  1755000                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  1365000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              10809765                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              10569510                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 38250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                249000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                13982370                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                13714770                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             881.195525                       # Core power per rank (mW)
-system.physmem.averagePower::1             864.330865                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 415                       # Transaction distribution
-system.membus.trans_dist::ReadResp                415                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          974                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    974                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   31168                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               487                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     487    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 487                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              610000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4554500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             22.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                     234360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     127875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   1755000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               10809765                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  38250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 13982370                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              881.195525                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          22000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15339250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     332640                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     181500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1365000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               10541295                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 252750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13690305                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              864.696352                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         637250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14974750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    2806                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1662                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               479                       # Number of conditional branches incorrect
@@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             32.481061                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     395                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 30                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -605,34 +587,118 @@ system.cpu.fp_regfile_reads                         8                       # nu
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq            416                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           416                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          348                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               976                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              31232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          488                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                488    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            488                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         244000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        528500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           107.148001                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2314                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             13.298851                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.148001                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026159                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026159                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5846                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5846                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1808                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1808                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2314                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2314                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2314                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2314                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          163                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           163                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          522                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            522                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          522                       # number of overall misses
+system.cpu.dcache.overall_misses::total           522                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11503750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11503750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22566471                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22566471                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34070221                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34070221                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34070221                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34070221                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1971                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1971                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2836                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2836                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2836                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2836                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082699                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.082699                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.184062                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.184062                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.184062                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.184062                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65268.622605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65268.622605                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1879                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                42                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.738095                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           61                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          348                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8025750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      8025750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5483750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5483750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13509500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13509500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13509500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13509500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051750                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051750                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.061354                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.061354                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           158.374396                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1718                       # Total number of references to valid blocks.
@@ -854,117 +920,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.148001                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2314                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             13.298851                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.148001                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026159                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026159                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5846                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5846                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1808                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1808                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2314                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2314                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2314                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2314                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          163                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           163                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          522                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            522                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          522                       # number of overall misses
-system.cpu.dcache.overall_misses::total           522                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11503750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11503750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22566471                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22566471                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     34070221                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     34070221                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     34070221                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     34070221                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1971                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1971                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2836                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2836                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2836                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2836                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082699                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.082699                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.184062                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.184062                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.184062                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.184062                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65268.622605                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65268.622605                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1879                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                42                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.738095                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           61                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           61                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          287                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          348                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          348                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      8025750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      8025750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5483750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5483750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13509500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13509500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13509500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13509500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051750                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051750                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.061354                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061354                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.061354                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            416                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           416                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           72                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           72                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          628                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          348                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               976                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              31232                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          488                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                488    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            488                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         244000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        528500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 415                       # Transaction distribution
+system.membus.trans_dist::ReadResp                415                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                72                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               72                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          974                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    974                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        31168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   31168                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               487                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     487    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 487                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              610000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4554500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000139                       # Nu
 sim_ticks                                      138637                       # Number of ticks simulated
 final_tick                                     138637                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12523                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12523                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 271684                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436940                       # Number of bytes of host memory used
-host_seconds                                     0.51                       # Real time elapsed on the host
+host_inst_rate                                  45640                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45635                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 990010                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451208                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -237,157 +237,35 @@ system.mem_ctrls.readRowHitRate                 81.03                       # Ro
 system.mem_ctrls.writeRowHitRate                75.41                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         79.75                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    80.50                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE            211                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            4420                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT          128005                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  559440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                 1103760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  310800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  613200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                5828160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                8112000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                362880                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                673920                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             8645520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             8645520                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            75333024                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            89081424                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0            13491600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             1431600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0             104531424                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1             109661424                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           788.190677                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           826.872042                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   9645                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.162779                       # delay histogram for all message
-system.ruby.delayHist::stdev                 1.010338                       # delay histogram for all message
-system.ruby.delayHist                    |        9295     96.37%     96.37% |           0      0.00%     96.37% |         205      2.13%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     9645                       # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8449                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8449                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              15.410630                      
-system.ruby.latency_hist::gmean              5.220511                      
-system.ruby.latency_hist::stdev             29.550250                      
-system.ruby.latency_hist                 |        7278     86.15%     86.15% |        1151     13.62%     99.78% |           3      0.04%     99.81% |           2      0.02%     99.83% |           6      0.07%     99.91% |           8      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  8448                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            6958                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6958    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              6958                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples           1490                      
-system.ruby.miss_latency_hist::mean         73.365772                      
-system.ruby.miss_latency_hist::gmean        69.379008                      
-system.ruby.miss_latency_hist::stdev        29.545012                      
-system.ruby.miss_latency_hist            |         320     21.48%     21.48% |        1151     77.25%     98.72% |           3      0.20%     98.93% |           2      0.13%     99.06% |           6      0.40%     99.46% |           8      0.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1490                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits         1249                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          799                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         5709                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          691                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   559440                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   310800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5828160                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 362880                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              8645520                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             75338496                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             13486800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy              104532096                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            788.195744                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        25869                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          4420                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT        106214                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1103760                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   613200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 8112000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 673920                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              8645520                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             89081424                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1431600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy              109661424                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            826.872042                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1728                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          4420                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        126488                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers0.percent_links_utilized     3.776229                      
-system.ruby.network.routers0.msg_count.Control::0         1490                      
-system.ruby.network.routers0.msg_count.Request_Control::2         1041                      
-system.ruby.network.routers0.msg_count.Response_Data::1         1490                      
-system.ruby.network.routers0.msg_count.Response_Control::1         1336                      
-system.ruby.network.routers0.msg_count.Response_Control::2          799                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0          145                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1          141                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0          291                      
-system.ruby.network.routers0.msg_bytes.Control::0        11920                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         8328                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1       107280                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1        10688                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2         6392                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0        10440                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1        10152                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           30                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses         1460                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses         1490                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     7.332278                      
-system.ruby.network.routers1.msg_count.Control::0         2950                      
-system.ruby.network.routers1.msg_count.Request_Control::2         1041                      
-system.ruby.network.routers1.msg_count.Response_Data::1         3227                      
-system.ruby.network.routers1.msg_count.Response_Control::1         3963                      
-system.ruby.network.routers1.msg_count.Response_Control::2          799                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0          145                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1          141                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0          291                      
-system.ruby.network.routers1.msg_bytes.Control::0        23600                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         8328                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1       232344                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1        31704                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2         6392                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0        10440                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1        10152                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.routers2.percent_links_utilized     3.556049                      
-system.ruby.network.routers2.msg_count.Control::0         1460                      
-system.ruby.network.routers2.msg_count.Response_Data::1         1737                      
-system.ruby.network.routers2.msg_count.Response_Control::1         2627                      
-system.ruby.network.routers2.msg_bytes.Control::0        11680                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1       125064                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1        21016                      
-system.ruby.network.routers3.percent_links_utilized     4.888185                      
-system.ruby.network.routers3.msg_count.Control::0         2950                      
-system.ruby.network.routers3.msg_count.Request_Control::2         1041                      
-system.ruby.network.routers3.msg_count.Response_Data::1         3227                      
-system.ruby.network.routers3.msg_count.Response_Control::1         3963                      
-system.ruby.network.routers3.msg_count.Response_Control::2          799                      
-system.ruby.network.routers3.msg_count.Writeback_Data::0          145                      
-system.ruby.network.routers3.msg_count.Writeback_Data::1          141                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0          291                      
-system.ruby.network.routers3.msg_bytes.Control::0        23600                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         8328                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1       232344                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1        31704                      
-system.ruby.network.routers3.msg_bytes.Response_Control::2         6392                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0        10440                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1        10152                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0         2328                      
-system.ruby.network.msg_count.Control            8850                      
-system.ruby.network.msg_count.Request_Control         3123                      
-system.ruby.network.msg_count.Response_Data         9681                      
-system.ruby.network.msg_count.Response_Control        14286                      
-system.ruby.network.msg_count.Writeback_Data          858                      
-system.ruby.network.msg_count.Writeback_Control          873                      
-system.ruby.network.msg_byte.Control            70800                      
-system.ruby.network.msg_byte.Request_Control        24984                      
-system.ruby.network.msg_byte.Response_Data       697032                      
-system.ruby.network.msg_byte.Response_Control       114288                      
-system.ruby.network.msg_byte.Writeback_Data        61776                      
-system.ruby.network.msg_byte.Writeback_Control         6984                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -479,6 +357,133 @@ system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
+system.ruby.delayHist::samples                   9645                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.162779                       # delay histogram for all message
+system.ruby.delayHist::stdev                 1.010338                       # delay histogram for all message
+system.ruby.delayHist                    |        9295     96.37%     96.37% |           0      0.00%     96.37% |         205      2.13%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |           0      0.00%     98.50% |         145      1.50%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     9645                       # delay histogram for all message
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         8449                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8449                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                8448                      
+system.ruby.latency_hist::mean              15.410630                      
+system.ruby.latency_hist::gmean              5.220490                      
+system.ruby.latency_hist::stdev             29.556532                      
+system.ruby.latency_hist                 |        7278     86.15%     86.15% |        1151     13.62%     99.78% |           3      0.04%     99.81% |           2      0.02%     99.83% |           6      0.07%     99.91% |           8      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  8448                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            6958                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6958    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              6958                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples           1490                      
+system.ruby.miss_latency_hist::mean         73.365772                      
+system.ruby.miss_latency_hist::gmean        69.377440                      
+system.ruby.miss_latency_hist::stdev        29.580633                      
+system.ruby.miss_latency_hist            |         320     21.48%     21.48% |        1151     77.25%     98.72% |           3      0.20%     98.93% |           2      0.13%     99.06% |           6      0.40%     99.46% |           8      0.54%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1490                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits         1249                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          799                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         5709                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          691                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
+system.ruby.l2_cntrl0.L2cache.demand_hits           30                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses         1460                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses         1490                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     3.776229                      
+system.ruby.network.routers0.msg_count.Control::0         1490                      
+system.ruby.network.routers0.msg_count.Request_Control::2         1041                      
+system.ruby.network.routers0.msg_count.Response_Data::1         1490                      
+system.ruby.network.routers0.msg_count.Response_Control::1         1336                      
+system.ruby.network.routers0.msg_count.Response_Control::2          799                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0          145                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1          141                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0          291                      
+system.ruby.network.routers0.msg_bytes.Control::0        11920                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         8328                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1       107280                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1        10688                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2         6392                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0        10440                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1        10152                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0         2328                      
+system.ruby.network.routers1.percent_links_utilized     7.332278                      
+system.ruby.network.routers1.msg_count.Control::0         2950                      
+system.ruby.network.routers1.msg_count.Request_Control::2         1041                      
+system.ruby.network.routers1.msg_count.Response_Data::1         3227                      
+system.ruby.network.routers1.msg_count.Response_Control::1         3963                      
+system.ruby.network.routers1.msg_count.Response_Control::2          799                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0          145                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1          141                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0          291                      
+system.ruby.network.routers1.msg_bytes.Control::0        23600                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         8328                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1       232344                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1        31704                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2         6392                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0        10440                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1        10152                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0         2328                      
+system.ruby.network.routers2.percent_links_utilized     3.556049                      
+system.ruby.network.routers2.msg_count.Control::0         1460                      
+system.ruby.network.routers2.msg_count.Response_Data::1         1737                      
+system.ruby.network.routers2.msg_count.Response_Control::1         2627                      
+system.ruby.network.routers2.msg_bytes.Control::0        11680                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1       125064                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1        21016                      
+system.ruby.network.routers3.percent_links_utilized     4.888185                      
+system.ruby.network.routers3.msg_count.Control::0         2950                      
+system.ruby.network.routers3.msg_count.Request_Control::2         1041                      
+system.ruby.network.routers3.msg_count.Response_Data::1         3227                      
+system.ruby.network.routers3.msg_count.Response_Control::1         3963                      
+system.ruby.network.routers3.msg_count.Response_Control::2          799                      
+system.ruby.network.routers3.msg_count.Writeback_Data::0          145                      
+system.ruby.network.routers3.msg_count.Writeback_Data::1          141                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0          291                      
+system.ruby.network.routers3.msg_bytes.Control::0        23600                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         8328                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1       232344                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1        31704                      
+system.ruby.network.routers3.msg_bytes.Response_Control::2         6392                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0        10440                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1        10152                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0         2328                      
+system.ruby.network.msg_count.Control            8850                      
+system.ruby.network.msg_count.Request_Control         3123                      
+system.ruby.network.msg_count.Response_Data         9681                      
+system.ruby.network.msg_count.Response_Control        14286                      
+system.ruby.network.msg_count.Writeback_Data          858                      
+system.ruby.network.msg_count.Writeback_Control          873                      
+system.ruby.network.msg_byte.Control            70800                      
+system.ruby.network.msg_byte.Request_Control        24984                      
+system.ruby.network.msg_byte.Response_Data       697032                      
+system.ruby.network.msg_byte.Response_Control       114288                      
+system.ruby.network.msg_byte.Writeback_Data        61776                      
+system.ruby.network.msg_byte.Writeback_Control         6984                      
 system.ruby.network.routers0.throttle0.link_utilization     5.369057                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2         1041                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1         1490                      
@@ -609,9 +614,9 @@ system.ruby.LD.miss_latency_hist::total           583
 system.ruby.ST.latency_hist::bucket_size           64                      
 system.ruby.ST.latency_hist::max_bucket           639                      
 system.ruby.ST.latency_hist::samples              865                      
-system.ruby.ST.latency_hist::mean           17.899422                      
-system.ruby.ST.latency_hist::gmean           6.261931                      
-system.ruby.ST.latency_hist::stdev          30.808929                      
+system.ruby.ST.latency_hist::mean           17.890173                      
+system.ruby.ST.latency_hist::gmean           6.261514                      
+system.ruby.ST.latency_hist::stdev          30.772511                      
 system.ruby.ST.latency_hist              |         767     88.67%     88.67% |          95     10.98%     99.65% |           1      0.12%     99.77% |           0      0.00%     99.77% |           0      0.00%     99.77% |           2      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.latency_hist::total                865                      
 system.ruby.ST.hit_latency_hist::bucket_size            1                      
@@ -624,17 +629,17 @@ system.ruby.ST.hit_latency_hist::total            649
 system.ruby.ST.miss_latency_hist::bucket_size           64                      
 system.ruby.ST.miss_latency_hist::max_bucket          639                      
 system.ruby.ST.miss_latency_hist::samples          216                      
-system.ruby.ST.miss_latency_hist::mean      62.666667                      
-system.ruby.ST.miss_latency_hist::gmean     57.141141                      
-system.ruby.ST.miss_latency_hist::stdev     33.628615                      
+system.ruby.ST.miss_latency_hist::mean      62.629630                      
+system.ruby.ST.miss_latency_hist::gmean     57.125913                      
+system.ruby.ST.miss_latency_hist::stdev     33.544027                      
 system.ruby.ST.miss_latency_hist         |         118     54.63%     54.63% |          95     43.98%     98.61% |           1      0.46%     99.07% |           0      0.00%     99.07% |           0      0.00%     99.07% |           2      0.93%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.ST.miss_latency_hist::total           216                      
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean       11.389844                      
-system.ruby.IFETCH.latency_hist::gmean       4.264766                      
-system.ruby.IFETCH.latency_hist::stdev      26.115167                      
+system.ruby.IFETCH.latency_hist::mean       11.391094                      
+system.ruby.IFETCH.latency_hist::gmean       4.264782                      
+system.ruby.IFETCH.latency_hist::stdev      26.130654                      
 system.ruby.IFETCH.latency_hist          |        5714     89.28%     89.28% |         673     10.52%     99.80% |           1      0.02%     99.81% |           2      0.03%     99.84% |           5      0.08%     99.92% |           5      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
@@ -647,11 +652,21 @@ system.ruby.IFETCH.hit_latency_hist::total         5709
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          691                      
-system.ruby.IFETCH.miss_latency_hist::mean    80.706223                      
-system.ruby.IFETCH.miss_latency_hist::gmean    78.001693                      
-system.ruby.IFETCH.miss_latency_hist::stdev    30.507480                      
+system.ruby.IFETCH.miss_latency_hist::mean    80.717800                      
+system.ruby.IFETCH.miss_latency_hist::gmean    78.004389                      
+system.ruby.IFETCH.miss_latency_hist::stdev    30.603968                      
 system.ruby.IFETCH.miss_latency_hist     |           5      0.72%      0.72% |         673     97.40%     98.12% |           1      0.14%     98.26% |           2      0.29%     98.55% |           5      0.72%     99.28% |           5      0.72%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          691                      
+system.ruby.Directory_Controller.Fetch           1460      0.00%      0.00%
+system.ruby.Directory_Controller.Data             277      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1460      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          277      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement         1175      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch         1460      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data           277      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement         1175      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data         1460      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          277      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load              1183      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            6400      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
@@ -716,15 +731,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data          570      0.00%      0.00%
 system.ruby.L2Cache_Controller.IS.Mem_Data          686      0.00%      0.00%
 system.ruby.L2Cache_Controller.IM.Mem_Data          204      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          799      0.00%      0.00%
-system.ruby.Directory_Controller.Fetch           1460      0.00%      0.00%
-system.ruby.Directory_Controller.Data             277      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1460      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          277      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement         1175      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch         1460      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data           277      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement         1175      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data         1460      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          277      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000126                       # Nu
 sim_ticks                                      126195                       # Number of ticks simulated
 final_tick                                     126195                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  17040                       # Simulator instruction rate (inst/s)
-host_op_rate                                    17039                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 336486                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 440076                       # Number of bytes of host memory used
-host_seconds                                     0.38                       # Real time elapsed on the host
+host_inst_rate                                  43805                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43801                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 864948                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 454088                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -230,148 +230,42 @@ system.mem_ctrls.busUtil                         4.32                       # Da
 system.mem_ctrls.busUtilRead                     4.00                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.32                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      22.41                       # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      22.42                       # Average write queue length when enqueuing
 system.mem_ctrls.readRowHits                      799                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      76                       # Number of row buffer hits during writes
 system.mem_ctrls.readRowHitRate                 79.19                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                68.47                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         91.66                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    78.12                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE            232                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            4160                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT          120458                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  551880                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                 1035720                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  306600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  575400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                4992000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                7450560                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                186624                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                663552                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             8136960                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             8136960                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            64157832                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            84064968                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0            18622800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             1160400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              96954696                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1             103087560                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           776.656541                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           825.783908                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8449                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8449                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              13.937855                      
-system.ruby.latency_hist::gmean              4.957822                      
-system.ruby.latency_hist::stdev             28.418252                      
-system.ruby.latency_hist                 |        7438     88.04%     88.04% |         992     11.74%     99.79% |           2      0.02%     99.81% |           1      0.01%     99.82% |          11      0.13%     99.95% |           3      0.04%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  8448                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            7027                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        7027    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              7027                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples           1421                      
-system.ruby.miss_latency_hist::mean         68.026742                      
-system.ruby.miss_latency_hist::gmean        59.451623                      
-system.ruby.miss_latency_hist::stdev        35.838026                      
-system.ruby.miss_latency_hist            |         411     28.92%     28.92% |         992     69.81%     98.73% |           2      0.14%     98.87% |           1      0.07%     98.94% |          11      0.77%     99.72% |           3      0.21%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1421                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits         1273                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          775                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   551880                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   306600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4992000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 186624                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              8136960                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             64142784                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             18636000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               96952848                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            776.641738                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        31414                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          4160                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         90106                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1035720                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   575400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 7450560                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              8136960                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             84064968                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1160400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy              103087560                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            825.783908                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1262                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          4160                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        119428                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.974286                      
-system.ruby.network.routers0.msg_count.Request_Control::0         1421                      
-system.ruby.network.routers0.msg_count.Response_Data::2         1182                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2          239                      
-system.ruby.network.routers0.msg_count.Writeback_Data::2         1308                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0         2708                      
-system.ruby.network.routers0.msg_count.Unblock_Control::2         1467                      
-system.ruby.network.routers0.msg_bytes.Request_Control::0        11368                      
-system.ruby.network.routers0.msg_bytes.Response_Data::2        85104                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2        17208                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2        94176                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0        21664                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2        11736                      
-system.ruby.l2_cntrl0.L2cache.demand_hits          239                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses         1182                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses         1421                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     8.972820                      
-system.ruby.network.routers1.msg_count.Request_Control::0         1421                      
-system.ruby.network.routers1.msg_count.Request_Control::1         1182                      
-system.ruby.network.routers1.msg_count.Response_Data::2         2364                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2          239                      
-system.ruby.network.routers1.msg_count.Writeback_Data::2         1502                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0         2708                      
-system.ruby.network.routers1.msg_count.Writeback_Control::1          388                      
-system.ruby.network.routers1.msg_count.Unblock_Control::2         2649                      
-system.ruby.network.routers1.msg_bytes.Request_Control::0        11368                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         9456                      
-system.ruby.network.routers1.msg_bytes.Response_Data::2       170208                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2        17208                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2       108144                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0        21664                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1         3104                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2        21192                      
-system.ruby.network.routers2.percent_links_utilized     2.998534                      
-system.ruby.network.routers2.msg_count.Request_Control::1         1182                      
-system.ruby.network.routers2.msg_count.Response_Data::2         1182                      
-system.ruby.network.routers2.msg_count.Writeback_Data::2          194                      
-system.ruby.network.routers2.msg_count.Writeback_Control::1          388                      
-system.ruby.network.routers2.msg_count.Unblock_Control::2         1182                      
-system.ruby.network.routers2.msg_bytes.Request_Control::1         9456                      
-system.ruby.network.routers2.msg_bytes.Response_Data::2        85104                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2        13968                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1         3104                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2         9456                      
-system.ruby.network.routers3.percent_links_utilized     5.981880                      
-system.ruby.network.routers3.msg_count.Request_Control::0         1421                      
-system.ruby.network.routers3.msg_count.Request_Control::1         1182                      
-system.ruby.network.routers3.msg_count.Response_Data::2         2364                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2          239                      
-system.ruby.network.routers3.msg_count.Writeback_Data::2         1502                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0         2708                      
-system.ruby.network.routers3.msg_count.Writeback_Control::1          388                      
-system.ruby.network.routers3.msg_count.Unblock_Control::2         2649                      
-system.ruby.network.routers3.msg_bytes.Request_Control::0        11368                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         9456                      
-system.ruby.network.routers3.msg_bytes.Response_Data::2       170208                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2        17208                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2       108144                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0        21664                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1         3104                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2        21192                      
-system.ruby.network.msg_count.Request_Control         7809                      
-system.ruby.network.msg_count.Response_Data         7092                      
-system.ruby.network.msg_count.ResponseL2hit_Data          717                      
-system.ruby.network.msg_count.Writeback_Data         4506                      
-system.ruby.network.msg_count.Writeback_Control         9288                      
-system.ruby.network.msg_count.Unblock_Control         7947                      
-system.ruby.network.msg_byte.Request_Control        62472                      
-system.ruby.network.msg_byte.Response_Data       510624                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        51624                      
-system.ruby.network.msg_byte.Writeback_Data       324432                      
-system.ruby.network.msg_byte.Writeback_Control        74304                      
-system.ruby.network.msg_byte.Unblock_Control        63576                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -463,6 +357,117 @@ system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         8449                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8449                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                8448                      
+system.ruby.latency_hist::mean              13.937855                      
+system.ruby.latency_hist::gmean              4.957827                      
+system.ruby.latency_hist::stdev             28.413153                      
+system.ruby.latency_hist                 |        7438     88.04%     88.04% |         992     11.74%     99.79% |           2      0.02%     99.81% |           1      0.01%     99.82% |          11      0.13%     99.95% |           3      0.04%     99.99% |           1      0.01%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  8448                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            7027                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        7027    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              7027                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples           1421                      
+system.ruby.miss_latency_hist::mean         68.026742                      
+system.ruby.miss_latency_hist::gmean        59.451968                      
+system.ruby.miss_latency_hist::stdev        35.813966                      
+system.ruby.miss_latency_hist            |         411     28.92%     28.92% |         992     69.81%     98.73% |           2      0.14%     98.87% |           1      0.07%     98.94% |          11      0.77%     99.72% |           3      0.21%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1421                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits         1273                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          775                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits          239                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses         1182                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses         1421                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     5.974286                      
+system.ruby.network.routers0.msg_count.Request_Control::0         1421                      
+system.ruby.network.routers0.msg_count.Response_Data::2         1182                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2          239                      
+system.ruby.network.routers0.msg_count.Writeback_Data::2         1308                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0         2708                      
+system.ruby.network.routers0.msg_count.Unblock_Control::2         1467                      
+system.ruby.network.routers0.msg_bytes.Request_Control::0        11368                      
+system.ruby.network.routers0.msg_bytes.Response_Data::2        85104                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2        17208                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2        94176                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0        21664                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2        11736                      
+system.ruby.network.routers1.percent_links_utilized     8.972820                      
+system.ruby.network.routers1.msg_count.Request_Control::0         1421                      
+system.ruby.network.routers1.msg_count.Request_Control::1         1182                      
+system.ruby.network.routers1.msg_count.Response_Data::2         2364                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2          239                      
+system.ruby.network.routers1.msg_count.Writeback_Data::2         1502                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0         2708                      
+system.ruby.network.routers1.msg_count.Writeback_Control::1          388                      
+system.ruby.network.routers1.msg_count.Unblock_Control::2         2649                      
+system.ruby.network.routers1.msg_bytes.Request_Control::0        11368                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         9456                      
+system.ruby.network.routers1.msg_bytes.Response_Data::2       170208                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2        17208                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2       108144                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0        21664                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::1         3104                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2        21192                      
+system.ruby.network.routers2.percent_links_utilized     2.998534                      
+system.ruby.network.routers2.msg_count.Request_Control::1         1182                      
+system.ruby.network.routers2.msg_count.Response_Data::2         1182                      
+system.ruby.network.routers2.msg_count.Writeback_Data::2          194                      
+system.ruby.network.routers2.msg_count.Writeback_Control::1          388                      
+system.ruby.network.routers2.msg_count.Unblock_Control::2         1182                      
+system.ruby.network.routers2.msg_bytes.Request_Control::1         9456                      
+system.ruby.network.routers2.msg_bytes.Response_Data::2        85104                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::2        13968                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::1         3104                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2         9456                      
+system.ruby.network.routers3.percent_links_utilized     5.981880                      
+system.ruby.network.routers3.msg_count.Request_Control::0         1421                      
+system.ruby.network.routers3.msg_count.Request_Control::1         1182                      
+system.ruby.network.routers3.msg_count.Response_Data::2         2364                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2          239                      
+system.ruby.network.routers3.msg_count.Writeback_Data::2         1502                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0         2708                      
+system.ruby.network.routers3.msg_count.Writeback_Control::1          388                      
+system.ruby.network.routers3.msg_count.Unblock_Control::2         2649                      
+system.ruby.network.routers3.msg_bytes.Request_Control::0        11368                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         9456                      
+system.ruby.network.routers3.msg_bytes.Response_Data::2       170208                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2        17208                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2       108144                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0        21664                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1         3104                      
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2        21192                      
+system.ruby.network.msg_count.Request_Control         7809                      
+system.ruby.network.msg_count.Response_Data         7092                      
+system.ruby.network.msg_count.ResponseL2hit_Data          717                      
+system.ruby.network.msg_count.Writeback_Data         4506                      
+system.ruby.network.msg_count.Writeback_Control         9288                      
+system.ruby.network.msg_count.Unblock_Control         7947                      
+system.ruby.network.msg_byte.Request_Control        62472                      
+system.ruby.network.msg_byte.Response_Data       510624                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        51624                      
+system.ruby.network.msg_byte.Writeback_Data       324432                      
+system.ruby.network.msg_byte.Writeback_Control        74304                      
+system.ruby.network.msg_byte.Unblock_Control        63576                      
 system.ruby.network.routers0.throttle0.link_utilization     5.603629                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2         1182                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2          239                      
@@ -553,9 +558,9 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2         9456
 system.ruby.LD.latency_hist::bucket_size           64                      
 system.ruby.LD.latency_hist::max_bucket           639                      
 system.ruby.LD.latency_hist::samples             1183                      
-system.ruby.LD.latency_hist::mean           29.355030                      
-system.ruby.LD.latency_hist::gmean          10.774857                      
-system.ruby.LD.latency_hist::stdev          36.604149                      
+system.ruby.LD.latency_hist::mean           29.370245                      
+system.ruby.LD.latency_hist::gmean          10.775321                      
+system.ruby.LD.latency_hist::stdev          36.738545                      
 system.ruby.LD.latency_hist              |         860     72.70%     72.70% |         320     27.05%     99.75% |           0      0.00%     99.75% |           0      0.00%     99.75% |           2      0.17%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.latency_hist::total               1183                      
 system.ruby.LD.hit_latency_hist::bucket_size            1                      
@@ -568,9 +573,9 @@ system.ruby.LD.hit_latency_hist::total            658
 system.ruby.LD.miss_latency_hist::bucket_size           64                      
 system.ruby.LD.miss_latency_hist::max_bucket          639                      
 system.ruby.LD.miss_latency_hist::samples          525                      
-system.ruby.LD.miss_latency_hist::mean      62.386667                      
-system.ruby.LD.miss_latency_hist::gmean     53.502649                      
-system.ruby.LD.miss_latency_hist::stdev     32.511258                      
+system.ruby.LD.miss_latency_hist::mean      62.420952                      
+system.ruby.LD.miss_latency_hist::gmean     53.507846                      
+system.ruby.LD.miss_latency_hist::stdev     32.816863                      
 system.ruby.LD.miss_latency_hist         |         202     38.48%     38.48% |         320     60.95%     99.43% |           0      0.00%     99.43% |           0      0.00%     99.43% |           2      0.38%     99.81% |           1      0.19%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.LD.miss_latency_hist::total           525                      
 system.ruby.ST.latency_hist::bucket_size           64                      
@@ -599,9 +604,9 @@ system.ruby.ST.miss_latency_hist::total           250
 system.ruby.IFETCH.latency_hist::bucket_size           64                      
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
-system.ruby.IFETCH.latency_hist::mean       10.378594                      
-system.ruby.IFETCH.latency_hist::gmean       4.114908                      
-system.ruby.IFETCH.latency_hist::stdev      25.040800                      
+system.ruby.IFETCH.latency_hist::mean       10.375781                      
+system.ruby.IFETCH.latency_hist::gmean       4.114880                      
+system.ruby.IFETCH.latency_hist::stdev      24.994631                      
 system.ruby.IFETCH.latency_hist          |        5825     91.02%     91.02% |         564      8.81%     99.83% |           0      0.00%     99.83% |           1      0.02%     99.84% |           8      0.12%     99.97% |           1      0.02%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            1                      
@@ -614,11 +619,33 @@ system.ruby.IFETCH.hit_latency_hist::total         5754
 system.ruby.IFETCH.miss_latency_hist::bucket_size           64                      
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          646                      
-system.ruby.IFETCH.miss_latency_hist::mean    76.100619                      
-system.ruby.IFETCH.miss_latency_hist::gmean    68.669414                      
-system.ruby.IFETCH.miss_latency_hist::stdev    37.537546                      
+system.ruby.IFETCH.miss_latency_hist::mean    76.072755                      
+system.ruby.IFETCH.miss_latency_hist::gmean    68.664868                      
+system.ruby.IFETCH.miss_latency_hist::stdev    37.280241                      
 system.ruby.IFETCH.miss_latency_hist     |          71     10.99%     10.99% |         564     87.31%     98.30% |           0      0.00%     98.30% |           1      0.15%     98.45% |           8      1.24%     99.69% |           1      0.15%     99.85% |           1      0.15%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          646                      
+system.ruby.Directory_Controller.GETX             198      0.00%      0.00%
+system.ruby.Directory_Controller.GETS             984      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             194      0.00%      0.00%
+system.ruby.Directory_Controller.Unblock          466      0.00%      0.00%
+system.ruby.Directory_Controller.Last_Unblock          518      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock          198      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback          194      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1182      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          194      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           111      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS           466      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack          194      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETX            87      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETS           518      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           194      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Unblock          466      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data          466      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock          518      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Memory_Data          518      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock          198      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data          198      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback          194      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load              1183      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            6400      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
@@ -696,27 +723,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           52      0.00%
 system.ruby.L2Cache_Controller.SS.Unblock          141      0.00%      0.00%
 system.ruby.L2Cache_Controller.OO.Exclusive_Unblock           46      0.00%      0.00%
 system.ruby.L2Cache_Controller.MI.Writeback_Ack          194      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             198      0.00%      0.00%
-system.ruby.Directory_Controller.GETS             984      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             194      0.00%      0.00%
-system.ruby.Directory_Controller.Unblock          466      0.00%      0.00%
-system.ruby.Directory_Controller.Last_Unblock          518      0.00%      0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock          198      0.00%      0.00%
-system.ruby.Directory_Controller.Dirty_Writeback          194      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1182      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          194      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           111      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS           466      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack          194      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETX            87      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETS           518      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           194      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Unblock          466      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data          466      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock          518      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Memory_Data          518      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock          198      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data          198      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback          194      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000117                       # Nu
 sim_ticks                                      116770                       # Number of ticks simulated
 final_tick                                     116770                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                    333                       # Simulator instruction rate (inst/s)
-host_op_rate                                      333                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                   6085                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436992                       # Number of bytes of host memory used
-host_seconds                                    19.19                       # Real time elapsed on the host
+host_inst_rate                                  63656                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63646                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1162909                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451252                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -236,143 +236,35 @@ system.mem_ctrls.readRowHitRate                 79.80                       # Ro
 system.mem_ctrls.writeRowHitRate                77.31                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         83.10                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    79.54                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             22                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            3640                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT          105625                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  514080                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  937440                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  285600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  520800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                5041920                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                6764160                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                269568                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                725760                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             7119840                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             7119840                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            60929352                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            72381564                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0            12117000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             2071200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              86277360                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              90520764                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           789.557896                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           828.390947                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8449                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8449                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              12.822206                      
-system.ruby.latency_hist::gmean              3.506831                      
-system.ruby.latency_hist::stdev             27.804874                      
-system.ruby.latency_hist                 |        7433     87.99%     87.99% |         995     11.78%     99.76% |           6      0.07%     99.83% |           2      0.02%     99.86% |           8      0.09%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  8448                      
-system.ruby.hit_latency_hist::bucket_size            4                      
-system.ruby.hit_latency_hist::max_bucket           39                      
-system.ruby.hit_latency_hist::samples            7272                      
-system.ruby.hit_latency_hist::mean           2.641777                      
-system.ruby.hit_latency_hist::gmean          2.147878                      
-system.ruby.hit_latency_hist::stdev          3.755596                      
-system.ruby.hit_latency_hist             |        7065     97.15%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |          24      0.33%     97.48% |         183      2.52%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              7272                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples           1176                      
-system.ruby.miss_latency_hist::mean         75.774660                      
-system.ruby.miss_latency_hist::gmean        72.686076                      
-system.ruby.miss_latency_hist::stdev        29.372665                      
-system.ruby.miss_latency_hist            |         161     13.69%     13.69% |         995     84.61%     98.30% |           6      0.51%     98.81% |           2      0.17%     98.98% |           8      0.68%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1176                      
-system.ruby.Directory.incomplete_times           1175                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits         1311                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          737                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   514080                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   285600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5041920                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 269568                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             60923196                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy             12117000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               86271204                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            789.566591                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        22175                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         85821                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   937440                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   520800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 6764160                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 725760                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              7119840                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             72391140                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              2062800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               90521940                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            828.401709                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         2878                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3640                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT        102769                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.578702                      
-system.ruby.network.routers0.msg_count.Request_Control::1         1383                      
-system.ruby.network.routers0.msg_count.Response_Data::4         1176                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4          207                      
-system.ruby.network.routers0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.msg_count.Writeback_Data::4         1354                      
-system.ruby.network.routers0.msg_count.Persistent_Control::3           40                      
-system.ruby.network.routers0.msg_bytes.Request_Control::1        11064                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        84672                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4        14904                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4        97488                      
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3          320                      
-system.ruby.l2_cntrl0.L2cache.demand_hits          189                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses         1194                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses         1383                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     4.210200                      
-system.ruby.network.routers1.msg_count.Request_Control::1         1383                      
-system.ruby.network.routers1.msg_count.Request_Control::2         1194                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4          207                      
-system.ruby.network.routers1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.msg_count.Writeback_Data::4         1582                      
-system.ruby.network.routers1.msg_count.Writeback_Control::4          966                      
-system.ruby.network.routers1.msg_count.Persistent_Control::3           20                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1        11064                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         9552                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4        14904                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4       113904                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4         7728                      
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers2.percent_links_utilized     3.172048                      
-system.ruby.network.routers2.msg_count.Request_Control::2         1194                      
-system.ruby.network.routers2.msg_count.Response_Data::4         1176                      
-system.ruby.network.routers2.msg_count.Writeback_Data::4          228                      
-system.ruby.network.routers2.msg_count.Writeback_Control::4          966                      
-system.ruby.network.routers2.msg_count.Persistent_Control::3           20                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         9552                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        84672                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4        16416                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4         7728                      
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3          160                      
-system.ruby.network.routers3.percent_links_utilized     4.320316                      
-system.ruby.network.routers3.msg_count.Request_Control::1         1383                      
-system.ruby.network.routers3.msg_count.Request_Control::2         1194                      
-system.ruby.network.routers3.msg_count.Response_Data::4         1176                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4          207                      
-system.ruby.network.routers3.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.msg_count.Writeback_Data::4         1582                      
-system.ruby.network.routers3.msg_count.Writeback_Control::4          966                      
-system.ruby.network.routers3.msg_count.Persistent_Control::3           40                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1        11064                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         9552                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4        84672                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4        14904                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4       113904                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4         7728                      
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3          320                      
-system.ruby.network.msg_count.Request_Control         7731                      
-system.ruby.network.msg_count.Response_Data         3528                      
-system.ruby.network.msg_count.ResponseL2hit_Data          621                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         4746                      
-system.ruby.network.msg_count.Writeback_Control         2898                      
-system.ruby.network.msg_count.Persistent_Control          120                      
-system.ruby.network.msg_byte.Request_Control        61848                      
-system.ruby.network.msg_byte.Response_Data       254016                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        44712                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       341712                      
-system.ruby.network.msg_byte.Writeback_Control        23184                      
-system.ruby.network.msg_byte.Persistent_Control          960                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -464,6 +356,119 @@ system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         8449                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8449                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                8448                      
+system.ruby.latency_hist::mean              12.822206                      
+system.ruby.latency_hist::gmean              3.506830                      
+system.ruby.latency_hist::stdev             27.805292                      
+system.ruby.latency_hist                 |        7433     87.99%     87.99% |         995     11.78%     99.76% |           6      0.07%     99.83% |           2      0.02%     99.86% |           8      0.09%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  8448                      
+system.ruby.hit_latency_hist::bucket_size            4                      
+system.ruby.hit_latency_hist::max_bucket           39                      
+system.ruby.hit_latency_hist::samples            7272                      
+system.ruby.hit_latency_hist::mean           2.641777                      
+system.ruby.hit_latency_hist::gmean          2.147878                      
+system.ruby.hit_latency_hist::stdev          3.755596                      
+system.ruby.hit_latency_hist             |        7065     97.15%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |           0      0.00%     97.15% |          24      0.33%     97.48% |         183      2.52%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              7272                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples           1176                      
+system.ruby.miss_latency_hist::mean         75.774660                      
+system.ruby.miss_latency_hist::gmean        72.686009                      
+system.ruby.miss_latency_hist::stdev        29.375504                      
+system.ruby.miss_latency_hist            |         161     13.69%     13.69% |         995     84.61%     98.30% |           6      0.51%     98.81% |           2      0.17%     98.98% |           8      0.68%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1176                      
+system.ruby.Directory.incomplete_times           1175                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits         1311                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          737                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits          189                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses         1194                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses         1383                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     5.578702                      
+system.ruby.network.routers0.msg_count.Request_Control::1         1383                      
+system.ruby.network.routers0.msg_count.Response_Data::4         1176                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4          207                      
+system.ruby.network.routers0.msg_count.Response_Control::4            1                      
+system.ruby.network.routers0.msg_count.Writeback_Data::4         1354                      
+system.ruby.network.routers0.msg_count.Persistent_Control::3           40                      
+system.ruby.network.routers0.msg_bytes.Request_Control::1        11064                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        84672                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4        14904                      
+system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4        97488                      
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3          320                      
+system.ruby.network.routers1.percent_links_utilized     4.210200                      
+system.ruby.network.routers1.msg_count.Request_Control::1         1383                      
+system.ruby.network.routers1.msg_count.Request_Control::2         1194                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4          207                      
+system.ruby.network.routers1.msg_count.Response_Control::4            1                      
+system.ruby.network.routers1.msg_count.Writeback_Data::4         1582                      
+system.ruby.network.routers1.msg_count.Writeback_Control::4          966                      
+system.ruby.network.routers1.msg_count.Persistent_Control::3           20                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1        11064                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         9552                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4        14904                      
+system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4       113904                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4         7728                      
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3          160                      
+system.ruby.network.routers2.percent_links_utilized     3.172048                      
+system.ruby.network.routers2.msg_count.Request_Control::2         1194                      
+system.ruby.network.routers2.msg_count.Response_Data::4         1176                      
+system.ruby.network.routers2.msg_count.Writeback_Data::4          228                      
+system.ruby.network.routers2.msg_count.Writeback_Control::4          966                      
+system.ruby.network.routers2.msg_count.Persistent_Control::3           20                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         9552                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        84672                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::4        16416                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4         7728                      
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3          160                      
+system.ruby.network.routers3.percent_links_utilized     4.320316                      
+system.ruby.network.routers3.msg_count.Request_Control::1         1383                      
+system.ruby.network.routers3.msg_count.Request_Control::2         1194                      
+system.ruby.network.routers3.msg_count.Response_Data::4         1176                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4          207                      
+system.ruby.network.routers3.msg_count.Response_Control::4            1                      
+system.ruby.network.routers3.msg_count.Writeback_Data::4         1582                      
+system.ruby.network.routers3.msg_count.Writeback_Control::4          966                      
+system.ruby.network.routers3.msg_count.Persistent_Control::3           40                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1        11064                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         9552                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4        84672                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4        14904                      
+system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4       113904                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4         7728                      
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3          320                      
+system.ruby.network.msg_count.Request_Control         7731                      
+system.ruby.network.msg_count.Response_Data         3528                      
+system.ruby.network.msg_count.ResponseL2hit_Data          621                      
+system.ruby.network.msg_count.Response_Control            3                      
+system.ruby.network.msg_count.Writeback_Data         4746                      
+system.ruby.network.msg_count.Writeback_Control         2898                      
+system.ruby.network.msg_count.Persistent_Control          120                      
+system.ruby.network.msg_byte.Request_Control        61848                      
+system.ruby.network.msg_byte.Response_Data       254016                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        44712                      
+system.ruby.network.msg_byte.Response_Control           24                      
+system.ruby.network.msg_byte.Writeback_Data       341712                      
+system.ruby.network.msg_byte.Writeback_Control        23184                      
+system.ruby.network.msg_byte.Persistent_Control          960                      
 system.ruby.network.routers0.throttle0.link_utilization     5.338700                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1176                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4          207                      
@@ -585,8 +590,8 @@ system.ruby.IFETCH.latency_hist::bucket_size           64
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
 system.ruby.IFETCH.latency_hist::mean        9.334062                      
-system.ruby.IFETCH.latency_hist::gmean       2.862492                      
-system.ruby.IFETCH.latency_hist::stdev      24.015420                      
+system.ruby.IFETCH.latency_hist::gmean       2.862491                      
+system.ruby.IFETCH.latency_hist::stdev      24.016058                      
 system.ruby.IFETCH.latency_hist          |        5815     90.86%     90.86% |         573      8.95%     99.81% |           4      0.06%     99.87% |           0      0.00%     99.87% |           7      0.11%     99.98% |           1      0.02%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            4                      
@@ -601,8 +606,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size           64
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          585                      
 system.ruby.IFETCH.miss_latency_hist::mean    79.849573                      
-system.ruby.IFETCH.miss_latency_hist::gmean    77.699187                      
-system.ruby.IFETCH.miss_latency_hist::stdev    27.986383                      
+system.ruby.IFETCH.miss_latency_hist::gmean    77.699044                      
+system.ruby.IFETCH.miss_latency_hist::stdev    27.992378                      
 system.ruby.IFETCH.miss_latency_hist     |           0      0.00%      0.00% |         573     97.95%     97.95% |           4      0.68%     98.63% |           0      0.00%     98.63% |           7      1.20%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          585                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
@@ -624,8 +629,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size           64
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1176                      
 system.ruby.Directory.miss_mach_latency_hist::mean    75.774660                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    72.686076                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    29.372665                      
+system.ruby.Directory.miss_mach_latency_hist::gmean    72.686009                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    29.375504                      
 system.ruby.Directory.miss_mach_latency_hist |         161     13.69%     13.69% |         995     84.61%     98.30% |           6      0.51%     98.81% |           2      0.17%     98.98% |           8      0.68%     99.66% |           4      0.34%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1176                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
@@ -719,10 +724,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          585                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    79.849573                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    77.699187                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    27.986383                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    77.699044                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    27.992378                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         573     97.95%     97.95% |           4      0.68%     98.63% |           0      0.00%     98.63% |           7      1.20%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          585                      
+system.ruby.Directory_Controller.GETX             209      0.00%      0.00%
+system.ruby.Directory_Controller.GETS            1013      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown           10      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown           10      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner            9      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens          219      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner           29      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens          903      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens           34      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1176      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          228      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX           168      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS          1008      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens           34      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX           18      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Lockdown            1      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner            9      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens          219      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner           29      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens          903      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown           10      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETX           23      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETS            5      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack          228      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data            9      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown            9      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data         1167      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load              1183      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            6400      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
@@ -796,32 +828,5 @@ system.ruby.L2Cache_Controller.M.L1_GETX           26      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L2_Replacement         1122      0.00%      0.00%
 system.ruby.L2Cache_Controller.I_L.Persistent_GETX            1      0.00%      0.00%
 system.ruby.L2Cache_Controller.I_L.Persistent_GETS            9      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             209      0.00%      0.00%
-system.ruby.Directory_Controller.GETS            1013      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown           10      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown           10      0.00%      0.00%
-system.ruby.Directory_Controller.Data_Owner            9      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens          219      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner           29      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens          903      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens           34      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1176      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          228      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX           168      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS          1008      0.00%      0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens           34      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX           18      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Lockdown            1      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_Owner            9      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens          219      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner           29      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens          903      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown           10      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETX           23      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETS            5      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack          228      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data            9      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown            9      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data         1167      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000096                       # Nu
 sim_ticks                                       96381                       # Number of ticks simulated
 final_tick                                      96381                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32379                       # Simulator instruction rate (inst/s)
-host_op_rate                                    32376                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 488288                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436896                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  66831                       # Simulator instruction rate (inst/s)
+host_op_rate                                    66821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1007748                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449612                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -186,12 +186,12 @@ system.mem_ctrls.wrQLenPdf::62                      0                       # Wh
 system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
 system.mem_ctrls.bytesPerActivate::samples          194                       # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::mean    352.659794                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean   218.108055                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev   333.620332                       # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127           54     27.84%     27.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255           51     26.29%     54.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383           19      9.79%     63.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511           16      8.25%     72.16% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean   217.534506                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev   333.874690                       # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127           55     28.35%     28.35% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255           50     25.77%     54.12% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383           18      9.28%     63.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511           17      8.76%     72.16% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::512-639           12      6.19%     78.35% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::640-767            7      3.61%     81.96% # Bytes accessed per row activation
 system.mem_ctrls.bytesPerActivate::768-895            7      3.61%     85.57% # Bytes accessed per row activation
@@ -231,138 +231,42 @@ system.mem_ctrls.busUtil                         5.65                       # Da
 system.mem_ctrls.busUtilRead                     5.20                       # Data bus utilization in percentage for reads
 system.mem_ctrls.busUtilWrite                    0.45                       # Data bus utilization in percentage for writes
 system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen                      21.25                       # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen                      21.24                       # Average write queue length when enqueuing
 system.mem_ctrls.readRowHits                      808                       # Number of row buffer hits during reads
 system.mem_ctrls.writeRowHits                      82                       # Number of row buffer hits during writes
 system.mem_ctrls.readRowHitRate                 80.56                       # Row buffer hit rate for reads
 system.mem_ctrls.writeRowHitRate                70.69                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         69.83                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    79.54                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             11                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            3120                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           90575                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  476280                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  975240                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  264600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  541800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                5104320                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                7063680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                238464                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                663552                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             6102720                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            54836964                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            61829496                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0             8112600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             1978800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              75135948                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              79155288                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           801.946249                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           844.845750                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8449                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8449                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              10.408736                      
-system.ruby.latency_hist::gmean              3.320045                      
-system.ruby.latency_hist::stdev             22.997500                      
-system.ruby.latency_hist                 |        8209     97.17%     97.17% |         227      2.69%     99.86% |           0      0.00%     99.86% |           1      0.01%     99.87% |           6      0.07%     99.94% |           5      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  8448                      
-system.ruby.hit_latency_hist::bucket_size            2                      
-system.ruby.hit_latency_hist::max_bucket           19                      
-system.ruby.hit_latency_hist::samples            7289                      
-system.ruby.hit_latency_hist::mean           2.306352                      
-system.ruby.hit_latency_hist::gmean          2.107025                      
-system.ruby.hit_latency_hist::stdev          1.810102                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |        7086     97.21%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |         203      2.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              7289                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples           1159                      
-system.ruby.miss_latency_hist::mean         61.364970                      
-system.ruby.miss_latency_hist::gmean        57.951867                      
-system.ruby.miss_latency_hist::stdev        28.728264                      
-system.ruby.miss_latency_hist            |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           1      0.09%     99.05% |           6      0.52%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1159                      
-system.ruby.Directory.incomplete_times           1158                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.L1Dcache.demand_hits         1332                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          716                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits          203                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses         1159                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses         1362                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   476280                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   264600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 5104320                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                 238464                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             54887580                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              8068200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               75142164                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            802.012594                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        14237                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3120                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         77447                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   975240                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   541800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 7063680                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 663552                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              6102720                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             61908840                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1909200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               79165032                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            844.949750                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         2762                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3120                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         87824                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     4.652888                      
-system.ruby.network.routers0.msg_count.Request_Control::2         1159                      
-system.ruby.network.routers0.msg_count.Response_Data::4         1159                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5          220                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2         1143                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3         1143                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5          923                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5         1159                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         9272                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        83448                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5        15840                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2         9144                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5         7384                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
-system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
-system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     4.652888                      
-system.ruby.network.routers1.msg_count.Request_Control::2         1159                      
-system.ruby.network.routers1.msg_count.Response_Data::4         1159                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5          220                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2         1143                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3         1143                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5          923                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5         1159                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         9272                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        83448                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5        15840                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2         9144                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5         7384                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.routers2.percent_links_utilized     4.652888                      
-system.ruby.network.routers2.msg_count.Request_Control::2         1159                      
-system.ruby.network.routers2.msg_count.Response_Data::4         1159                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5          220                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2         1143                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3         1143                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5          923                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5         1159                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         9272                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        83448                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5        15840                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2         9144                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         9144                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5         7384                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5         9272                      
-system.ruby.network.msg_count.Request_Control         3477                      
-system.ruby.network.msg_count.Response_Data         3477                      
-system.ruby.network.msg_count.Writeback_Data          660                      
-system.ruby.network.msg_count.Writeback_Control         9627                      
-system.ruby.network.msg_count.Unblock_Control         3477                      
-system.ruby.network.msg_byte.Request_Control        27816                      
-system.ruby.network.msg_byte.Response_Data       250344                      
-system.ruby.network.msg_byte.Writeback_Data        47520                      
-system.ruby.network.msg_byte.Writeback_Control        77016                      
-system.ruby.network.msg_byte.Unblock_Control        27816                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -454,6 +358,107 @@ system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         8449                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8449                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                8448                      
+system.ruby.latency_hist::mean              10.408736                      
+system.ruby.latency_hist::gmean              3.320047                      
+system.ruby.latency_hist::stdev             22.995606                      
+system.ruby.latency_hist                 |        8209     97.17%     97.17% |         227      2.69%     99.86% |           0      0.00%     99.86% |           0      0.00%     99.86% |           7      0.08%     99.94% |           5      0.06%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  8448                      
+system.ruby.hit_latency_hist::bucket_size            2                      
+system.ruby.hit_latency_hist::max_bucket           19                      
+system.ruby.hit_latency_hist::samples            7289                      
+system.ruby.hit_latency_hist::mean           2.306352                      
+system.ruby.hit_latency_hist::gmean          2.107025                      
+system.ruby.hit_latency_hist::stdev          1.810102                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |        7086     97.21%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |           0      0.00%     97.21% |         203      2.79%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              7289                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples           1159                      
+system.ruby.miss_latency_hist::mean         61.364970                      
+system.ruby.miss_latency_hist::gmean        57.952099                      
+system.ruby.miss_latency_hist::stdev        28.717200                      
+system.ruby.miss_latency_hist            |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1159                      
+system.ruby.Directory.incomplete_times           1158                      
+system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
+system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
+system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits         1332                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          716                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         5754                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          646                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         6400                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits          203                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses         1159                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses         1362                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     4.652888                      
+system.ruby.network.routers0.msg_count.Request_Control::2         1159                      
+system.ruby.network.routers0.msg_count.Response_Data::4         1159                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5          220                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2         1143                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3         1143                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5          923                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5         1159                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         9272                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        83448                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5        15840                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2         9144                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         9144                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5         7384                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5         9272                      
+system.ruby.network.routers1.percent_links_utilized     4.652888                      
+system.ruby.network.routers1.msg_count.Request_Control::2         1159                      
+system.ruby.network.routers1.msg_count.Response_Data::4         1159                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5          220                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2         1143                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3         1143                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5          923                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5         1159                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         9272                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        83448                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5        15840                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2         9144                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         9144                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5         7384                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5         9272                      
+system.ruby.network.routers2.percent_links_utilized     4.652888                      
+system.ruby.network.routers2.msg_count.Request_Control::2         1159                      
+system.ruby.network.routers2.msg_count.Response_Data::4         1159                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5          220                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2         1143                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3         1143                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5          923                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5         1159                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         9272                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        83448                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5        15840                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2         9144                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         9144                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5         7384                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5         9272                      
+system.ruby.network.msg_count.Request_Control         3477                      
+system.ruby.network.msg_count.Response_Data         3477                      
+system.ruby.network.msg_count.Writeback_Data          660                      
+system.ruby.network.msg_count.Writeback_Control         9627                      
+system.ruby.network.msg_count.Unblock_Control         3477                      
+system.ruby.network.msg_byte.Request_Control        27816                      
+system.ruby.network.msg_byte.Response_Data       250344                      
+system.ruby.network.msg_byte.Writeback_Data        47520                      
+system.ruby.network.msg_byte.Writeback_Control        77016                      
+system.ruby.network.msg_byte.Unblock_Control        27816                      
 system.ruby.network.routers0.throttle0.link_utilization     6.004295                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1159                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1143                      
@@ -554,9 +559,9 @@ system.ruby.IFETCH.latency_hist::bucket_size           64
 system.ruby.IFETCH.latency_hist::max_bucket          639                      
 system.ruby.IFETCH.latency_hist::samples         6400                      
 system.ruby.IFETCH.latency_hist::mean        7.937812                      
-system.ruby.IFETCH.latency_hist::gmean       2.788276                      
-system.ruby.IFETCH.latency_hist::stdev      21.096217                      
-system.ruby.IFETCH.latency_hist          |        6291     98.30%     98.30% |          99      1.55%     99.84% |           0      0.00%     99.84% |           1      0.02%     99.86% |           4      0.06%     99.92% |           5      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.latency_hist::gmean       2.788278                      
+system.ruby.IFETCH.latency_hist::stdev      21.093490                      
+system.ruby.IFETCH.latency_hist          |        6291     98.30%     98.30% |          99      1.55%     99.84% |           0      0.00%     99.84% |           0      0.00%     99.84% |           5      0.08%     99.92% |           5      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.latency_hist::total           6400                      
 system.ruby.IFETCH.hit_latency_hist::bucket_size            2                      
 system.ruby.IFETCH.hit_latency_hist::max_bucket           19                      
@@ -570,9 +575,9 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size           64
 system.ruby.IFETCH.miss_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.miss_latency_hist::samples          581                      
 system.ruby.IFETCH.miss_latency_hist::mean    66.177281                      
-system.ruby.IFETCH.miss_latency_hist::gmean    63.049831                      
-system.ruby.IFETCH.miss_latency_hist::stdev    34.055805                      
-system.ruby.IFETCH.miss_latency_hist     |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           1      0.17%     98.45% |           4      0.69%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.miss_latency_hist::gmean    63.050334                      
+system.ruby.IFETCH.miss_latency_hist::stdev    34.037169                      
+system.ruby.IFETCH.miss_latency_hist     |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           0      0.00%     98.28% |           5      0.86%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          581                      
 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size            1                      
 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket            9                      
@@ -592,9 +597,9 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size           64
 system.ruby.Directory.miss_mach_latency_hist::max_bucket          639                      
 system.ruby.Directory.miss_mach_latency_hist::samples         1159                      
 system.ruby.Directory.miss_mach_latency_hist::mean    61.364970                      
-system.ruby.Directory.miss_mach_latency_hist::gmean    57.951867                      
-system.ruby.Directory.miss_mach_latency_hist::stdev    28.728264                      
-system.ruby.Directory.miss_mach_latency_hist |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           1      0.09%     99.05% |           6      0.52%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.Directory.miss_mach_latency_hist::gmean    57.952099                      
+system.ruby.Directory.miss_mach_latency_hist::stdev    28.717200                      
+system.ruby.Directory.miss_mach_latency_hist |         920     79.38%     79.38% |         227     19.59%     98.96% |           0      0.00%     98.96% |           0      0.00%     98.96% |           7      0.60%     99.57% |           5      0.43%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.Directory.miss_mach_latency_hist::total         1159                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size            1                      
 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket            9                      
@@ -684,10 +689,28 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket          639                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples          581                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean    66.177281                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    63.049831                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    34.055805                      
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           1      0.17%     98.45% |           4      0.69%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    63.050334                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    34.037169                      
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         472     81.24%     81.24% |          99     17.04%     98.28% |           0      0.00%     98.28% |           0      0.00%     98.28% |           5      0.86%     99.14% |           5      0.86%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          581                      
+system.ruby.Directory_Controller.GETX             185      0.00%      0.00%
+system.ruby.Directory_Controller.GETS            1020      0.00%      0.00%
+system.ruby.Directory_Controller.PUT             1143      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM         1159      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean          923      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          220      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1159      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          220      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT          1143      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX           158      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS          1001      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM         1159      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data         1159      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETX           27      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETS           19      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean          923      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          220      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack          220      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load              1191      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            6411      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              892      0.00%      0.00%
@@ -729,23 +752,5 @@ system.ruby.L1Cache_Controller.MI.Store            27      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Writeback_Ack         1143      0.00%      0.00%
 system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1          133      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1           70      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             185      0.00%      0.00%
-system.ruby.Directory_Controller.GETS            1020      0.00%      0.00%
-system.ruby.Directory_Controller.PUT             1143      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM         1159      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean          923      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty          220      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1159      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          220      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT          1143      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX           158      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS          1001      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM         1159      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data         1159      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETX           27      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETS           19      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean          923      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty          220      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack          220      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000124                       # Nu
 sim_ticks                                      123564                       # Number of ticks simulated
 final_tick                                     123564                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  34581                       # Simulator instruction rate (inst/s)
-host_op_rate                                    34578                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 668563                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436724                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  69668                       # Simulator instruction rate (inst/s)
+host_op_rate                                    69633                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1346306                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 450680                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate                 75.06                       # Ro
 system.mem_ctrls.writeRowHitRate                92.52                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         35.73                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    83.97                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE          11701                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            3900                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT          101465                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  771120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                 1081080                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  428400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  600600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                4879680                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                5466240                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0               4281984                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1               4323456                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             7628400                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            69482088                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            69027912                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0             9282000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             9680400                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              96753672                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              97808088                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           826.587089                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           835.595188                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   3456                       # delay histogram for all message
-system.ruby.delayHist                    |        3456    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     3456                       # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         8449                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          8449                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                8448                      
-system.ruby.latency_hist::mean              13.626420                      
-system.ruby.latency_hist::gmean              5.329740                      
-system.ruby.latency_hist::stdev             25.242996                      
-system.ruby.latency_hist                 |        8195     97.01%     97.01% |         199      2.36%     99.36% |          43      0.51%     99.87% |           2      0.02%     99.89% |           5      0.06%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  8448                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            6718                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6718    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              6718                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples           1730                      
-system.ruby.miss_latency_hist::mean         54.891329                      
-system.ruby.miss_latency_hist::gmean        49.648144                      
-system.ruby.miss_latency_hist::stdev        31.153546                      
-system.ruby.miss_latency_hist            |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total             1730                      
-system.ruby.Directory.incomplete_times           1729                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses         1730                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8448                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   771120                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   428400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 4879680                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                4281984                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             69480720                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              9282000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               96752304                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            826.589526                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE        15125                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          3900                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         98100                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                  1081080                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   600600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 5466240                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                4323456                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              7628400                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             69027912                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              9680400                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               97808088                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            835.595188                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE        15368                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          3900                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         97798                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.992328                      
-system.ruby.network.routers0.msg_count.Control::2         1730                      
-system.ruby.network.routers0.msg_count.Data::2         1726                      
-system.ruby.network.routers0.msg_count.Response_Data::4         1730                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3         1726                      
-system.ruby.network.routers0.msg_bytes.Control::2        13840                      
-system.ruby.network.routers0.msg_bytes.Data::2       124272                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4       124560                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers1.percent_links_utilized     6.992328                      
-system.ruby.network.routers1.msg_count.Control::2         1730                      
-system.ruby.network.routers1.msg_count.Data::2         1726                      
-system.ruby.network.routers1.msg_count.Response_Data::4         1730                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3         1726                      
-system.ruby.network.routers1.msg_bytes.Control::2        13840                      
-system.ruby.network.routers1.msg_bytes.Data::2       124272                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4       124560                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.routers2.percent_links_utilized     6.992328                      
-system.ruby.network.routers2.msg_count.Control::2         1730                      
-system.ruby.network.routers2.msg_count.Data::2         1726                      
-system.ruby.network.routers2.msg_count.Response_Data::4         1730                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3         1726                      
-system.ruby.network.routers2.msg_bytes.Control::2        13840                      
-system.ruby.network.routers2.msg_bytes.Data::2       124272                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4       124560                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3        13808                      
-system.ruby.network.msg_count.Control            5190                      
-system.ruby.network.msg_count.Data               5178                      
-system.ruby.network.msg_count.Response_Data         5190                      
-system.ruby.network.msg_count.Writeback_Control         5178                      
-system.ruby.network.msg_byte.Control            41520                      
-system.ruby.network.msg_byte.Data              372816                      
-system.ruby.network.msg_byte.Response_Data       373680                      
-system.ruby.network.msg_byte.Writeback_Control        41424                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite                     868     13.56%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       6400                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
+system.ruby.delayHist::samples                   3456                       # delay histogram for all message
+system.ruby.delayHist                    |        3456    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     3456                       # delay histogram for all message
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         8449                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        8449    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          8449                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                8448                      
+system.ruby.latency_hist::mean              13.626420                      
+system.ruby.latency_hist::gmean              5.329740                      
+system.ruby.latency_hist::stdev             25.242996                      
+system.ruby.latency_hist                 |        8195     97.01%     97.01% |         199      2.36%     99.36% |          43      0.51%     99.87% |           2      0.02%     99.89% |           5      0.06%     99.95% |           4      0.05%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  8448                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            6718                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        6718    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              6718                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples           1730                      
+system.ruby.miss_latency_hist::mean         54.891329                      
+system.ruby.miss_latency_hist::gmean        49.648144                      
+system.ruby.miss_latency_hist::stdev        31.153546                      
+system.ruby.miss_latency_hist            |        1477     85.38%     85.38% |         199     11.50%     96.88% |          43      2.49%     99.36% |           2      0.12%     99.48% |           5      0.29%     99.77% |           4      0.23%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total             1730                      
+system.ruby.Directory.incomplete_times           1729                      
+system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses         1730                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8448                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     6.992328                      
+system.ruby.network.routers0.msg_count.Control::2         1730                      
+system.ruby.network.routers0.msg_count.Data::2         1726                      
+system.ruby.network.routers0.msg_count.Response_Data::4         1730                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3         1726                      
+system.ruby.network.routers0.msg_bytes.Control::2        13840                      
+system.ruby.network.routers0.msg_bytes.Data::2       124272                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4       124560                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3        13808                      
+system.ruby.network.routers1.percent_links_utilized     6.992328                      
+system.ruby.network.routers1.msg_count.Control::2         1730                      
+system.ruby.network.routers1.msg_count.Data::2         1726                      
+system.ruby.network.routers1.msg_count.Response_Data::4         1730                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3         1726                      
+system.ruby.network.routers1.msg_bytes.Control::2        13840                      
+system.ruby.network.routers1.msg_bytes.Data::2       124272                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4       124560                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3        13808                      
+system.ruby.network.routers2.percent_links_utilized     6.992328                      
+system.ruby.network.routers2.msg_count.Control::2         1730                      
+system.ruby.network.routers2.msg_count.Data::2         1726                      
+system.ruby.network.routers2.msg_count.Response_Data::4         1730                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3         1726                      
+system.ruby.network.routers2.msg_bytes.Control::2        13840                      
+system.ruby.network.routers2.msg_bytes.Data::2       124272                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4       124560                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3        13808                      
+system.ruby.network.msg_count.Control            5190                      
+system.ruby.network.msg_count.Data               5178                      
+system.ruby.network.msg_count.Response_Data         5190                      
+system.ruby.network.msg_count.Writeback_Control         5178                      
+system.ruby.network.msg_byte.Control            41520                      
+system.ruby.network.msg_byte.Data              372816                      
+system.ruby.network.msg_byte.Response_Data       373680                      
+system.ruby.network.msg_byte.Writeback_Control        41424                      
 system.ruby.network.routers0.throttle0.link_utilization     6.998802                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4         1730                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3         1726                      
@@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    52.414605
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    32.138819                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |         614     84.11%     84.11% |          92     12.60%     96.71% |          19      2.60%     99.32% |           0      0.00%     99.32% |           3      0.41%     99.73% |           2      0.27%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          730                      
+system.ruby.Directory_Controller.GETX            1730      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX            1726      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data         1730      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack         1726      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX          1730      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX          1726      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data         1730      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack         1726      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load              1183      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            6400      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              865      0.00%      0.00%
@@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement         1726      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Writeback_Ack         1726      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Data           1457      0.00%      0.00%
 system.ruby.L1Cache_Controller.IM.Data            273      0.00%      0.00%
-system.ruby.Directory_Controller.GETX            1730      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX            1726      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data         1730      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack         1726      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX          1730      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX          1726      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data         1730      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack         1726      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18733500                       # Number of ticks simulated
 final_tick                                   18733500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41421                       # Simulator instruction rate (inst/s)
-host_op_rate                                    41407                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              299977624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235900                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  81438                       # Simulator instruction rate (inst/s)
+host_op_rate                                    81405                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              589715743                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292180                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895            4      9.30%     88.37% # By
 system.physmem.bytesPerActivate::896-1023            2      4.65%     93.02% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            3      6.98%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total             43                       # Bytes accessed per row activation
-system.physmem.totQLat                        1958750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7733750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        1952250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7727250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6359.58                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6338.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25109.58                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  25088.47                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1052.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1052.23                       # Average system read bandwidth in MiByte/s
@@ -218,29 +218,34 @@ system.physmem.readRowHitRate                   83.44                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        60556.82                       # Average gap between requests
 system.physmem.pageHitRate                      83.44                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            15500                       # Time in different power states
-system.physmem.memoryStateTime::REF            520000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15310750                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                     83160                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    219240                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                     45375                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    119625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                   795600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  1294800                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              10790100                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              10507095                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 34500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                282750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                12765855                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                13440630                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             806.306964                       # Core power per rank (mW)
-system.physmem.averagePower::1             848.926575                       # Core power per rank (mW)
+system.physmem_0.actEnergy                      83160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      45375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    795600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               10790100                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  34500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12765855                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              806.306964                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         894750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15310750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     219240                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     119625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   1294800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               10507095                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 282750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 13440630                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              848.926575                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         429000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14897250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                     793                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               397                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               168                       # Number of conditional branches incorrect
@@ -296,14 +301,14 @@ system.cpu.ipc                               0.068994                       # IP
 system.cpu.tickCycles                            5412                       # Number of cycles that the object actually ticked
 system.cpu.idleCycles                           32055                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            48.468521                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            48.478730                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 692                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst    48.468521                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.011833                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011833                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.inst    48.478730                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst     0.011836                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011836                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
@@ -326,14 +331,14 @@ system.cpu.dcache.demand_misses::cpu.inst          104                       # n
 system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
 system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4636500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4636500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3517500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3517500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst      8154000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      8154000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst      8154000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      8154000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4644500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4644500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3502000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3502000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst      8146500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      8146500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst      8146500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      8146500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.inst          502                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          502                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
@@ -350,14 +355,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst     0.130653
 system.cpu.dcache.demand_miss_rate::total     0.130653                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.inst     0.130653                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.130653                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 78403.846154                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 78403.846154                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 78331.730769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 78331.730769                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4302500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4302500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2086500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2086500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6389000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6389000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6389000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6389000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4310500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4310500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2079250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2079250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6389750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6389750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6389750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6389750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.115538                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115538                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
@@ -398,24 +403,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.106784
 system.cpu.dcache.demand_mshr_miss_rate::total     0.106784                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.106784                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.106784                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           118.426247                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           118.465909                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 751                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               223                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.367713                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   118.426247                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.057825                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.057825                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   118.465909                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.057845                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.057845                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          223                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
@@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst          223                       # n
 system.cpu.icache.demand_misses::total            223                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          223                       # number of overall misses
 system.cpu.icache.overall_misses::total           223                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15431500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15431500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15431500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15431500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15431500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15431500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15423500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15423500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15423500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15423500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15423500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15423500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          974                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          974                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          974                       # number of demand (read+write) accesses
@@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.228953
 system.cpu.icache.demand_miss_rate::total     0.228953                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.228953                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.228953                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69199.551570                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69199.551570                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69163.677130                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69163.677130                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -472,34 +477,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          223
 system.cpu.icache.demand_mshr_misses::total          223                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          223                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14892500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     14892500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14892500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     14892500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14892500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     14892500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14884500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14884500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14884500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14884500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14884500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14884500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.228953                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.228953                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.228953                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.228953                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          146.486275                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          146.534478                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.486275                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004470                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.534478                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004472                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004472                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          139                       # Occupied blocks per task id
@@ -516,12 +521,12 @@ system.cpu.l2cache.overall_misses::cpu.inst          308                       #
 system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18913000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     18913000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2059500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2059500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20972500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     20972500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20972500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     20972500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2052250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2052250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20965250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     20965250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20965250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     20965250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          281                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          281                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.inst           27                       # number of ReadExReq accesses(hits+misses)
@@ -540,12 +545,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst            1
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -564,12 +569,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst          308
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15398500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15398500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1725500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1725500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17124000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17124000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1718250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1718250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17116750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17116750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17116750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17116750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
@@ -580,12 +585,12 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           281                       # Transaction distribution
@@ -613,7 +618,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy         154000                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        381000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        137000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        136750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.membus.trans_dist::ReadReq                 281                       # Transaction distribution
 system.membus.trans_dist::ReadResp                281                       # Transaction distribution
@@ -636,7 +641,7 @@ system.membus.snoop_fanout::max_value               0                       # Re
 system.membus.snoop_fanout::total                 308                       # Request fanout histogram
 system.membus.reqLayer0.occupancy              363000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2868500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2868750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             15.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    11765500                       # Number of ticks simulated
 final_tick                                   11765500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35174                       # Simulator instruction rate (inst/s)
-host_op_rate                                    35164                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              173275234                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235920                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  73154                       # Simulator instruction rate (inst/s)
+host_op_rate                                    73124                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              360297045                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293708                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -222,53 +222,34 @@ system.physmem.readRowHitRate                   81.99                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        42926.47                       # Average gap between requests
 system.physmem.pageHitRate                      81.99                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            22000                       # Time in different power states
-system.physmem.memoryStateTime::REF            260000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT           7778000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                     68040                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    158760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                     37125                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                     86625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                   631800                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                   850200                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0                508560                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1                508560                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0               5478840                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1               5222340                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 21750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                246750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                 6746115                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                 7073235                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             838.417275                       # Core power per rank (mW)
-system.physmem.averagePower::1             879.072239                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 248                       # Transaction distribution
-system.membus.trans_dist::ReadResp                248                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          544                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    544                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   17408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               272                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     272    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 272                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              339500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2545000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                      68040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      37125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    631800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                5478840                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  21750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                  6746115                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              838.417275                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE         206000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          260000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT         7778000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     158760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      86625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    850200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                 508560                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy                5222340                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 246750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                  7073235                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              879.072239                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         397500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          260000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT         7402500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    1090                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               548                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               231                       # Number of conditional branches incorrect
@@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             27.520436                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     199                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  9                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -603,34 +585,118 @@ system.cpu.int_regfile_writes                    2774                       # nu
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq            248                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          374                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               544                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11968                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              17408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          272                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                272    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            272                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        314250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        133250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            46.118209                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 729                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.576471                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    46.118209                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011259                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011259                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              1939                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1939                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          516                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             516                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data           729                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              729                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          729                       # number of overall hits
+system.cpu.dcache.overall_hits::total             729                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          117                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           117                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          198                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            198                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          198                       # number of overall misses
+system.cpu.dcache.overall_misses::total           198                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7447000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7447000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5312000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5312000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12759000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12759000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12759000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12759000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          633                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          633                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data          927                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          927                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          927                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          927                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184834                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.184834                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.213592                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.213592                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.213592                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.213592                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64439.393939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64439.393939                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          131                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           24                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4512500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4512500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1719750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1719750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6232250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6232250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6232250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6232250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096367                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096367                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091694                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091694                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse            92.065177                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 685                       # Total number of references to valid blocks.
@@ -846,117 +912,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            46.118209                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 729                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.576471                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    46.118209                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011259                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011259                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1939                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1939                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          516                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             516                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           729                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              729                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          729                       # number of overall hits
-system.cpu.dcache.overall_hits::total             729                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          117                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           117                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          198                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            198                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          198                       # number of overall misses
-system.cpu.dcache.overall_misses::total           198                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7447000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7447000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5312000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5312000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     12759000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     12759000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     12759000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     12759000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          633                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          633                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          927                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          927                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          927                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          927                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.184834                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.184834                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.213592                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.213592                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.213592                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.213592                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64439.393939                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64439.393939                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          131                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    65.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           24                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4512500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4512500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1719750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1719750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6232250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6232250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6232250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6232250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.096367                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.096367                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091694                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091694                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091694                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            248                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           248                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           24                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          374                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          170                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               544                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        11968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              17408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          272                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                272    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            272                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         136000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        314250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        133250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 248                       # Transaction distribution
+system.membus.trans_dist::ReadResp                248                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               24                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    544                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   17408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               272                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     272    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 272                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              339500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            2545000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000052                       # Nu
 sim_ticks                                       52301                       # Number of ticks simulated
 final_tick                                      52301                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  11256                       # Simulator instruction rate (inst/s)
-host_op_rate                                    11255                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 228406                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 435628                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  42059                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42050                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 853239                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 450140                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -232,157 +232,35 @@ system.mem_ctrls.readRowHitRate                 79.91                       # Ro
 system.mem_ctrls.writeRowHitRate                30.43                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         80.33                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    75.21                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             20                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            1560                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           45410                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  173880                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  393120                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                   96600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  218400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                1971840                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                2907840                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                     0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            31347036                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            31310100                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0              688200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1              720600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              37328916                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              38767308                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           794.638028                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           825.257749                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   3612                       # delay histogram for all message
-system.ruby.delayHist::mean                  0.144518                       # delay histogram for all message
-system.ruby.delayHist::stdev                 0.930805                       # delay histogram for all message
-system.ruby.delayHist                    |        3486     96.51%     96.51% |           0      0.00%     96.51% |          81      2.24%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |          45      1.25%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     3612                       # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         3295                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          3295                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              14.877656                      
-system.ruby.latency_hist::gmean              5.143561                      
-system.ruby.latency_hist::stdev             28.438893                      
-system.ruby.latency_hist                 |        2856     86.70%     86.70% |         431     13.08%     99.79% |           1      0.03%     99.82% |           2      0.06%     99.88% |           3      0.09%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  3294                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            2722                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2722    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2722                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples            572                      
-system.ruby.miss_latency_hist::mean         71.400350                      
-system.ruby.miss_latency_hist::gmean        66.909551                      
-system.ruby.miss_latency_hist::stdev        28.130025                      
-system.ruby.miss_latency_hist            |         134     23.43%     23.43% |         431     75.35%     98.78% |           1      0.17%     98.95% |           2      0.35%     99.30% |           3      0.52%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              572                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits          437                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          272                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         2285                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          300                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   173880                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    96600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1971840                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             31347036                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               688200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               37328916                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            794.638028                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE         1179                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         44437                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   393120                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   218400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2907840                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             31309416                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               721200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               38767224                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            825.255960                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1048                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         44382                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers0.percent_links_utilized     3.803943                      
-system.ruby.network.routers0.msg_count.Control::0          572                      
-system.ruby.network.routers0.msg_count.Request_Control::2          431                      
-system.ruby.network.routers0.msg_count.Response_Data::1          572                      
-system.ruby.network.routers0.msg_count.Response_Control::1          493                      
-system.ruby.network.routers0.msg_count.Response_Control::2          272                      
-system.ruby.network.routers0.msg_count.Writeback_Data::0           45                      
-system.ruby.network.routers0.msg_count.Writeback_Data::1           62                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0           79                      
-system.ruby.network.routers0.msg_bytes.Control::0         4576                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         3448                      
-system.ruby.network.routers0.msg_bytes.Response_Data::1        41184                      
-system.ruby.network.routers0.msg_bytes.Response_Control::1         3944                      
-system.ruby.network.routers0.msg_bytes.Response_Control::2         2176                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0         3240                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1         4464                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0          632                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           25                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          547                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          572                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     7.327776                      
-system.ruby.network.routers1.msg_count.Control::0         1119                      
-system.ruby.network.routers1.msg_count.Request_Control::2          431                      
-system.ruby.network.routers1.msg_count.Response_Data::1         1222                      
-system.ruby.network.routers1.msg_count.Response_Control::1         1468                      
-system.ruby.network.routers1.msg_count.Response_Control::2          272                      
-system.ruby.network.routers1.msg_count.Writeback_Data::0           45                      
-system.ruby.network.routers1.msg_count.Writeback_Data::1           62                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0           79                      
-system.ruby.network.routers1.msg_bytes.Control::0         8952                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         3448                      
-system.ruby.network.routers1.msg_bytes.Response_Data::1        87984                      
-system.ruby.network.routers1.msg_bytes.Response_Control::1        11744                      
-system.ruby.network.routers1.msg_bytes.Response_Control::2         2176                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0         3240                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1         4464                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.routers2.percent_links_utilized     3.523833                      
-system.ruby.network.routers2.msg_count.Control::0          547                      
-system.ruby.network.routers2.msg_count.Response_Data::1          650                      
-system.ruby.network.routers2.msg_count.Response_Control::1          975                      
-system.ruby.network.routers2.msg_bytes.Control::0         4376                      
-system.ruby.network.routers2.msg_bytes.Response_Data::1        46800                      
-system.ruby.network.routers2.msg_bytes.Response_Control::1         7800                      
-system.ruby.network.routers3.percent_links_utilized     4.885184                      
-system.ruby.network.routers3.msg_count.Control::0         1119                      
-system.ruby.network.routers3.msg_count.Request_Control::2          431                      
-system.ruby.network.routers3.msg_count.Response_Data::1         1222                      
-system.ruby.network.routers3.msg_count.Response_Control::1         1468                      
-system.ruby.network.routers3.msg_count.Response_Control::2          272                      
-system.ruby.network.routers3.msg_count.Writeback_Data::0           45                      
-system.ruby.network.routers3.msg_count.Writeback_Data::1           62                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0           79                      
-system.ruby.network.routers3.msg_bytes.Control::0         8952                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         3448                      
-system.ruby.network.routers3.msg_bytes.Response_Data::1        87984                      
-system.ruby.network.routers3.msg_bytes.Response_Control::1        11744                      
-system.ruby.network.routers3.msg_bytes.Response_Control::2         2176                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0         3240                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1         4464                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0          632                      
-system.ruby.network.msg_count.Control            3357                      
-system.ruby.network.msg_count.Request_Control         1293                      
-system.ruby.network.msg_count.Response_Data         3666                      
-system.ruby.network.msg_count.Response_Control         5220                      
-system.ruby.network.msg_count.Writeback_Data          321                      
-system.ruby.network.msg_count.Writeback_Control          237                      
-system.ruby.network.msg_byte.Control            26856                      
-system.ruby.network.msg_byte.Request_Control        10344                      
-system.ruby.network.msg_byte.Response_Data       263952                      
-system.ruby.network.msg_byte.Response_Control        41760                      
-system.ruby.network.msg_byte.Writeback_Data        23112                      
-system.ruby.network.msg_byte.Writeback_Control         1896                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -474,6 +352,133 @@ system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
+system.ruby.delayHist::samples                   3612                       # delay histogram for all message
+system.ruby.delayHist::mean                  0.144518                       # delay histogram for all message
+system.ruby.delayHist::stdev                 0.930805                       # delay histogram for all message
+system.ruby.delayHist                    |        3486     96.51%     96.51% |           0      0.00%     96.51% |          81      2.24%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |           0      0.00%     98.75% |          45      1.25%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     3612                       # delay histogram for all message
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         3295                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          3295                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                3294                      
+system.ruby.latency_hist::mean              14.877656                      
+system.ruby.latency_hist::gmean              5.143561                      
+system.ruby.latency_hist::stdev             28.438893                      
+system.ruby.latency_hist                 |        2856     86.70%     86.70% |         431     13.08%     99.79% |           1      0.03%     99.82% |           2      0.06%     99.88% |           3      0.09%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  3294                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            2722                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2722    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2722                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples            572                      
+system.ruby.miss_latency_hist::mean         71.400350                      
+system.ruby.miss_latency_hist::gmean        66.909551                      
+system.ruby.miss_latency_hist::stdev        28.130025                      
+system.ruby.miss_latency_hist            |         134     23.43%     23.43% |         431     75.35%     98.78% |           1      0.17%     98.95% |           2      0.35%     99.30% |           3      0.52%     99.83% |           1      0.17%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              572                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits          437                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          272                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         2285                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          300                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted            0                       # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches            0                       # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits               0                       # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits            0                       # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed            0                       # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks            0                       # number of misses for blocks that were prefetched, yet missed
+system.ruby.l2_cntrl0.L2cache.demand_hits           25                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          547                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          572                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     3.803943                      
+system.ruby.network.routers0.msg_count.Control::0          572                      
+system.ruby.network.routers0.msg_count.Request_Control::2          431                      
+system.ruby.network.routers0.msg_count.Response_Data::1          572                      
+system.ruby.network.routers0.msg_count.Response_Control::1          493                      
+system.ruby.network.routers0.msg_count.Response_Control::2          272                      
+system.ruby.network.routers0.msg_count.Writeback_Data::0           45                      
+system.ruby.network.routers0.msg_count.Writeback_Data::1           62                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0           79                      
+system.ruby.network.routers0.msg_bytes.Control::0         4576                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         3448                      
+system.ruby.network.routers0.msg_bytes.Response_Data::1        41184                      
+system.ruby.network.routers0.msg_bytes.Response_Control::1         3944                      
+system.ruby.network.routers0.msg_bytes.Response_Control::2         2176                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0         3240                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1         4464                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0          632                      
+system.ruby.network.routers1.percent_links_utilized     7.327776                      
+system.ruby.network.routers1.msg_count.Control::0         1119                      
+system.ruby.network.routers1.msg_count.Request_Control::2          431                      
+system.ruby.network.routers1.msg_count.Response_Data::1         1222                      
+system.ruby.network.routers1.msg_count.Response_Control::1         1468                      
+system.ruby.network.routers1.msg_count.Response_Control::2          272                      
+system.ruby.network.routers1.msg_count.Writeback_Data::0           45                      
+system.ruby.network.routers1.msg_count.Writeback_Data::1           62                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0           79                      
+system.ruby.network.routers1.msg_bytes.Control::0         8952                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         3448                      
+system.ruby.network.routers1.msg_bytes.Response_Data::1        87984                      
+system.ruby.network.routers1.msg_bytes.Response_Control::1        11744                      
+system.ruby.network.routers1.msg_bytes.Response_Control::2         2176                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0         3240                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1         4464                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0          632                      
+system.ruby.network.routers2.percent_links_utilized     3.523833                      
+system.ruby.network.routers2.msg_count.Control::0          547                      
+system.ruby.network.routers2.msg_count.Response_Data::1          650                      
+system.ruby.network.routers2.msg_count.Response_Control::1          975                      
+system.ruby.network.routers2.msg_bytes.Control::0         4376                      
+system.ruby.network.routers2.msg_bytes.Response_Data::1        46800                      
+system.ruby.network.routers2.msg_bytes.Response_Control::1         7800                      
+system.ruby.network.routers3.percent_links_utilized     4.885184                      
+system.ruby.network.routers3.msg_count.Control::0         1119                      
+system.ruby.network.routers3.msg_count.Request_Control::2          431                      
+system.ruby.network.routers3.msg_count.Response_Data::1         1222                      
+system.ruby.network.routers3.msg_count.Response_Control::1         1468                      
+system.ruby.network.routers3.msg_count.Response_Control::2          272                      
+system.ruby.network.routers3.msg_count.Writeback_Data::0           45                      
+system.ruby.network.routers3.msg_count.Writeback_Data::1           62                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0           79                      
+system.ruby.network.routers3.msg_bytes.Control::0         8952                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         3448                      
+system.ruby.network.routers3.msg_bytes.Response_Data::1        87984                      
+system.ruby.network.routers3.msg_bytes.Response_Control::1        11744                      
+system.ruby.network.routers3.msg_bytes.Response_Control::2         2176                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0         3240                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1         4464                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0          632                      
+system.ruby.network.msg_count.Control            3357                      
+system.ruby.network.msg_count.Request_Control         1293                      
+system.ruby.network.msg_count.Response_Data         3666                      
+system.ruby.network.msg_count.Response_Control         5220                      
+system.ruby.network.msg_count.Writeback_Data          321                      
+system.ruby.network.msg_count.Writeback_Control          237                      
+system.ruby.network.msg_byte.Control            26856                      
+system.ruby.network.msg_byte.Request_Control        10344                      
+system.ruby.network.msg_byte.Response_Data       263952                      
+system.ruby.network.msg_byte.Response_Control        41760                      
+system.ruby.network.msg_byte.Writeback_Data        23112                      
+system.ruby.network.msg_byte.Writeback_Control         1896                      
 system.ruby.network.routers0.throttle0.link_utilization     5.452095                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2          431                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          572                      
@@ -647,6 +652,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean    75.006009
 system.ruby.IFETCH.miss_latency_hist::stdev    25.337433                      
 system.ruby.IFETCH.miss_latency_hist     |           9      3.00%      3.00% |           0      0.00%      3.00% |         276     92.00%     95.00% |          10      3.33%     98.33% |           1      0.33%     98.67% |           0      0.00%     98.67% |           1      0.33%     99.00% |           1      0.33%     99.33% |           1      0.33%     99.67% |           1      0.33%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          300                      
+system.ruby.Directory_Controller.Fetch            547      0.00%      0.00%
+system.ruby.Directory_Controller.Data             103      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          547      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          103      0.00%      0.00%
+system.ruby.Directory_Controller.CleanReplacement          436      0.00%      0.00%
+system.ruby.Directory_Controller.I.Fetch          547      0.00%      0.00%
+system.ruby.Directory_Controller.M.Data           103      0.00%      0.00%
+system.ruby.Directory_Controller.M.CleanReplacement          436      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          547      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          103      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               415      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2585      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              294      0.00%      0.00%
@@ -711,15 +726,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data          192      0.00%      0.00%
 system.ruby.L2Cache_Controller.IS.Mem_Data          291      0.00%      0.00%
 system.ruby.L2Cache_Controller.IM.Mem_Data           64      0.00%      0.00%
 system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock          272      0.00%      0.00%
-system.ruby.Directory_Controller.Fetch            547      0.00%      0.00%
-system.ruby.Directory_Controller.Data             103      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          547      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          103      0.00%      0.00%
-system.ruby.Directory_Controller.CleanReplacement          436      0.00%      0.00%
-system.ruby.Directory_Controller.I.Fetch          547      0.00%      0.00%
-system.ruby.Directory_Controller.M.Data           103      0.00%      0.00%
-system.ruby.Directory_Controller.M.CleanReplacement          436      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          547      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          103      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000048                       # Nu
 sim_ticks                                       48283                       # Number of ticks simulated
 final_tick                                      48283                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12943                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12941                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 242448                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 437744                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  45603                       # Simulator instruction rate (inst/s)
+host_op_rate                                    45593                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 854052                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 451760                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -232,141 +232,35 @@ system.mem_ctrls.readRowHitRate                 77.66                       # Ro
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         88.76                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    72.85                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             76                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            1560                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           45412                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  173880                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  446040                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                   96600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  247800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                1884480                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                2808000                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                     0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            31539240                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            30693132                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0              520800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1             1263000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              37266360                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              38675220                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           793.272596                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           823.262378                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         3295                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          3295                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              13.657863                      
-system.ruby.latency_hist::gmean              4.922626                      
-system.ruby.latency_hist::stdev             27.058784                      
-system.ruby.latency_hist                 |        2909     88.31%     88.31% |         378     11.48%     99.79% |           3      0.09%     99.88% |           0      0.00%     99.88% |           3      0.09%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  3294                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            2750                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2750    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2750                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples            544                      
-system.ruby.miss_latency_hist::mean         67.534926                      
-system.ruby.miss_latency_hist::gmean        60.177697                      
-system.ruby.miss_latency_hist::stdev        30.933879                      
-system.ruby.miss_latency_hist            |         159     29.23%     29.23% |         378     69.49%     98.71% |           3      0.55%     99.26% |           0      0.00%     99.26% |           3      0.55%     99.82% |           1      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              544                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits          435                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          274                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   173880                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    96600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1884480                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             31537872                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               520800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               37264992                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            793.277248                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE          968                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         44716                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   446040                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   247800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2808000                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             30693132                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy              1263000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               38675220                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            823.262378                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         2007                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         43481                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.874739                      
-system.ruby.network.routers0.msg_count.Request_Control::0          544                      
-system.ruby.network.routers0.msg_count.Response_Data::2          465                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           79                      
-system.ruby.network.routers0.msg_count.Writeback_Data::2          482                      
-system.ruby.network.routers0.msg_count.Writeback_Control::0         1004                      
-system.ruby.network.routers0.msg_count.Unblock_Control::2          564                      
-system.ruby.network.routers0.msg_bytes.Request_Control::0         4352                      
-system.ruby.network.routers0.msg_bytes.Response_Data::2        33480                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         5688                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2        34704                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0         8032                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2         4512                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           79                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          465                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          544                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     8.967442                      
-system.ruby.network.routers1.msg_count.Request_Control::0          544                      
-system.ruby.network.routers1.msg_count.Request_Control::1          465                      
-system.ruby.network.routers1.msg_count.Response_Data::2          930                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           79                      
-system.ruby.network.routers1.msg_count.Writeback_Data::2          560                      
-system.ruby.network.routers1.msg_count.Writeback_Control::0         1004                      
-system.ruby.network.routers1.msg_count.Writeback_Control::1          156                      
-system.ruby.network.routers1.msg_count.Unblock_Control::2         1029                      
-system.ruby.network.routers1.msg_bytes.Request_Control::0         4352                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         3720                      
-system.ruby.network.routers1.msg_bytes.Response_Data::2        66960                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         5688                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2        40320                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0         8032                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::1         1248                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2         8232                      
-system.ruby.network.routers2.percent_links_utilized     3.092186                      
-system.ruby.network.routers2.msg_count.Request_Control::1          465                      
-system.ruby.network.routers2.msg_count.Response_Data::2          465                      
-system.ruby.network.routers2.msg_count.Writeback_Data::2           78                      
-system.ruby.network.routers2.msg_count.Writeback_Control::1          156                      
-system.ruby.network.routers2.msg_count.Unblock_Control::2          464                      
-system.ruby.network.routers2.msg_bytes.Request_Control::1         3720                      
-system.ruby.network.routers2.msg_bytes.Response_Data::2        33480                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::2         5616                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::1         1248                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2         3712                      
-system.ruby.network.routers3.percent_links_utilized     5.978295                      
-system.ruby.network.routers3.msg_count.Request_Control::0          544                      
-system.ruby.network.routers3.msg_count.Request_Control::1          465                      
-system.ruby.network.routers3.msg_count.Response_Data::2          930                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           79                      
-system.ruby.network.routers3.msg_count.Writeback_Data::2          560                      
-system.ruby.network.routers3.msg_count.Writeback_Control::0         1004                      
-system.ruby.network.routers3.msg_count.Writeback_Control::1          156                      
-system.ruby.network.routers3.msg_count.Unblock_Control::2         1029                      
-system.ruby.network.routers3.msg_bytes.Request_Control::0         4352                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         3720                      
-system.ruby.network.routers3.msg_bytes.Response_Data::2        66960                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         5688                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2        40320                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0         8032                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1         1248                      
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2         8232                      
-system.ruby.network.msg_count.Request_Control         3027                      
-system.ruby.network.msg_count.Response_Data         2790                      
-system.ruby.network.msg_count.ResponseL2hit_Data          237                      
-system.ruby.network.msg_count.Writeback_Data         1680                      
-system.ruby.network.msg_count.Writeback_Control         3480                      
-system.ruby.network.msg_count.Unblock_Control         3086                      
-system.ruby.network.msg_byte.Request_Control        24216                      
-system.ruby.network.msg_byte.Response_Data       200880                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        17064                      
-system.ruby.network.msg_byte.Writeback_Data       120960                      
-system.ruby.network.msg_byte.Writeback_Control        27840                      
-system.ruby.network.msg_byte.Unblock_Control        24688                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -458,6 +352,117 @@ system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         3295                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          3295                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                3294                      
+system.ruby.latency_hist::mean              13.657863                      
+system.ruby.latency_hist::gmean              4.922626                      
+system.ruby.latency_hist::stdev             27.058784                      
+system.ruby.latency_hist                 |        2909     88.31%     88.31% |         378     11.48%     99.79% |           3      0.09%     99.88% |           0      0.00%     99.88% |           3      0.09%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  3294                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            2750                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2750    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2750                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples            544                      
+system.ruby.miss_latency_hist::mean         67.534926                      
+system.ruby.miss_latency_hist::gmean        60.177697                      
+system.ruby.miss_latency_hist::stdev        30.933879                      
+system.ruby.miss_latency_hist            |         159     29.23%     29.23% |         378     69.49%     98.71% |           3      0.55%     99.26% |           0      0.00%     99.26% |           3      0.55%     99.82% |           1      0.18%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              544                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits          435                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          274                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits           79                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          465                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          544                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     5.874739                      
+system.ruby.network.routers0.msg_count.Request_Control::0          544                      
+system.ruby.network.routers0.msg_count.Response_Data::2          465                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2           79                      
+system.ruby.network.routers0.msg_count.Writeback_Data::2          482                      
+system.ruby.network.routers0.msg_count.Writeback_Control::0         1004                      
+system.ruby.network.routers0.msg_count.Unblock_Control::2          564                      
+system.ruby.network.routers0.msg_bytes.Request_Control::0         4352                      
+system.ruby.network.routers0.msg_bytes.Response_Data::2        33480                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2         5688                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2        34704                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0         8032                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2         4512                      
+system.ruby.network.routers1.percent_links_utilized     8.967442                      
+system.ruby.network.routers1.msg_count.Request_Control::0          544                      
+system.ruby.network.routers1.msg_count.Request_Control::1          465                      
+system.ruby.network.routers1.msg_count.Response_Data::2          930                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2           79                      
+system.ruby.network.routers1.msg_count.Writeback_Data::2          560                      
+system.ruby.network.routers1.msg_count.Writeback_Control::0         1004                      
+system.ruby.network.routers1.msg_count.Writeback_Control::1          156                      
+system.ruby.network.routers1.msg_count.Unblock_Control::2         1029                      
+system.ruby.network.routers1.msg_bytes.Request_Control::0         4352                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         3720                      
+system.ruby.network.routers1.msg_bytes.Response_Data::2        66960                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2         5688                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2        40320                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0         8032                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::1         1248                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2         8232                      
+system.ruby.network.routers2.percent_links_utilized     3.092186                      
+system.ruby.network.routers2.msg_count.Request_Control::1          465                      
+system.ruby.network.routers2.msg_count.Response_Data::2          465                      
+system.ruby.network.routers2.msg_count.Writeback_Data::2           78                      
+system.ruby.network.routers2.msg_count.Writeback_Control::1          156                      
+system.ruby.network.routers2.msg_count.Unblock_Control::2          464                      
+system.ruby.network.routers2.msg_bytes.Request_Control::1         3720                      
+system.ruby.network.routers2.msg_bytes.Response_Data::2        33480                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::2         5616                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::1         1248                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2         3712                      
+system.ruby.network.routers3.percent_links_utilized     5.978295                      
+system.ruby.network.routers3.msg_count.Request_Control::0          544                      
+system.ruby.network.routers3.msg_count.Request_Control::1          465                      
+system.ruby.network.routers3.msg_count.Response_Data::2          930                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2           79                      
+system.ruby.network.routers3.msg_count.Writeback_Data::2          560                      
+system.ruby.network.routers3.msg_count.Writeback_Control::0         1004                      
+system.ruby.network.routers3.msg_count.Writeback_Control::1          156                      
+system.ruby.network.routers3.msg_count.Unblock_Control::2         1029                      
+system.ruby.network.routers3.msg_bytes.Request_Control::0         4352                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         3720                      
+system.ruby.network.routers3.msg_bytes.Response_Data::2        66960                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2         5688                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2        40320                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0         8032                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1         1248                      
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2         8232                      
+system.ruby.network.msg_count.Request_Control         3027                      
+system.ruby.network.msg_count.Response_Data         2790                      
+system.ruby.network.msg_count.ResponseL2hit_Data          237                      
+system.ruby.network.msg_count.Writeback_Data         1680                      
+system.ruby.network.msg_count.Writeback_Control         3480                      
+system.ruby.network.msg_count.Unblock_Control         3086                      
+system.ruby.network.msg_byte.Request_Control        24216                      
+system.ruby.network.msg_byte.Response_Data       200880                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        17064                      
+system.ruby.network.msg_byte.Writeback_Data       120960                      
+system.ruby.network.msg_byte.Writeback_Control        27840                      
+system.ruby.network.msg_byte.Unblock_Control        24688                      
 system.ruby.network.routers0.throttle0.link_utilization     5.589959                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          465                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           79                      
@@ -614,6 +619,29 @@ system.ruby.IFETCH.miss_latency_hist::gmean    69.413198
 system.ruby.IFETCH.miss_latency_hist::stdev    30.681798                      
 system.ruby.IFETCH.miss_latency_hist     |          26      9.63%      9.63% |         239     88.52%     98.15% |           2      0.74%     98.89% |           0      0.00%     98.89% |           2      0.74%     99.63% |           1      0.37%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.miss_latency_hist::total          270                      
+system.ruby.Directory_Controller.GETX              80      0.00%      0.00%
+system.ruby.Directory_Controller.GETS             385      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX              78      0.00%      0.00%
+system.ruby.Directory_Controller.Unblock          262      0.00%      0.00%
+system.ruby.Directory_Controller.Last_Unblock          122      0.00%      0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock           80      0.00%      0.00%
+system.ruby.Directory_Controller.Dirty_Writeback           78      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          465      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack           78      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX            40      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETS           262      0.00%      0.00%
+system.ruby.Directory_Controller.I.Memory_Ack           77      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETX            40      0.00%      0.00%
+system.ruby.Directory_Controller.S.GETS           123      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX            78      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Unblock          262      0.00%      0.00%
+system.ruby.Directory_Controller.IS.Memory_Data          262      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock          122      0.00%      0.00%
+system.ruby.Directory_Controller.SS.Memory_Data          123      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock           80      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Data           80      0.00%      0.00%
+system.ruby.Directory_Controller.MM.Memory_Ack            1      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback           78      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               415      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2585      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              294      0.00%      0.00%
@@ -691,28 +719,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock           12      0.00%
 system.ruby.L2Cache_Controller.SS.Unblock           51      0.00%      0.00%
 system.ruby.L2Cache_Controller.OO.Exclusive_Unblock           16      0.00%      0.00%
 system.ruby.L2Cache_Controller.MI.Writeback_Ack           78      0.00%      0.00%
-system.ruby.Directory_Controller.GETX              80      0.00%      0.00%
-system.ruby.Directory_Controller.GETS             385      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX              78      0.00%      0.00%
-system.ruby.Directory_Controller.Unblock          262      0.00%      0.00%
-system.ruby.Directory_Controller.Last_Unblock          122      0.00%      0.00%
-system.ruby.Directory_Controller.Exclusive_Unblock           80      0.00%      0.00%
-system.ruby.Directory_Controller.Dirty_Writeback           78      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          465      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack           78      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX            40      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETS           262      0.00%      0.00%
-system.ruby.Directory_Controller.I.Memory_Ack           77      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETX            40      0.00%      0.00%
-system.ruby.Directory_Controller.S.GETS           123      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX            78      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Unblock          262      0.00%      0.00%
-system.ruby.Directory_Controller.IS.Memory_Data          262      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock          122      0.00%      0.00%
-system.ruby.Directory_Controller.SS.Memory_Data          123      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Exclusive_Unblock           80      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Data           80      0.00%      0.00%
-system.ruby.Directory_Controller.MM.Memory_Ack            1      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Dirty_Writeback           78      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000044                       # Nu
 sim_ticks                                       43869                       # Number of ticks simulated
 final_tick                                      43869                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                    107                       # Simulator instruction rate (inst/s)
-host_op_rate                                      107                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                   1826                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 435688                       # Number of bytes of host memory used
-host_seconds                                    24.02                       # Real time elapsed on the host
+host_inst_rate                                  63661                       # Simulator instruction rate (inst/s)
+host_op_rate                                    63637                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1082971                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449944                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -232,143 +232,35 @@ system.mem_ctrls.readRowHitRate                 78.40                       # Ro
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         82.31                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    73.40                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             22                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            1300                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           37882                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  158760                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  355320                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                   88200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  197400                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                1697280                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                2483520                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                     0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             2542800                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            25360668                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            26385300                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0             1267800                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1              369000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              31115508                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              32499228                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           793.965501                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           829.273488                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         3295                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          3295                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              12.317851                      
-system.ruby.latency_hist::gmean              3.428807                      
-system.ruby.latency_hist::stdev             27.092783                      
-system.ruby.latency_hist                 |        2919     88.62%     88.62% |         368     11.17%     99.79% |           2      0.06%     99.85% |           1      0.03%     99.88% |           1      0.03%     99.91% |           3      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  3294                      
-system.ruby.hit_latency_hist::bucket_size            4                      
-system.ruby.hit_latency_hist::max_bucket           39                      
-system.ruby.hit_latency_hist::samples            2846                      
-system.ruby.hit_latency_hist::mean           2.554462                      
-system.ruby.hit_latency_hist::gmean          2.127153                      
-system.ruby.hit_latency_hist::stdev          3.497278                      
-system.ruby.hit_latency_hist             |        2776     97.54%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           9      0.32%     97.86% |          61      2.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2846                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples            448                      
-system.ruby.miss_latency_hist::mean         74.341518                      
-system.ruby.miss_latency_hist::gmean        71.176280                      
-system.ruby.miss_latency_hist::stdev        29.447133                      
-system.ruby.miss_latency_hist            |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           1      0.22%     99.11% |           1      0.22%     99.33% |           3      0.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              448                      
-system.ruby.Directory.incomplete_times            447                      
-system.ruby.l1_cntrl0.L1Dcache.demand_hits          461                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          248                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   158760                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    88200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1697280                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             25360668                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              1267800                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               31115508                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            793.965501                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE         1987                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1300                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         35917                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   355320                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   197400                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2483520                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              2542800                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             26385300                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               369000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               32499228                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            829.273488                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE          583                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1300                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         37415                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     5.531811                      
-system.ruby.network.routers0.msg_count.Request_Control::1          518                      
-system.ruby.network.routers0.msg_count.Response_Data::4          448                      
-system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           70                      
-system.ruby.network.routers0.msg_count.Response_Control::4            1                      
-system.ruby.network.routers0.msg_count.Writeback_Data::4          502                      
-system.ruby.network.routers0.msg_count.Persistent_Control::3            8                      
-system.ruby.network.routers0.msg_bytes.Request_Control::1         4144                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        32256                      
-system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         5040                      
-system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4        36144                      
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3           64                      
-system.ruby.l2_cntrl0.L2cache.demand_hits           64                       # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses          454                       # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses          518                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     4.129340                      
-system.ruby.network.routers1.msg_count.Request_Control::1          518                      
-system.ruby.network.routers1.msg_count.Request_Control::2          454                      
-system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           70                      
-system.ruby.network.routers1.msg_count.Response_Control::4            1                      
-system.ruby.network.routers1.msg_count.Writeback_Data::4          586                      
-system.ruby.network.routers1.msg_count.Writeback_Control::4          365                      
-system.ruby.network.routers1.msg_count.Persistent_Control::3            4                      
-system.ruby.network.routers1.msg_bytes.Request_Control::1         4144                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         3632                      
-system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         5040                      
-system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4        42192                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4         2920                      
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3           32                      
-system.ruby.network.routers2.percent_links_utilized     3.197588                      
-system.ruby.network.routers2.msg_count.Request_Control::2          454                      
-system.ruby.network.routers2.msg_count.Response_Data::4          448                      
-system.ruby.network.routers2.msg_count.Writeback_Data::4           84                      
-system.ruby.network.routers2.msg_count.Writeback_Control::4          365                      
-system.ruby.network.routers2.msg_count.Persistent_Control::3            4                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         3632                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        32256                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::4         6048                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4         2920                      
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3           32                      
-system.ruby.network.routers3.percent_links_utilized     4.286246                      
-system.ruby.network.routers3.msg_count.Request_Control::1          518                      
-system.ruby.network.routers3.msg_count.Request_Control::2          454                      
-system.ruby.network.routers3.msg_count.Response_Data::4          448                      
-system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           70                      
-system.ruby.network.routers3.msg_count.Response_Control::4            1                      
-system.ruby.network.routers3.msg_count.Writeback_Data::4          586                      
-system.ruby.network.routers3.msg_count.Writeback_Control::4          365                      
-system.ruby.network.routers3.msg_count.Persistent_Control::3            8                      
-system.ruby.network.routers3.msg_bytes.Request_Control::1         4144                      
-system.ruby.network.routers3.msg_bytes.Request_Control::2         3632                      
-system.ruby.network.routers3.msg_bytes.Response_Data::4        32256                      
-system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         5040                      
-system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4        42192                      
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4         2920                      
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3           64                      
-system.ruby.network.msg_count.Request_Control         2916                      
-system.ruby.network.msg_count.Response_Data         1344                      
-system.ruby.network.msg_count.ResponseL2hit_Data          210                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         1758                      
-system.ruby.network.msg_count.Writeback_Control         1095                      
-system.ruby.network.msg_count.Persistent_Control           24                      
-system.ruby.network.msg_byte.Request_Control        23328                      
-system.ruby.network.msg_byte.Response_Data        96768                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        15120                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       126576                      
-system.ruby.network.msg_byte.Writeback_Control         8760                      
-system.ruby.network.msg_byte.Persistent_Control          192                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -460,6 +352,119 @@ system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         3295                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          3295                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                3294                      
+system.ruby.latency_hist::mean              12.317851                      
+system.ruby.latency_hist::gmean              3.428807                      
+system.ruby.latency_hist::stdev             27.092783                      
+system.ruby.latency_hist                 |        2919     88.62%     88.62% |         368     11.17%     99.79% |           2      0.06%     99.85% |           1      0.03%     99.88% |           1      0.03%     99.91% |           3      0.09%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  3294                      
+system.ruby.hit_latency_hist::bucket_size            4                      
+system.ruby.hit_latency_hist::max_bucket           39                      
+system.ruby.hit_latency_hist::samples            2846                      
+system.ruby.hit_latency_hist::mean           2.554462                      
+system.ruby.hit_latency_hist::gmean          2.127153                      
+system.ruby.hit_latency_hist::stdev          3.497278                      
+system.ruby.hit_latency_hist             |        2776     97.54%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           0      0.00%     97.54% |           9      0.32%     97.86% |          61      2.14%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2846                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples            448                      
+system.ruby.miss_latency_hist::mean         74.341518                      
+system.ruby.miss_latency_hist::gmean        71.176280                      
+system.ruby.miss_latency_hist::stdev        29.447133                      
+system.ruby.miss_latency_hist            |          73     16.29%     16.29% |         368     82.14%     98.44% |           2      0.45%     98.88% |           1      0.22%     99.11% |           1      0.22%     99.33% |           3      0.67%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              448                      
+system.ruby.Directory.incomplete_times            447                      
+system.ruby.l1_cntrl0.L1Dcache.demand_hits          461                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          248                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_hits           64                       # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses          454                       # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses          518                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     5.531811                      
+system.ruby.network.routers0.msg_count.Request_Control::1          518                      
+system.ruby.network.routers0.msg_count.Response_Data::4          448                      
+system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4           70                      
+system.ruby.network.routers0.msg_count.Response_Control::4            1                      
+system.ruby.network.routers0.msg_count.Writeback_Data::4          502                      
+system.ruby.network.routers0.msg_count.Persistent_Control::3            8                      
+system.ruby.network.routers0.msg_bytes.Request_Control::1         4144                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        32256                      
+system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4         5040                      
+system.ruby.network.routers0.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4        36144                      
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3           64                      
+system.ruby.network.routers1.percent_links_utilized     4.129340                      
+system.ruby.network.routers1.msg_count.Request_Control::1          518                      
+system.ruby.network.routers1.msg_count.Request_Control::2          454                      
+system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4           70                      
+system.ruby.network.routers1.msg_count.Response_Control::4            1                      
+system.ruby.network.routers1.msg_count.Writeback_Data::4          586                      
+system.ruby.network.routers1.msg_count.Writeback_Control::4          365                      
+system.ruby.network.routers1.msg_count.Persistent_Control::3            4                      
+system.ruby.network.routers1.msg_bytes.Request_Control::1         4144                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         3632                      
+system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4         5040                      
+system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4        42192                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4         2920                      
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3           32                      
+system.ruby.network.routers2.percent_links_utilized     3.197588                      
+system.ruby.network.routers2.msg_count.Request_Control::2          454                      
+system.ruby.network.routers2.msg_count.Response_Data::4          448                      
+system.ruby.network.routers2.msg_count.Writeback_Data::4           84                      
+system.ruby.network.routers2.msg_count.Writeback_Control::4          365                      
+system.ruby.network.routers2.msg_count.Persistent_Control::3            4                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         3632                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        32256                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::4         6048                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4         2920                      
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3           32                      
+system.ruby.network.routers3.percent_links_utilized     4.286246                      
+system.ruby.network.routers3.msg_count.Request_Control::1          518                      
+system.ruby.network.routers3.msg_count.Request_Control::2          454                      
+system.ruby.network.routers3.msg_count.Response_Data::4          448                      
+system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4           70                      
+system.ruby.network.routers3.msg_count.Response_Control::4            1                      
+system.ruby.network.routers3.msg_count.Writeback_Data::4          586                      
+system.ruby.network.routers3.msg_count.Writeback_Control::4          365                      
+system.ruby.network.routers3.msg_count.Persistent_Control::3            8                      
+system.ruby.network.routers3.msg_bytes.Request_Control::1         4144                      
+system.ruby.network.routers3.msg_bytes.Request_Control::2         3632                      
+system.ruby.network.routers3.msg_bytes.Response_Data::4        32256                      
+system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         5040                      
+system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4        42192                      
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4         2920                      
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3           64                      
+system.ruby.network.msg_count.Request_Control         2916                      
+system.ruby.network.msg_count.Response_Data         1344                      
+system.ruby.network.msg_count.ResponseL2hit_Data          210                      
+system.ruby.network.msg_count.Response_Control            3                      
+system.ruby.network.msg_count.Writeback_Data         1758                      
+system.ruby.network.msg_count.Writeback_Control         1095                      
+system.ruby.network.msg_count.Persistent_Control           24                      
+system.ruby.network.msg_byte.Request_Control        23328                      
+system.ruby.network.msg_byte.Response_Data        96768                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        15120                      
+system.ruby.network.msg_byte.Response_Control           24                      
+system.ruby.network.msg_byte.Writeback_Data       126576                      
+system.ruby.network.msg_byte.Writeback_Control         8760                      
+system.ruby.network.msg_byte.Persistent_Control          192                      
 system.ruby.network.routers0.throttle0.link_utilization     5.319246                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          448                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           70                      
@@ -718,6 +723,32 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    77.741160
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    34.366891                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         242     97.98%     97.98% |           0      0.00%     97.98% |           1      0.40%     98.38% |           1      0.40%     98.79% |           3      1.21%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          247                      
+system.ruby.Directory_Controller.GETX              61      0.00%      0.00%
+system.ruby.Directory_Controller.GETS             398      0.00%      0.00%
+system.ruby.Directory_Controller.Lockdown            2      0.00%      0.00%
+system.ruby.Directory_Controller.Unlockdown            2      0.00%      0.00%
+system.ruby.Directory_Controller.Data_Owner            3      0.00%      0.00%
+system.ruby.Directory_Controller.Data_All_Tokens           81      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner           16      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens          334      0.00%      0.00%
+system.ruby.Directory_Controller.Ack_All_Tokens           15      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          448      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack           84      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETX            52      0.00%      0.00%
+system.ruby.Directory_Controller.O.GETS           396      0.00%      0.00%
+system.ruby.Directory_Controller.O.Ack_All_Tokens           15      0.00%      0.00%
+system.ruby.Directory_Controller.NO.GETX            6      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_Owner            3      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Data_All_Tokens           81      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner           16      0.00%      0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens          334      0.00%      0.00%
+system.ruby.Directory_Controller.L.Unlockdown            2      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETX            3      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.GETS            2      0.00%      0.00%
+system.ruby.Directory_Controller.O_W.Memory_Ack           84      0.00%      0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown            2      0.00%      0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data          446      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               415      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2585      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              294      0.00%      0.00%
@@ -786,31 +817,5 @@ system.ruby.L2Cache_Controller.M.L1_GETS           52      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L1_GETX            8      0.00%      0.00%
 system.ruby.L2Cache_Controller.M.L2_Replacement          415      0.00%      0.00%
 system.ruby.L2Cache_Controller.I_L.Persistent_GETS            2      0.00%      0.00%
-system.ruby.Directory_Controller.GETX              61      0.00%      0.00%
-system.ruby.Directory_Controller.GETS             398      0.00%      0.00%
-system.ruby.Directory_Controller.Lockdown            2      0.00%      0.00%
-system.ruby.Directory_Controller.Unlockdown            2      0.00%      0.00%
-system.ruby.Directory_Controller.Data_Owner            3      0.00%      0.00%
-system.ruby.Directory_Controller.Data_All_Tokens           81      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner           16      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens          334      0.00%      0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens           15      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          448      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack           84      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETX            52      0.00%      0.00%
-system.ruby.Directory_Controller.O.GETS           396      0.00%      0.00%
-system.ruby.Directory_Controller.O.Ack_All_Tokens           15      0.00%      0.00%
-system.ruby.Directory_Controller.NO.GETX            6      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_Owner            3      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens           81      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner           16      0.00%      0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens          334      0.00%      0.00%
-system.ruby.Directory_Controller.L.Unlockdown            2      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETX            3      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.GETS            2      0.00%      0.00%
-system.ruby.Directory_Controller.O_W.Memory_Ack           84      0.00%      0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown            2      0.00%      0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data          446      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000036                       # Nu
 sim_ticks                                       36255                       # Number of ticks simulated
 final_tick                                      36255                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  16369                       # Simulator instruction rate (inst/s)
-host_op_rate                                    16367                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 230240                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 435584                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  60442                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60421                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 849780                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449324                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -232,131 +232,35 @@ system.mem_ctrls.readRowHitRate                 80.27                       # Ro
 system.mem_ctrls.writeRowHitRate                32.61                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         69.32                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    75.06                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE             11                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            1040                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           30367                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  143640                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  309960                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                   79800                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  172200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                1634880                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                2446080                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0                     0                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1                165888                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             2034240                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            20833956                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            21069936                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0              567000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1              360000                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              25293516                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              26558304                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           805.423386                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           845.698128                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         3295                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          3295                      
-system.ruby.latency_hist::bucket_size              32                      
-system.ruby.latency_hist::max_bucket              319                      
-system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              10.006375                      
-system.ruby.latency_hist::gmean              3.254924                      
-system.ruby.latency_hist::stdev             22.032392                      
-system.ruby.latency_hist                 |        2912     88.40%     88.40% |         290      8.80%     97.21% |          87      2.64%     99.85% |           1      0.03%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.03%     99.91% |           3      0.09%    100.00%
-system.ruby.latency_hist::total                  3294                      
-system.ruby.hit_latency_hist::bucket_size            2                      
-system.ruby.hit_latency_hist::max_bucket           19                      
-system.ruby.hit_latency_hist::samples            2853                      
-system.ruby.hit_latency_hist::mean           2.266036                      
-system.ruby.hit_latency_hist::gmean          2.092620                      
-system.ruby.hit_latency_hist::stdev          1.690154                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |        2784     97.58%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |          69      2.42%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2853                      
-system.ruby.miss_latency_hist::bucket_size           32                      
-system.ruby.miss_latency_hist::max_bucket          319                      
-system.ruby.miss_latency_hist::samples            441                      
-system.ruby.miss_latency_hist::mean         60.081633                      
-system.ruby.miss_latency_hist::gmean        56.714803                      
-system.ruby.miss_latency_hist::stdev        26.697338                      
-system.ruby.miss_latency_hist            |          59     13.38%     13.38% |         290     65.76%     79.14% |          87     19.73%     98.87% |           1      0.23%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           1      0.23%     99.32% |           3      0.68%    100.00%
-system.ruby.miss_latency_hist::total              441                      
-system.ruby.Directory.incomplete_times            440                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses          240                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L2cache.demand_hits           69                       # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses          441                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses          510                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   143640                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                    79800                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 1634880                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                      0                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             20833956                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy               567000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               25293516                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            805.423386                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE          847                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1040                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         29531                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   309960                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   172200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2446080                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                 165888                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              2034240                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             21069936                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               360000                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               26558304                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            845.698128                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1450                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1040                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         29876                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     4.670390                      
-system.ruby.network.routers0.msg_count.Request_Control::2          441                      
-system.ruby.network.routers0.msg_count.Response_Data::4          441                      
-system.ruby.network.routers0.msg_count.Writeback_Data::5           81                      
-system.ruby.network.routers0.msg_count.Writeback_Control::2          425                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          425                      
-system.ruby.network.routers0.msg_count.Writeback_Control::5          344                      
-system.ruby.network.routers0.msg_count.Unblock_Control::5          440                      
-system.ruby.network.routers0.msg_bytes.Request_Control::2         3528                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        31752                      
-system.ruby.network.routers0.msg_bytes.Writeback_Data::5         5832                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2         3400                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5         2752                      
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
-system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
-system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized     4.670390                      
-system.ruby.network.routers1.msg_count.Request_Control::2          441                      
-system.ruby.network.routers1.msg_count.Response_Data::4          441                      
-system.ruby.network.routers1.msg_count.Writeback_Data::5           81                      
-system.ruby.network.routers1.msg_count.Writeback_Control::2          425                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          425                      
-system.ruby.network.routers1.msg_count.Writeback_Control::5          344                      
-system.ruby.network.routers1.msg_count.Unblock_Control::5          440                      
-system.ruby.network.routers1.msg_bytes.Request_Control::2         3528                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        31752                      
-system.ruby.network.routers1.msg_bytes.Writeback_Data::5         5832                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2         3400                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5         2752                      
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.routers2.percent_links_utilized     4.670390                      
-system.ruby.network.routers2.msg_count.Request_Control::2          441                      
-system.ruby.network.routers2.msg_count.Response_Data::4          441                      
-system.ruby.network.routers2.msg_count.Writeback_Data::5           81                      
-system.ruby.network.routers2.msg_count.Writeback_Control::2          425                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          425                      
-system.ruby.network.routers2.msg_count.Writeback_Control::5          344                      
-system.ruby.network.routers2.msg_count.Unblock_Control::5          440                      
-system.ruby.network.routers2.msg_bytes.Request_Control::2         3528                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        31752                      
-system.ruby.network.routers2.msg_bytes.Writeback_Data::5         5832                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2         3400                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         3400                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5         2752                      
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5         3520                      
-system.ruby.network.msg_count.Request_Control         1323                      
-system.ruby.network.msg_count.Response_Data         1323                      
-system.ruby.network.msg_count.Writeback_Data          243                      
-system.ruby.network.msg_count.Writeback_Control         3582                      
-system.ruby.network.msg_count.Unblock_Control         1320                      
-system.ruby.network.msg_byte.Request_Control        10584                      
-system.ruby.network.msg_byte.Response_Data        95256                      
-system.ruby.network.msg_byte.Writeback_Data        17496                      
-system.ruby.network.msg_byte.Writeback_Control        28656                      
-system.ruby.network.msg_byte.Unblock_Control        10560                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -448,6 +352,107 @@ system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         3295                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          3295                      
+system.ruby.latency_hist::bucket_size              32                      
+system.ruby.latency_hist::max_bucket              319                      
+system.ruby.latency_hist::samples                3294                      
+system.ruby.latency_hist::mean              10.006375                      
+system.ruby.latency_hist::gmean              3.254924                      
+system.ruby.latency_hist::stdev             22.032392                      
+system.ruby.latency_hist                 |        2912     88.40%     88.40% |         290      8.80%     97.21% |          87      2.64%     99.85% |           1      0.03%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           0      0.00%     99.88% |           1      0.03%     99.91% |           3      0.09%    100.00%
+system.ruby.latency_hist::total                  3294                      
+system.ruby.hit_latency_hist::bucket_size            2                      
+system.ruby.hit_latency_hist::max_bucket           19                      
+system.ruby.hit_latency_hist::samples            2853                      
+system.ruby.hit_latency_hist::mean           2.266036                      
+system.ruby.hit_latency_hist::gmean          2.092620                      
+system.ruby.hit_latency_hist::stdev          1.690154                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |        2784     97.58%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |           0      0.00%     97.58% |          69      2.42%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2853                      
+system.ruby.miss_latency_hist::bucket_size           32                      
+system.ruby.miss_latency_hist::max_bucket          319                      
+system.ruby.miss_latency_hist::samples            441                      
+system.ruby.miss_latency_hist::mean         60.081633                      
+system.ruby.miss_latency_hist::gmean        56.714803                      
+system.ruby.miss_latency_hist::stdev        26.697338                      
+system.ruby.miss_latency_hist            |          59     13.38%     13.38% |         290     65.76%     79.14% |          87     19.73%     98.87% |           1      0.23%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           0      0.00%     99.09% |           1      0.23%     99.32% |           3      0.68%    100.00%
+system.ruby.miss_latency_hist::total              441                      
+system.ruby.Directory.incomplete_times            440                      
+system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
+system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
+system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses          240                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits         2315                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses          270                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses         2585                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_hits           69                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L2cache.demand_misses          441                       # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses          510                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     4.670390                      
+system.ruby.network.routers0.msg_count.Request_Control::2          441                      
+system.ruby.network.routers0.msg_count.Response_Data::4          441                      
+system.ruby.network.routers0.msg_count.Writeback_Data::5           81                      
+system.ruby.network.routers0.msg_count.Writeback_Control::2          425                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          425                      
+system.ruby.network.routers0.msg_count.Writeback_Control::5          344                      
+system.ruby.network.routers0.msg_count.Unblock_Control::5          440                      
+system.ruby.network.routers0.msg_bytes.Request_Control::2         3528                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        31752                      
+system.ruby.network.routers0.msg_bytes.Writeback_Data::5         5832                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2         3400                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         3400                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5         2752                      
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5         3520                      
+system.ruby.network.routers1.percent_links_utilized     4.670390                      
+system.ruby.network.routers1.msg_count.Request_Control::2          441                      
+system.ruby.network.routers1.msg_count.Response_Data::4          441                      
+system.ruby.network.routers1.msg_count.Writeback_Data::5           81                      
+system.ruby.network.routers1.msg_count.Writeback_Control::2          425                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          425                      
+system.ruby.network.routers1.msg_count.Writeback_Control::5          344                      
+system.ruby.network.routers1.msg_count.Unblock_Control::5          440                      
+system.ruby.network.routers1.msg_bytes.Request_Control::2         3528                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        31752                      
+system.ruby.network.routers1.msg_bytes.Writeback_Data::5         5832                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2         3400                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         3400                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5         2752                      
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5         3520                      
+system.ruby.network.routers2.percent_links_utilized     4.670390                      
+system.ruby.network.routers2.msg_count.Request_Control::2          441                      
+system.ruby.network.routers2.msg_count.Response_Data::4          441                      
+system.ruby.network.routers2.msg_count.Writeback_Data::5           81                      
+system.ruby.network.routers2.msg_count.Writeback_Control::2          425                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          425                      
+system.ruby.network.routers2.msg_count.Writeback_Control::5          344                      
+system.ruby.network.routers2.msg_count.Unblock_Control::5          440                      
+system.ruby.network.routers2.msg_bytes.Request_Control::2         3528                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        31752                      
+system.ruby.network.routers2.msg_bytes.Writeback_Data::5         5832                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2         3400                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         3400                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5         2752                      
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5         3520                      
+system.ruby.network.msg_count.Request_Control         1323                      
+system.ruby.network.msg_count.Response_Data         1323                      
+system.ruby.network.msg_count.Writeback_Data          243                      
+system.ruby.network.msg_count.Writeback_Control         3582                      
+system.ruby.network.msg_count.Unblock_Control         1320                      
+system.ruby.network.msg_byte.Request_Control        10584                      
+system.ruby.network.msg_byte.Response_Data        95256                      
+system.ruby.network.msg_byte.Writeback_Data        17496                      
+system.ruby.network.msg_byte.Writeback_Control        28656                      
+system.ruby.network.msg_byte.Unblock_Control        10560                      
 system.ruby.network.routers0.throttle0.link_utilization     6.059854                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          441                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          425                      
@@ -682,6 +687,25 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    62.229629
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    23.299188                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         199     80.24%     80.24% |          46     18.55%     98.79% |           1      0.40%     99.19% |           0      0.00%     99.19% |           0      0.00%     99.19% |           0      0.00%     99.19% |           0      0.00%     99.19% |           0      0.00%     99.19% |           2      0.81%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          248                      
+system.ruby.Directory_Controller.GETX              51      0.00%      0.00%
+system.ruby.Directory_Controller.GETS             409      0.00%      0.00%
+system.ruby.Directory_Controller.PUT              425      0.00%      0.00%
+system.ruby.Directory_Controller.UnblockM          440      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean          344      0.00%      0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty           81      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          441      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack           81      0.00%      0.00%
+system.ruby.Directory_Controller.NO.PUT           425      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETX            47      0.00%      0.00%
+system.ruby.Directory_Controller.E.GETS           394      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM          440      0.00%      0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data          441      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETX            4      0.00%      0.00%
+system.ruby.Directory_Controller.WB.GETS           14      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean          344      0.00%      0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty           81      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.GETS            1      0.00%      0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack           81      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               422      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2591      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              298      0.00%      0.00%
@@ -723,24 +747,5 @@ system.ruby.L1Cache_Controller.MI.Store             4      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Writeback_Ack          425      0.00%      0.00%
 system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1           45      0.00%      0.00%
 system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1           24      0.00%      0.00%
-system.ruby.Directory_Controller.GETX              51      0.00%      0.00%
-system.ruby.Directory_Controller.GETS             409      0.00%      0.00%
-system.ruby.Directory_Controller.PUT              425      0.00%      0.00%
-system.ruby.Directory_Controller.UnblockM          440      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean          344      0.00%      0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty           81      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          441      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack           81      0.00%      0.00%
-system.ruby.Directory_Controller.NO.PUT           425      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETX            47      0.00%      0.00%
-system.ruby.Directory_Controller.E.GETS           394      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM          440      0.00%      0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data          441      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETX            4      0.00%      0.00%
-system.ruby.Directory_Controller.WB.GETS           14      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean          344      0.00%      0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty           81      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.GETS            1      0.00%      0.00%
-system.ruby.Directory_Controller.WB_E_W.Memory_Ack           81      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000048                       # Nu
 sim_ticks                                       47840                       # Number of ticks simulated
 final_tick                                      47840                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  31483                       # Simulator instruction rate (inst/s)
-host_op_rate                                    31473                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 584131                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 435420                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  35814                       # Simulator instruction rate (inst/s)
+host_op_rate                                    35808                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 664620                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 449364                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate                 74.87                       # Ro
 system.mem_ctrls.writeRowHitRate                87.91                       # Row buffer hit rate for writes
 system.mem_ctrls.avgGap                         38.30                       # Average gap between requests
 system.mem_ctrls.pageHitRate                    81.48                       # Row buffer hit rate, read and write combined
-system.mem_ctrls.memoryStateTime::IDLE            140                       # Time in different power states
-system.mem_ctrls.memoryStateTime::REF            1560                       # Time in different power states
-system.mem_ctrls.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT           45290                       # Time in different power states
-system.mem_ctrls.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.mem_ctrls.actEnergy::0                  249480                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.actEnergy::1                  574560                       # Energy for activate commands per rank (pJ)
-system.mem_ctrls.preEnergy::0                  138600                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.preEnergy::1                  319200                       # Energy for precharge commands per rank (pJ)
-system.mem_ctrls.readEnergy::0                2009280                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.readEnergy::1                2758080                       # Energy for read commands per rank (pJ)
-system.mem_ctrls.writeEnergy::0               1575936                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.writeEnergy::1               2208384                       # Energy for write commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::0             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.refreshEnergy::1             3051360                       # Energy for refresh commands per rank (pJ)
-system.mem_ctrls.actBackEnergy::0            30369600                       # Energy for active background per rank (pJ)
-system.mem_ctrls.actBackEnergy::1            31087116                       # Energy for active background per rank (pJ)
-system.mem_ctrls.preBackEnergy::0             1545600                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.preBackEnergy::1              916200                       # Energy for precharge background per rank (pJ)
-system.mem_ctrls.totalEnergy::0              38939856                       # Total energy per rank (pJ)
-system.mem_ctrls.totalEnergy::1              40914900                       # Total energy per rank (pJ)
-system.mem_ctrls.averagePower::0           828.930858                       # Core power per rank (mW)
-system.mem_ctrls.averagePower::1           870.974540                       # Core power per rank (mW)
-system.ruby.clk_domain.clock                        1                       # Clock period in ticks
-system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
-system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
-system.ruby.delayHist::samples                   1248                       # delay histogram for all message
-system.ruby.delayHist                    |        1248    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
-system.ruby.delayHist::total                     1248                       # delay histogram for all message
-system.ruby.outstanding_req_hist::bucket_size            1                      
-system.ruby.outstanding_req_hist::max_bucket            9                      
-system.ruby.outstanding_req_hist::samples         3295                      
-system.ruby.outstanding_req_hist::mean              1                      
-system.ruby.outstanding_req_hist::gmean             1                      
-system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.outstanding_req_hist::total          3295                      
-system.ruby.latency_hist::bucket_size              64                      
-system.ruby.latency_hist::max_bucket              639                      
-system.ruby.latency_hist::samples                3294                      
-system.ruby.latency_hist::mean              13.523376                      
-system.ruby.latency_hist::gmean              5.183572                      
-system.ruby.latency_hist::stdev             25.409311                      
-system.ruby.latency_hist                 |        3181     96.57%     96.57% |          93      2.82%     99.39% |          16      0.49%     99.88% |           1      0.03%     99.91% |           2      0.06%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.latency_hist::total                  3294                      
-system.ruby.hit_latency_hist::bucket_size            1                      
-system.ruby.hit_latency_hist::max_bucket            9                      
-system.ruby.hit_latency_hist::samples            2668                      
-system.ruby.hit_latency_hist::mean                  3                      
-system.ruby.hit_latency_hist::gmean          3.000000                      
-system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2668    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.hit_latency_hist::total              2668                      
-system.ruby.miss_latency_hist::bucket_size           64                      
-system.ruby.miss_latency_hist::max_bucket          639                      
-system.ruby.miss_latency_hist::samples            626                      
-system.ruby.miss_latency_hist::mean         58.373802                      
-system.ruby.miss_latency_hist::gmean        53.319163                      
-system.ruby.miss_latency_hist::stdev        30.235728                      
-system.ruby.miss_latency_hist            |         513     81.95%     81.95% |          93     14.86%     96.81% |          16      2.56%     99.36% |           1      0.16%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
-system.ruby.miss_latency_hist::total              626                      
-system.ruby.Directory.incomplete_times            625                      
-system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
-system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
+system.mem_ctrls_0.actEnergy                   249480                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy                   138600                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy                 2009280                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy                1575936                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy             30369600                       # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy              1545600                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy               38939856                       # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower            828.930858                       # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE         2928                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT         43008                       # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.mem_ctrls_1.actEnergy                   574560                       # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy                   319200                       # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy                 2758080                       # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy                2208384                       # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy              3051360                       # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy             31087116                       # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy               916200                       # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy               40914900                       # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower            870.974540                       # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE         1359                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF          1560                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT         44071                       # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.clk_domain.clock                         1                       # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized     6.521739                      
-system.ruby.network.routers0.msg_count.Control::2          626                      
-system.ruby.network.routers0.msg_count.Data::2          622                      
-system.ruby.network.routers0.msg_count.Response_Data::4          626                      
-system.ruby.network.routers0.msg_count.Writeback_Control::3          622                      
-system.ruby.network.routers0.msg_bytes.Control::2         5008                      
-system.ruby.network.routers0.msg_bytes.Data::2        44784                      
-system.ruby.network.routers0.msg_bytes.Response_Data::4        45072                      
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers1.percent_links_utilized     6.521739                      
-system.ruby.network.routers1.msg_count.Control::2          626                      
-system.ruby.network.routers1.msg_count.Data::2          622                      
-system.ruby.network.routers1.msg_count.Response_Data::4          626                      
-system.ruby.network.routers1.msg_count.Writeback_Control::3          622                      
-system.ruby.network.routers1.msg_bytes.Control::2         5008                      
-system.ruby.network.routers1.msg_bytes.Data::2        44784                      
-system.ruby.network.routers1.msg_bytes.Response_Data::4        45072                      
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.routers2.percent_links_utilized     6.521739                      
-system.ruby.network.routers2.msg_count.Control::2          626                      
-system.ruby.network.routers2.msg_count.Data::2          622                      
-system.ruby.network.routers2.msg_count.Response_Data::4          626                      
-system.ruby.network.routers2.msg_count.Writeback_Control::3          622                      
-system.ruby.network.routers2.msg_bytes.Control::2         5008                      
-system.ruby.network.routers2.msg_bytes.Data::2        44784                      
-system.ruby.network.routers2.msg_bytes.Response_Data::4        45072                      
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3         4976                      
-system.ruby.network.msg_count.Control            1878                      
-system.ruby.network.msg_count.Data               1866                      
-system.ruby.network.msg_count.Response_Data         1878                      
-system.ruby.network.msg_count.Writeback_Control         1866                      
-system.ruby.network.msg_byte.Control            15024                      
-system.ruby.network.msg_byte.Data              134352                      
-system.ruby.network.msg_byte.Response_Data       135216                      
-system.ruby.network.msg_byte.Writeback_Control        14928                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite                     298     11.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       2585                       # Class of executed instruction
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
+system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
+system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
+system.ruby.delayHist::samples                   1248                       # delay histogram for all message
+system.ruby.delayHist                    |        1248    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% # delay histogram for all message
+system.ruby.delayHist::total                     1248                       # delay histogram for all message
+system.ruby.outstanding_req_hist::bucket_size            1                      
+system.ruby.outstanding_req_hist::max_bucket            9                      
+system.ruby.outstanding_req_hist::samples         3295                      
+system.ruby.outstanding_req_hist::mean              1                      
+system.ruby.outstanding_req_hist::gmean             1                      
+system.ruby.outstanding_req_hist         |           0      0.00%      0.00% |        3295    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.outstanding_req_hist::total          3295                      
+system.ruby.latency_hist::bucket_size              64                      
+system.ruby.latency_hist::max_bucket              639                      
+system.ruby.latency_hist::samples                3294                      
+system.ruby.latency_hist::mean              13.523376                      
+system.ruby.latency_hist::gmean              5.183572                      
+system.ruby.latency_hist::stdev             25.409311                      
+system.ruby.latency_hist                 |        3181     96.57%     96.57% |          93      2.82%     99.39% |          16      0.49%     99.88% |           1      0.03%     99.91% |           2      0.06%     99.97% |           1      0.03%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.latency_hist::total                  3294                      
+system.ruby.hit_latency_hist::bucket_size            1                      
+system.ruby.hit_latency_hist::max_bucket            9                      
+system.ruby.hit_latency_hist::samples            2668                      
+system.ruby.hit_latency_hist::mean                  3                      
+system.ruby.hit_latency_hist::gmean          3.000000                      
+system.ruby.hit_latency_hist             |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        2668    100.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.hit_latency_hist::total              2668                      
+system.ruby.miss_latency_hist::bucket_size           64                      
+system.ruby.miss_latency_hist::max_bucket          639                      
+system.ruby.miss_latency_hist::samples            626                      
+system.ruby.miss_latency_hist::mean         58.373802                      
+system.ruby.miss_latency_hist::gmean        53.319163                      
+system.ruby.miss_latency_hist::stdev        30.235728                      
+system.ruby.miss_latency_hist            |         513     81.95%     81.95% |          93     14.86%     96.81% |          16      2.56%     99.36% |           1      0.16%     99.52% |           2      0.32%     99.84% |           1      0.16%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
+system.ruby.miss_latency_hist::total              626                      
+system.ruby.Directory.incomplete_times            625                      
+system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
+system.ruby.network.routers0.percent_links_utilized     6.521739                      
+system.ruby.network.routers0.msg_count.Control::2          626                      
+system.ruby.network.routers0.msg_count.Data::2          622                      
+system.ruby.network.routers0.msg_count.Response_Data::4          626                      
+system.ruby.network.routers0.msg_count.Writeback_Control::3          622                      
+system.ruby.network.routers0.msg_bytes.Control::2         5008                      
+system.ruby.network.routers0.msg_bytes.Data::2        44784                      
+system.ruby.network.routers0.msg_bytes.Response_Data::4        45072                      
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3         4976                      
+system.ruby.network.routers1.percent_links_utilized     6.521739                      
+system.ruby.network.routers1.msg_count.Control::2          626                      
+system.ruby.network.routers1.msg_count.Data::2          622                      
+system.ruby.network.routers1.msg_count.Response_Data::4          626                      
+system.ruby.network.routers1.msg_count.Writeback_Control::3          622                      
+system.ruby.network.routers1.msg_bytes.Control::2         5008                      
+system.ruby.network.routers1.msg_bytes.Data::2        44784                      
+system.ruby.network.routers1.msg_bytes.Response_Data::4        45072                      
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3         4976                      
+system.ruby.network.routers2.percent_links_utilized     6.521739                      
+system.ruby.network.routers2.msg_count.Control::2          626                      
+system.ruby.network.routers2.msg_count.Data::2          622                      
+system.ruby.network.routers2.msg_count.Response_Data::4          626                      
+system.ruby.network.routers2.msg_count.Writeback_Control::3          622                      
+system.ruby.network.routers2.msg_bytes.Control::2         5008                      
+system.ruby.network.routers2.msg_bytes.Data::2        44784                      
+system.ruby.network.routers2.msg_bytes.Response_Data::4        45072                      
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3         4976                      
+system.ruby.network.msg_count.Control            1878                      
+system.ruby.network.msg_count.Data               1866                      
+system.ruby.network.msg_count.Response_Data         1878                      
+system.ruby.network.msg_count.Writeback_Control         1866                      
+system.ruby.network.msg_byte.Control            15024                      
+system.ruby.network.msg_byte.Data              134352                      
+system.ruby.network.msg_byte.Response_Data       135216                      
+system.ruby.network.msg_byte.Writeback_Control        14928                      
 system.ruby.network.routers0.throttle0.link_utilization     6.538462                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          626                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          622                      
@@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean    58.999958
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev    28.587258                      
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist |           0      0.00%      0.00% |         234     78.79%     78.79% |          49     16.50%     95.29% |           3      1.01%     96.30% |           2      0.67%     96.97% |           7      2.36%     99.33% |           1      0.34%     99.66% |           0      0.00%     99.66% |           0      0.00%     99.66% |           1      0.34%    100.00%
 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total          297                      
+system.ruby.Directory_Controller.GETX             626      0.00%      0.00%
+system.ruby.Directory_Controller.PUTX             622      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Data          626      0.00%      0.00%
+system.ruby.Directory_Controller.Memory_Ack          622      0.00%      0.00%
+system.ruby.Directory_Controller.I.GETX           626      0.00%      0.00%
+system.ruby.Directory_Controller.M.PUTX           622      0.00%      0.00%
+system.ruby.Directory_Controller.IM.Memory_Data          626      0.00%      0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack          622      0.00%      0.00%
 system.ruby.L1Cache_Controller.Load               415      0.00%      0.00%
 system.ruby.L1Cache_Controller.Ifetch            2585      0.00%      0.00%
 system.ruby.L1Cache_Controller.Store              294      0.00%      0.00%
@@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement          622      0.00%      0.00%
 system.ruby.L1Cache_Controller.MI.Writeback_Ack          622      0.00%      0.00%
 system.ruby.L1Cache_Controller.IS.Data            542      0.00%      0.00%
 system.ruby.L1Cache_Controller.IM.Data             84      0.00%      0.00%
-system.ruby.Directory_Controller.GETX             626      0.00%      0.00%
-system.ruby.Directory_Controller.PUTX             622      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Data          626      0.00%      0.00%
-system.ruby.Directory_Controller.Memory_Ack          622      0.00%      0.00%
-system.ruby.Directory_Controller.I.GETX           626      0.00%      0.00%
-system.ruby.Directory_Controller.M.PUTX           622      0.00%      0.00%
-system.ruby.Directory_Controller.IM.Memory_Data          626      0.00%      0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack          622      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    27981000                       # Number of ticks simulated
 final_tick                                   27981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65720                       # Simulator instruction rate (inst/s)
-host_op_rate                                    76928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              399296424                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250660                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  95550                       # Simulator instruction rate (inst/s)
+host_op_rate                                   111835                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              580422337                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309164                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4604                       # Number of instructions simulated
 sim_ops                                          5390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -217,29 +217,34 @@ system.physmem.readRowHitRate                   83.14                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        66260.10                       # Average gap between requests
 system.physmem.pageHitRate                      83.14                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            12000                       # Time in different power states
-system.physmem.memoryStateTime::REF            780000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          22840500                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    294840                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    136080                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    160875                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                     74250                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                  2090400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                   702000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              16099650                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              15972255                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 48750                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                160500                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                20220195                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                18570765                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             856.107753                       # Core power per rank (mW)
-system.physmem.averagePower::1             786.272135                       # Core power per rank (mW)
+system.physmem_0.actEnergy                     294840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     160875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2090400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               16099650                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  48750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 20220195                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              856.107753                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          12000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        22840500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     136080                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      74250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    702000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               15972255                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 160500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 18570765                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              786.272135                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE        1588250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22654750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    1926                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1154                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               341                       # Number of conditional branches incorrect
@@ -250,6 +255,14 @@ system.cpu.branchPred.BTBHitPct             20.426065                       # BT
 system.cpu.branchPred.usedRAS                     222                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 16                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -271,6 +284,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -292,6 +313,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -313,6 +342,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits

tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000016                       # Nu
 sim_ticks                                    16223000                       # Number of ticks simulated
 final_tick                                   16223000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  26356                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30865                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               93111675                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251576                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  54860                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64243                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              193800024                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308908                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5377                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -221,53 +221,34 @@ system.physmem.readRowHitRate                   83.38                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        40695.21                       # Average gap between requests
 system.physmem.pageHitRate                      83.38                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
-system.physmem.memoryStateTime::REF            520000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    317520                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    151200                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                    173250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                     82500                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                  2238600                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                   795600                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              10793520                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              10477170                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                 31500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                309000                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                14571510                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                12832590                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             920.354334                       # Core power per rank (mW)
-system.physmem.averagePower::1             810.522027                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 355                       # Transaction distribution
-system.membus.trans_dist::ReadResp                355                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          794                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    794                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   25408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               397                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     397    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 397                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              494500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3699500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             22.8                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                     317520                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                     173250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                   2238600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               10793520                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                  31500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 14571510                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              920.354334                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE          11000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        15315250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     151200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                      82500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                    795600                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               10477170                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                 309000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 12832590                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              810.522027                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE         784250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        14853250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    2638                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1635                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               480                       # Number of conditional branches incorrect
@@ -277,6 +258,15 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             37.267968                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     354                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -298,6 +288,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.dtb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -319,6 +317,14 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                         0                       # DTB hits
 system.cpu.checker.dtb.misses                       0                       # DTB misses
 system.cpu.checker.dtb.accesses                     0                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -340,6 +346,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.itb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
@@ -365,6 +379,14 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.checker.numCycles                     5390                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -386,6 +408,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -407,6 +437,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -428,6 +466,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -744,42 +790,136 @@ system.cpu.cc_regfile_reads                     28734                       # nu
 system.cpu.cc_regfile_writes                     3302                       # number of cc regfile writes
 system.cpu.misc_regfile_reads                    3189                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq            399                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          588                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               881                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18816                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              28160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               9                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9                441    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::10                 0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            9                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            441                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        488250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          3.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        228495                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            87.114563                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2168                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             14.849315                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.114563                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021268                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021268                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1551                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1551                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          595                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            595                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data          2146                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2146                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2146                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2146                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          203                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           203                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          318                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          318                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data          521                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            521                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          521                       # number of overall misses
+system.cpu.dcache.overall_misses::total           521                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11353493                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11353493                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20745500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20745500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       130500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     32098993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     32098993                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     32098993                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     32098993                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1754                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.115735                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.348302                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.348302                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.195351                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.195351                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61610.351248                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61610.351248                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          105                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.250000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          276                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          276                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           42                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6247255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6247255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3144750                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9392005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9392005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9392005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9392005                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.059863                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.059863                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.055118                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.055118                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        74875                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           150.722255                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1666                       # Total number of references to valid blocks.
@@ -1010,135 +1150,64 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.114563                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2168                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             14.849315                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.114563                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021268                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021268                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5528                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5528                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1551                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1551                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          595                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            595                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          2146                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2146                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2146                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2146                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          203                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           203                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          318                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          318                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data          521                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            521                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          521                       # number of overall misses
-system.cpu.dcache.overall_misses::total           521                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11353493                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11353493                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     20745500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     20745500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       130500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32098993                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32098993                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32098993                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32098993                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1754                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1754                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2667                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2667                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2667                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2667                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.115735                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.115735                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.348302                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.348302                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.153846                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.195351                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.195351                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.195351                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.195351                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61610.351248                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61610.351248                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          105                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.250000                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           98                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           98                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          276                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          276                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          105                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          105                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           42                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6247255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6247255                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3144750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3144750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9392005                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9392005                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9392005                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9392005                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.059863                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.059863                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.055118                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055118                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.055118                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        74875                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        74875                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            399                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           398                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           42                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           42                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          588                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          293                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               881                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        18816                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              28160                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          441                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               9                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::7                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::8                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9                441    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10                 0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            9                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            9                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            441                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         220500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        488250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          3.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 355                       # Transaction distribution
+system.membus.trans_dist::ReadResp                355                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                42                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               42                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    794                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   25408                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               397                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     397    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 397                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              494500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3699500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             22.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 582910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   681582                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              341032781                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293692                       # Number of bytes of host memory used
+host_inst_rate                                 396323                       # Simulator instruction rate (inst/s)
+host_op_rate                                   463654                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              232084410                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298640                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5377                       # Number of ops (including micro ops) simulated
@@ -35,35 +35,15 @@ system.physmem.bw_write::total             1353868992                       # Wr
 system.physmem.bw_total::cpu.inst          6834663203                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3020597513                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9855260716                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
-system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
-system.membus.trans_dist::WriteReq                913                       # Transaction distribution
-system.membus.trans_dist::WriteResp               913                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
-system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.dtb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits
@@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                         0                       # DTB hits
 system.cpu.checker.dtb.misses                       0                       # DTB misses
 system.cpu.checker.dtb.accesses                     0                       # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.checker.itb.walker.walks                 0                       # Table walker walks requested
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.checker.itb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.itb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
@@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.checker.numCycles                        0                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5390                       # Class of executed instruction
+system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
+system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
+system.membus.trans_dist::WriteReq                913                       # Transaction distribution
+system.membus.trans_dist::WriteResp               913                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
+system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt

@@ -4,10 +4,10 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 685428                       # Simulator instruction rate (inst/s)
-host_op_rate                                   801222                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              400788339                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292412                       # Number of bytes of host memory used
+host_inst_rate                                 370272                       # Simulator instruction rate (inst/s)
+host_op_rate                                   433210                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              216878622                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297624                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5377                       # Number of ops (including micro ops) simulated
@@ -35,35 +35,15 @@ system.physmem.bw_write::total             1353868992                       # Wr
 system.physmem.bw_total::cpu.inst          6834663203                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3020597513                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             9855260716                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
-system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
-system.membus.trans_dist::WriteReq                913                       # Transaction distribution
-system.membus.trans_dist::WriteResp               913                       # Transaction distribution
-system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
-system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
-system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
-system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
-system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
-system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -85,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -106,6 +94,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -127,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -209,5 +213,33 @@ system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5390                       # Class of executed instruction
+system.membus.trans_dist::ReadReq                5596                       # Transaction distribution
+system.membus.trans_dist::ReadResp               5607                       # Transaction distribution
+system.membus.trans_dist::WriteReq                913                       # Transaction distribution
+system.membus.trans_dist::WriteResp               913                       # Transaction distribution
+system.membus.trans_dist::LoadLockedReq            11                       # Transaction distribution
+system.membus.trans_dist::StoreCondReq             11                       # Transaction distribution
+system.membus.trans_dist::StoreCondResp            11                       # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port         9208                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port         3854                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  13062                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port        18416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port         8139                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   26555                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples              6531                       # Request fanout histogram
+system.membus.snoop_fanout::mean             4.704946                       # Request fanout histogram
+system.membus.snoop_fanout::stdev            0.456102                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::2                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::3                       0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::4                    1927     29.51%     29.51% # Request fanout histogram
+system.membus.snoop_fanout::5                    4604     70.49%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               4                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               5                       # Request fanout histogram
+system.membus.snoop_fanout::total                6531                       # Request fanout histogram
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

@@ -4,10 +4,10 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    25815000                       # Number of ticks simulated
 final_tick                                   25815000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 367819                       # Simulator instruction rate (inst/s)
-host_op_rate                                   428893                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2075494452                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302164                       # Number of bytes of host memory used
+host_inst_rate                                 376930                       # Simulator instruction rate (inst/s)
+host_op_rate                                   439541                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2127142386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307352                       # Number of bytes of host memory used
 host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5329                       # Number of ops (including micro ops) simulated
@@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total          557815224                       # In
 system.physmem.bw_total::cpu.inst           557815224                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           309897347                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              867712570                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq                 307                       # Transaction distribution
-system.membus.trans_dist::ReadResp                307                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          700                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    700                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        22400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   22400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               350                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     350    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 350                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              355000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3155000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.walks                         0                       # Table walker walks requested
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.inst_hits                            0                       # ITB inst hits
 system.cpu.itb.inst_misses                          0                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
@@ -198,6 +207,118 @@ system.cpu.op_class::MemWrite                     938     17.40%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       5390                       # Class of executed instruction
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            82.900177                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1786                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.666667                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.900177                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020239                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020239                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              3995                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             3995                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          894                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             894                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            870                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data          1764                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1764                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1764                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1764                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           98                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            98                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            141                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          141                       # number of overall misses
+system.cpu.dcache.overall_misses::total           141                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4718000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4718000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2365000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2365000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7083000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7083000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7083000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7083000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          992                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1905                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1905                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098790                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098790                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.047097                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074016                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074016                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074016                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 50234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 50234.042553                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           98                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2279000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2279000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098790                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098790                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074016                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074016                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
 system.cpu.icache.tags.tagsinuse           114.428477                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                4364                       # Total number of references to valid blocks.
@@ -416,118 +537,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            82.900177                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1786                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.666667                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    82.900177                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020239                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020239                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              3995                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             3995                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          894                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             894                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            870                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data          1764                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1764                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1764                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1764                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           98                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            98                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            141                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          141                       # number of overall misses
-system.cpu.dcache.overall_misses::total           141                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4718000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4718000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      2365000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      2365000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7083000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7083000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7083000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7083000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          992                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         1905                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         1905                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098790                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098790                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074016                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074016                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074016                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074016                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 50234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 50234.042553                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           98                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4522000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4522000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2279000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2279000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6801000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6801000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098790                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098790                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.074016                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074016                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074016                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           43                       # Transaction distribution
@@ -560,5 +569,28 @@ system.cpu.toL2Bus.respLayer0.occupancy        361500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        211500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 307                       # Transaction distribution
+system.membus.trans_dist::ReadResp                307                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                43                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               43                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          700                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    700                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        22400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   22400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               350                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     350    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 350                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              355000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3155000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             12.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt

@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000024                       # Number of seconds simulated
-sim_ticks                                    24417000                       # Number of ticks simulated
-final_tick                                   24417000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    24407000                       # Number of ticks simulated
+final_tick                                   24407000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  26948                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              116974890                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 277212                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  92117                       # Simulator instruction rate (inst/s)
+host_op_rate                                    92097                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              399597243                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 289532                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5624                       # Number of instructions simulated
 sim_ops                                          5624                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           20032                       # Nu
 system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                137                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   450                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            820412008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            359094074                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1179506082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       820412008                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          820412008                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           820412008                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           359094074                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1179506082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            820748146                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            359241201                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1179989347                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       820748146                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          820748146                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           820748146                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           359241201                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1179989347                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           450                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         450                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24336000                       # Total gap between requests
+system.physmem.totGap                        24326000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895            3      2.91%     94.17% # By
 system.physmem.bytesPerActivate::896-1023            1      0.97%     95.15% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::1024-1151            5      4.85%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::total            103                       # Bytes accessed per row activation
-system.physmem.totQLat                        4914500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13352000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                        4895500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13333000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2250000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10921.11                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       10878.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29671.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1179.51                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29628.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1179.99                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1179.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1179.99                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.21                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.21                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.22                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.22                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.52                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
@@ -220,55 +220,36 @@ system.physmem.readRowHits                        344                       # Nu
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   76.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54080.00                       # Average gap between requests
+system.physmem.avgGap                        54057.78                       # Average gap between requests
 system.physmem.pageHitRate                      76.44                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
-system.physmem.memoryStateTime::REF            780000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          22851000                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    181440                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    582120                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                     99000                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    317625                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                   772200                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  2652000                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1525680                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0              14753880                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              16048350                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0               1235250                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                 99750                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                18567450                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                21225525                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             785.799080                       # Core power per rank (mW)
-system.physmem.averagePower::1             898.292335                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 400                       # Transaction distribution
-system.membus.trans_dist::ReadResp                400                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    900                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   28800                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               450                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     450    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 450                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              545500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4210750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.2                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                     181440                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      99000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    772200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy               14753880                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                1232250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 18564450                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              785.838404                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE        1971000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        20886000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     582120                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     317625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2652000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1525680                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               16041510                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  99750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 21218685                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              898.383064                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE          96500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          780000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        22756000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    1124                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               833                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               586                       # Number of conditional branches incorrect
@@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             38.705882                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                      84                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 31                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -297,7 +279,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    7                       # Number of system calls
-system.cpu.numCycles                            48835                       # number of cpu cycles simulated
+system.cpu.numCycles                            48815                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken          421                       # Number of Branches Predicted As Taken (True).
@@ -322,9 +304,9 @@ system.cpu.contextSwitches                          1                       # Nu
 system.cpu.threadCycles                          9295                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.timesIdled                             454                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           43587                       # Number of cycles cpu's stages were not processed
+system.cpu.idleCycles                           43567                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                             5248                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         10.746391                       # Percentage of cycles cpu is active
+system.cpu.activity                         10.750794                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1132                       # Number of Load instructions committed
 system.cpu.comStores                              901                       # Number of Store instructions committed
 system.cpu.comBranches                            883                       # Number of Branches instructions committed
@@ -336,36 +318,148 @@ system.cpu.committedInsts                        5624                       # Nu
 system.cpu.committedOps                          5624                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5624                       # Number of Instructions committed (Total)
-system.cpu.cpi                               8.683321                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               8.679765                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         8.683321                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.115163                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         8.679765                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.115210                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.115163                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    45291                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.115210                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    45271                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      3544                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                7.257090                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    46099                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization                7.260064                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    46079                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      2736                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                5.602539                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    46145                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                5.604835                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    46125                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      2690                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                5.508344                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    47641                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization                5.510601                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    47621                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1194                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.444968                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    46041                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization                2.445969                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46021                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      2794                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                5.721306                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization                5.723651                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            89.114959                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                1596                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.649635                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    89.114959                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021757                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021757                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033447                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4203                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4203                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1035                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1035                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          561                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            561                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1596                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1596                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1596                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1596                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          340                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          340                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
+system.cpu.dcache.overall_misses::total           437                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7368000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7368000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20579000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20579000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     27947000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     27947000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     27947000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     27947000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1132                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2033                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2033                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085689                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085689                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.377358                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.377358                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.214953                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.214953                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.214953                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.214953                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63951.945080                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63951.945080                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.384615                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          290                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          290                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          300                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          300                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          300                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6703250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3771500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3771500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10474750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10474750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10474750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10474750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        75430                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        75430                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           147.900639                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           147.861470                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 418                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               315                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              1.326984                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   147.900639                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072217                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072217                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.861470                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.072198                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.072198                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          302                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
@@ -384,12 +478,12 @@ system.cpu.icache.demand_misses::cpu.inst          344                       # n
 system.cpu.icache.demand_misses::total            344                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.icache.overall_misses::total           344                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25151000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25151000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25151000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25151000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25151000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25151000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25136000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25136000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25136000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25136000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25136000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25136000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          762                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          762                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          762                       # number of demand (read+write) accesses
@@ -402,12 +496,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.451444
 system.cpu.icache.demand_miss_rate::total     0.451444                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.451444                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.451444                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73113.372093                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73113.372093                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73069.767442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73069.767442                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -428,25 +522,156 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          315
 system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22975000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22975000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22975000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22975000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22960000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22960000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22960000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22960000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.413386                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.413386                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.413386                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.413386                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          204.748410                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              400                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.005000                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   149.325774                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    55.422636                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004557                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001691                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006248                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012207                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4066                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4066                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          400                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           450                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          137                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          450                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22619000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6609750                       # number of ReadReq miss cycles
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3718500                       # number of ReadExReq miss cycles
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+system.cpu.l2cache.demand_miss_latency::cpu.inst     22619000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10328250                       # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.inst     22619000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10328250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     32947250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.inst          315                       # number of demand (read+write) accesses
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+system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993651                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993651                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995575                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993651                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995575                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        74370                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        74370                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::total          450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          450                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18689500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5530750                       # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3088000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18689500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8618750                       # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8618750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27308250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995575                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995575                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        61760                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        61760                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        60685                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        60685                       # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            402                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           402                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
@@ -475,248 +700,28 @@ system.cpu.toL2Bus.respLayer0.occupancy        532000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        224750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          204.797884                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              400                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.005000                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   149.365797                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    55.432088                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004558                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001692                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006250                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012207                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             4066                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            4066                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          400                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           50                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           50                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          137                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           450                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          137                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          450                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22634000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6609750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29243750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3723500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3723500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22634000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10333250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32967250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22634000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10333250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32967250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          402                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           50                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           50                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          315                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          315                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993651                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.995025                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993651                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.995575                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993651                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.995575                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        74470                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        74470                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          400                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           50                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           50                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          450                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          450                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18704000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5530750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24234750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3093000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3093000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18704000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8623750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27327750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18704000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8623750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27327750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995025                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.995575                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993651                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.995575                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        61860                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        61860                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            89.129655                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                1596                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               137                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.649635                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    89.129655                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021760                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021760                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          137                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          107                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.033447                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              4203                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             4203                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1035                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1035                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          561                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            561                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1596                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1596                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1596                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1596                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          340                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          340                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          437                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            437                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          437                       # number of overall misses
-system.cpu.dcache.overall_misses::total           437                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7368000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7368000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     20584000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     20584000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     27952000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     27952000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     27952000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     27952000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1132                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1132                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2033                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2033                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2033                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2033                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085689                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.085689                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.377358                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.377358                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.214953                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.214953                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.214953                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.214953                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63963.386728                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63963.386728                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.384615                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          290                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          290                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          300                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          300                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          137                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          137                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          137                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          137                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6703250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6703250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3776500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3776500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10479750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10479750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10479750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10479750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.076855                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.076855                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.067388                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067388                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.067388                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        75530                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        75530                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq                 400                       # Transaction distribution
+system.membus.trans_dist::ReadResp                400                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    900                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        28800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   28800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               450                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     450    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 450                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              545500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4210250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------

tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt

@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21163500                       # Number of ticks simulated
 final_tick                                   21163500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24711                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24708                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              104867636                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278232                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  81533                       # Simulator instruction rate (inst/s)
+host_op_rate                                    81515                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              345921870                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292088                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4986                       # Number of instructions simulated
 sim_ops                                          4986                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -222,53 +222,34 @@ system.physmem.readRowHitRate                   75.58                       # Ro
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        44762.21                       # Average gap between requests
 system.physmem.pageHitRate                      75.58                       # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE            11000                       # Time in different power states
-system.physmem.memoryStateTime::REF            520000                       # Time in different power states
-system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
-system.physmem.memoryStateTime::ACT          15315250                       # Time in different power states
-system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
-system.physmem.actEnergy::0                    136080                       # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1                    536760                       # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0                     74250                       # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1                    292875                       # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0                   569400                       # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1                  2285400                       # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0                       0                       # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1                       0                       # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1               1017120                       # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0               9955620                       # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1              10734525                       # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0                766500                       # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1                 83250                       # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0                12518970                       # Total energy per rank (pJ)
-system.physmem.totalEnergy::1                14949930                       # Total energy per rank (pJ)
-system.physmem.averagePower::0             790.713406                       # Core power per rank (mW)
-system.physmem.averagePower::1             944.255803                       # Core power per rank (mW)
-system.membus.trans_dist::ReadReq                 421                       # Transaction distribution
-system.membus.trans_dist::ReadResp                421                       # Transaction distribution
-system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
-system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                    942                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                   30144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples               471                       # Request fanout histogram
-system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
-system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                     471    100.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                 471                       # Request fanout histogram
-system.membus.reqLayer0.occupancy              594000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4415500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             20.9                       # Layer utilization (%)
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.physmem_0.actEnergy                     136080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                      74250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                    569400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy                9948780                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy                 772500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy                 12518130                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              790.660351                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE        2505250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT        14081250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
+system.physmem_1.actEnergy                     536760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                     292875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                   2285400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy                1017120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy               10734525                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy                  83250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy                 14949930                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              944.255803                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE          97000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF          520000                       # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT        15229250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
 system.cpu.branchPred.lookups                    2146                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1406                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               427                       # Number of conditional branches incorrect
@@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect                    0                       # Nu
 system.cpu.branchPred.BTBHitPct             32.273839                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     284                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 68                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -589,34 +571,118 @@ system.cpu.int_regfile_writes                    5247                       # nu
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                     164                       # number of misc regfile reads
-system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          666                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total               948                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total              30336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples          474                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                474    100.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total            474                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy         237000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        562000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        227000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            91.168146                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2445                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             17.340426                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.168146                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022258                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022258                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              6061                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             6061                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         1893                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1893                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          552                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            552                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2445                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2445                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2445                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2445                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          166                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           166                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          349                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          349                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          515                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            515                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          515                       # number of overall misses
+system.cpu.dcache.overall_misses::total           515                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11320500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11320500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22383749                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22383749                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33704249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33704249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33704249                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33704249                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2059                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2960                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2960                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2960                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2960                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080622                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.080622                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.387347                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.387347                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.173986                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.173986                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.173986                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.173986                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65445.143689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65445.143689                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.090909                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          299                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          299                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4032499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4032499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11343499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11343499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11343499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11343499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044196                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044196                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.047635                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.047635                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                17                       # number of replacements
 system.cpu.icache.tags.tagsinuse           158.344728                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1593                       # Total number of references to valid blocks.
@@ -838,117 +904,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.168146                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                2445                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               141                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             17.340426                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.168146                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022258                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022258                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              6061                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             6061                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         1893                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1893                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          552                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            552                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2445                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2445                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2445                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2445                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          166                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           166                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          349                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          349                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          515                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            515                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          515                       # number of overall misses
-system.cpu.dcache.overall_misses::total           515                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11320500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11320500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22383749                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22383749                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33704249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33704249                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33704249                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33704249                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2059                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2059                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2960                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2960                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2960                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2960                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080622                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.080622                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.387347                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.387347                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.173986                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.173986                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.173986                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.173986                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65445.143689                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65445.143689                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.090909                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           75                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           75                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          299                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          299                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          374                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          374                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          374                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           50                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           50                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7311000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7311000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4032499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4032499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11343499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     11343499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11343499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     11343499                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044196                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044196                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055494                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.047635                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.047635                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.047635                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq            424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           424                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           50                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           50                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          666                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          282                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               948                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        21312                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total              30336                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples          474                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                474    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total            474                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy         237000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        562000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          2.7                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        227000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadReq                 421                       # Transaction distribution
+system.membus.trans_dist::ReadResp                421                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                50                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               50                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    942                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        30144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                   30144                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops                                0                       # Total snoops (count)
+system.membus.snoop_fanout::samples               471                       # Request fanout histogram
+system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
+system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
+system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
+system.membus.snoop_fanout::0                     471    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
+system.membus.snoop_fanout::total                 471                       # Request fanout histogram
+system.membus.reqLayer0.occupancy              594000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4415500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             20.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------