stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
This commit is contained in:
Andreas Hansson
parent
fc315901ff
commit
8909843a76
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@ -1,14 +1,14 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.061494 # Number of seconds simulated
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sim_ticks 61493732000 # Number of ticks simulated
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final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.061593 # Number of seconds simulated
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sim_ticks 61592600500 # Number of ticks simulated
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final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 144123 # Simulator instruction rate (inst/s)
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host_op_rate 144840 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 97818525 # Simulator tick rate (ticks/s)
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host_mem_usage 433504 # Number of bytes of host memory used
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host_seconds 628.65 # Real time elapsed on the host
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host_inst_rate 271325 # Simulator instruction rate (inst/s)
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host_op_rate 272676 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 184448880 # Simulator tick rate (ticks/s)
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host_mem_usage 445184 # Number of bytes of host memory used
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host_seconds 333.93 # Real time elapsed on the host
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sim_insts 90602849 # Number of instructions simulated
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sim_ops 91054080 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu
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system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15575 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
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@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 61493643500 # Total gap between requests
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system.physmem.totGap 61592506000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation
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system.physmem.totQLat 73247750 # Total ticks spent queuing
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system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
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system.physmem.totQLat 77242000 # Total ticks spent queuing
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system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst
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system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.13 # Data bus utilization in percentage
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@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 14031 # Number of row buffer hits during reads
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system.physmem.readRowHits 14018 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
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system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 3948227.51 # Average gap between requests
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system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ)
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system.physmem.avgGap 3954575.02 # Average gap between requests
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system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ)
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system.physmem_0.averagePower 671.483541 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states
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system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ)
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system.physmem_0.averagePower 671.572046 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states
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system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
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system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ)
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system.physmem_1.averagePower 671.402933 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states
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system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states
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system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ)
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system.physmem_1.averagePower 671.509428 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states
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system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 20789429 # Number of BP lookups
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system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted
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system.cpu.branchPred.lookups 20789446 # Number of BP lookups
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system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits
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system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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@ -377,89 +377,89 @@ system.cpu.itb.hits 0 # DT
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 122987464 # number of cpu cycles simulated
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system.cpu.numCycles 123185201 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 90602849 # Number of instructions committed
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system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
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system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit
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system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit
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system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
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system.cpu.cpi 1.357435 # CPI: cycles per instruction
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system.cpu.ipc 0.736684 # IPC: instructions per cycle
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system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked
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system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped
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system.cpu.cpi 1.359617 # CPI: cycles per instruction
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system.cpu.ipc 0.735501 # IPC: instructions per cycle
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system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked
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system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped
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system.cpu.dcache.tags.replacements 946107 # number of replacements
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system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks.
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system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks.
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system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy
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system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses
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system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses
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system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26259886 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 988866 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26259649 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 989105 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -470,14 +470,14 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 943286 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses
|
||||
|
|
@ -486,14 +486,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950203
|
|||
system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -502,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27857009 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27857028 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 803 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -577,38 +577,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803
|
|||
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||
|
|
@ -618,41 +618,41 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 935423 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses
|
||||
system.cpu.l2cache.overall_hits::total 935422 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15583 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::total 15584 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -666,28 +666,28 @@ system.cpu.l2cache.demand_accesses::total 951006 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -696,15 +696,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses
|
||||
|
|
@ -716,17 +716,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15575
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -738,17 +738,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
|
||||
|
|
@ -763,25 +763,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
|
||||
|
|
@ -802,9 +800,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15575 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu
|
|||
sim_ticks 54141000000 # Number of ticks simulated
|
||||
final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1669323 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 997531404 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 433488 # Number of bytes of host memory used
|
||||
host_seconds 54.28 # Real time elapsed on the host
|
||||
host_inst_rate 1893120 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1131265211 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 433636 # Number of bytes of host memory used
|
||||
host_seconds 47.86 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91053638 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736
|
|||
system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 135031170 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 135031170 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.147041 # Number of seconds simulated
|
||||
sim_ticks 147041218000 # Number of ticks simulated
|
||||
final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 147041218500 # Number of ticks simulated
|
||||
final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1114927 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1809956176 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 442716 # Number of bytes of host memory used
|
||||
host_seconds 81.24 # Real time elapsed on the host
|
||||
host_inst_rate 937429 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 942087 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1521808702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 442868 # Number of bytes of host memory used
|
||||
host_seconds 96.62 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91026990 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 294082436 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 294082437 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90576861 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu
|
|||
system.cpu.num_load_insts 22475911 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 294082435.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 18732304 # Number of branches fetched
|
||||
|
|
@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91054080 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795
|
|||
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
|
||||
|
|
@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
|
|||
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
|
||||
|
|
@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
|
|||
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
|
|||
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
|
||||
|
|
@ -477,17 +477,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -512,17 +512,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -542,17 +542,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15340
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -564,17 +564,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
|
|
@ -589,19 +589,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
|
|
@ -628,9 +626,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15340 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.361489 # Number of seconds simulated
|
||||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 361488530500 # Number of ticks simulated
|
||||
final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1379749 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2045576865 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 421936 # Number of bytes of host memory used
|
||||
host_seconds 176.72 # Real time elapsed on the host
|
||||
host_inst_rate 1163469 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1724927568 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 425840 # Number of bytes of host memory used
|
||||
host_seconds 209.57 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 155623 # In
|
|||
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 722977060 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 722977061 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
|
|
@ -73,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu
|
|||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
|
|
@ -112,244 +89,13 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -440,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -460,17 +206,248 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 244420617 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 924850 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 879 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 157 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1036 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000176 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001159 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 879 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 157 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1036 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
|
|
@ -500,5 +477,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.365989 # Number of seconds simulated
|
||||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 365989065500 # Number of ticks simulated
|
||||
final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 756908 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1753418925 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 446124 # Number of bytes of host memory used
|
||||
host_seconds 208.73 # Real time elapsed on the host
|
||||
host_inst_rate 638452 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1479007835 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 450980 # Number of bytes of host memory used
|
||||
host_seconds 247.46 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,36 +36,10 @@ system.physmem.bw_total::writebacks 17487 # To
|
|||
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1025 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1025 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 100 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 30149 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30149 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 731978130 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 731978131 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
|
|
@ -86,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu
|
|||
system.cpu.num_load_insts 90779385 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
|
|
@ -125,245 +99,13 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 217695356 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 318 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 100 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -440,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
|
|||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -456,15 +198,247 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 217695356 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 318 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 100 # number of writebacks
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
|
||||
|
|
@ -496,5 +470,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 1025 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1025 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 100 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 30149 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30149 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu
|
|||
sim_ticks 279362297500 # Number of ticks simulated
|
||||
final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1700410 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 937717572 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304668 # Number of bytes of host memory used
|
||||
host_seconds 297.92 # Real time elapsed on the host
|
||||
host_inst_rate 1941586 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1070717412 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304560 # Number of bytes of host memory used
|
||||
host_seconds 260.91 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 548694828 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325
|
|||
system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 687930749 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.707539 # Number of seconds simulated
|
||||
sim_ticks 707539023000 # Number of ticks simulated
|
||||
final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.707538 # Number of seconds simulated
|
||||
sim_ticks 707538046500 # Number of ticks simulated
|
||||
final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1166033 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1633733414 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312880 # Number of bytes of host memory used
|
||||
host_seconds 433.08 # Real time elapsed on the host
|
||||
host_inst_rate 1058036 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1482416058 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313032 # Number of bytes of host memory used
|
||||
host_seconds 477.29 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 546878104 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,16 +26,16 @@ system.physmem.num_reads::total 142649 # Nu
|
|||
system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1415078046 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1415076093 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986853 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu
|
|||
system.cpu.num_load_insts 115884756 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548301 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548695378 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n
|
|||
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917
|
|||
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
|
|
@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
|||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
|
||||
|
|
@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
|||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
|||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
|
|
@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142649 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -546,17 +546,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -568,17 +568,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
|
|
@ -593,19 +593,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
|
|
@ -633,9 +631,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 238603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.647873 # Number of seconds simulated
|
||||
sim_ticks 1647872849000 # Number of ticks simulated
|
||||
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1647872738500 # Number of ticks simulated
|
||||
final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 845545 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1685075999 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318276 # Number of bytes of host memory used
|
||||
host_seconds 977.92 # Real time elapsed on the host
|
||||
host_inst_rate 730118 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1455043701 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323120 # Number of bytes of host memory used
|
||||
host_seconds 1132.52 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,46 +26,20 @@ system.physmem.num_reads::total 381143 # Nu
|
|||
system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 174452 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 174452 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 292286 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 673429 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 673429 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3295745698 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3295745477 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877110 # Number of instructions committed
|
||||
|
|
@ -86,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu
|
|||
system.cpu.num_load_insts 384102157 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160186 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 149758583 # Number of branches fetched
|
||||
|
|
@ -125,13 +99,122 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2323523 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
|
||||
|
|
@ -155,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
|
|||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses
|
||||
|
|
@ -173,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
|
|||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -193,34 +276,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
|
|||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 348459 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy
|
||||
|
|
@ -257,17 +340,17 @@ system.cpu.l2cache.demand_misses::total 381143 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 381143 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -292,17 +375,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.151171 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -324,17 +407,17 @@ system.cpu.l2cache.demand_mshr_misses::total 381143
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -346,127 +429,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 530743930 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2323523 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
||||
|
|
@ -498,5 +472,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 174452 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 174452 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 292286 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 673429 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 673429 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.226819 # Number of seconds simulated
|
||||
sim_ticks 226818771000 # Number of ticks simulated
|
||||
final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.226866 # Number of seconds simulated
|
||||
sim_ticks 226865901500 # Number of ticks simulated
|
||||
final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 207340 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 207340 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 117965343 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287544 # Number of bytes of host memory used
|
||||
host_seconds 1922.76 # Real time elapsed on the host
|
||||
host_inst_rate 324605 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 324605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 184721178 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301676 # Number of bytes of host memory used
|
||||
host_seconds 1228.15 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7873 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 226818689500 # Total gap between requests
|
||||
system.physmem.totGap 226865813000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 50610250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 54380250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6341 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6303 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28809690.02 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.avgGap 28815675.47 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.664235 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.682686 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.483670 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.490749 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 46273761 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 46273750 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 95585470 # DTB read hits
|
||||
system.cpu.dtb.read_hits 95585469 # DTB read hits
|
||||
system.cpu.dtb.read_misses 115 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 95585585 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73606436 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 95585584 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73606437 # DTB write hits
|
||||
system.cpu.dtb.write_misses 857 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73607293 # DTB write accesses
|
||||
system.cpu.dtb.write_accesses 73607294 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 169191906 # DTB hits
|
||||
system.cpu.dtb.data_misses 972 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 169192878 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 98781228 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1237 # ITB misses
|
||||
system.cpu.itb.fetch_hits 98781212 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1236 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 98782465 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 98782448 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,59 +293,59 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 453637542 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 453731803 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664665 # Number of instructions committed
|
||||
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.137893 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.878818 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.138129 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.878635 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168028615 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168028622 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7112 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -382,28 +382,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
|
|||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3196 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 197567630 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 197567630 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 98776054 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 98776054 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 98776054 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 98776054 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 98776054 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 98776054 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 98776038 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5174 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 98781228 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 98781228 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 98781228 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -488,41 +488,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174
|
|||
system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id
|
||||
|
|
@ -552,17 +552,17 @@ system.cpu.l2cache.demand_misses::total 7873 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -587,17 +587,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.843024 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -617,17 +617,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7873
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -639,17 +639,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution
|
||||
|
|
@ -676,9 +676,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 #
|
|||
system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 4736 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
|
||||
|
|
@ -699,9 +699,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7873 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567335 # Number of seconds simulated
|
||||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 567335093500 # Number of ticks simulated
|
||||
final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1606485 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2286169690 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295576 # Number of bytes of host memory used
|
||||
host_seconds 248.16 # Real time elapsed on the host
|
||||
host_inst_rate 1360508 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1936123010 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299124 # Number of bytes of host memory used
|
||||
host_seconds 293.03 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 361550 # In
|
|||
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7174 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 1134670186 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134670187 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
|
|
@ -105,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu
|
|||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134670186 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1134670187 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
|
|
@ -144,245 +121,13 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664665 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
|
|
@ -460,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -476,15 +221,247 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 398660993 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 651 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3205 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 827 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4032 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870526 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.872161 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 827 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4032 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
|
|
@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7174 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.216828 # Number of seconds simulated
|
||||
sim_ticks 216828260500 # Number of ticks simulated
|
||||
final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.216865 # Number of seconds simulated
|
||||
sim_ticks 216864820000 # Number of ticks simulated
|
||||
final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113548 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 136327 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 90171945 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309844 # Number of bytes of host memory used
|
||||
host_seconds 2404.61 # Real time elapsed on the host
|
||||
host_inst_rate 175540 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 210755 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 139425507 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321524 # Number of bytes of host memory used
|
||||
host_seconds 1555.42 # Real time elapsed on the host
|
||||
sim_insts 273037856 # Number of instructions simulated
|
||||
sim_ops 327812213 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 485440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 485376 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7585 # Number of read requests accepted
|
||||
system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7584 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side
|
||||
system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
|
|
@ -53,7 +53,7 @@ system.physmem.perBankRdBursts::8 209 # Pe
|
|||
system.physmem.perBankRdBursts::9 311 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 342 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 428 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 554 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 553 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 706 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 637 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 541 # Per bank write bursts
|
||||
|
|
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 216828031000 # Total gap between requests
|
||||
system.physmem.totGap 216864583500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 7585 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 7584 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 50845500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst
|
||||
system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 53728750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6073 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6056 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28586424.65 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 28595013.65 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.690273 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.698913 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.748242 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.797614 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 33221230 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 33219592 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
|
|
@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 433656521 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 433729640 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037856 # Number of instructions committed
|
||||
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.588265 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.629618 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.588533 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.629512 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 1354 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168762017 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7290 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168760435 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7280 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
|
||||
|
|
@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -472,14 +472,14 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
|
||||
|
|
@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4511
|
|||
system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 36927 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 36897 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 73270394 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38865 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 73252005 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38835 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 35746 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses
|
||||
system.cpu.l2cache.overall_hits::total 35718 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::total 7628 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 4731 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4731 # Transaction distribution
|
||||
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7585 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 7584 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7585 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 7584 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu
|
|||
sim_ticks 201717313500 # Number of ticks simulated
|
||||
final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1117455 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 825564009 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308812 # Number of bytes of host memory used
|
||||
host_seconds 244.34 # Real time elapsed on the host
|
||||
host_inst_rate 1235958 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 913112758 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308700 # Number of bytes of host memory used
|
||||
host_seconds 220.91 # Real time elapsed on the host
|
||||
sim_insts 273037594 # Number of instructions simulated
|
||||
sim_ops 327811949 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979
|
|||
system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 517024351 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 517024351 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.517235 # Number of seconds simulated
|
||||
sim_ticks 517235411000 # Number of ticks simulated
|
||||
final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 517235404500 # Number of ticks simulated
|
||||
final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 761441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 914138 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1444030997 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318052 # Number of bytes of host memory used
|
||||
host_seconds 358.19 # Real time elapsed on the host
|
||||
host_inst_rate 693666 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 832772 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1315500911 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318184 # Number of bytes of host memory used
|
||||
host_seconds 393.19 # Real time elapsed on the host
|
||||
sim_insts 272739285 # Number of instructions simulated
|
||||
sim_ops 327433743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1034470822 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1034470809 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739285 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu
|
|||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563502 # Number of branches fetched
|
||||
|
|
@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812213 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
|
|
@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 #
|
|||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475
|
|||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
|
|
@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
|
|||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
|
||||
|
|
@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
|
|||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
|||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
|
|
@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -544,17 +544,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -566,17 +566,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
|
|
@ -591,19 +591,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6833 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.559962 # Number of seconds simulated
|
||||
sim_ticks 559961514500 # Number of ticks simulated
|
||||
final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.561963 # Number of seconds simulated
|
||||
sim_ticks 561962991000 # Number of ticks simulated
|
||||
final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 216839 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 216839 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 130731039 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291560 # Number of bytes of host memory used
|
||||
host_seconds 4283.31 # Real time elapsed on the host
|
||||
host_inst_rate 333136 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 333136 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 201563357 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305440 # Number of bytes of host memory used
|
||||
host_seconds 2788.02 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,45 +25,45 @@ system.physmem.num_reads::cpu.data 288600 # Nu
|
|||
system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291519 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66683 # Number of write requests accepted
|
||||
system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue
|
||||
system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 17935 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18289 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18306 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 17933 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18288 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18309 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18250 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18167 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18240 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18320 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18230 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18226 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18219 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18391 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18259 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18042 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 17977 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18101 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18165 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18241 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18322 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 18300 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18229 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18227 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18214 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18389 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18260 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18047 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 17980 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18105 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 559961438500 # Total gap between requests
|
||||
system.physmem.totGap 561962908000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see
|
||||
|
|
@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes
|
||||
|
|
@ -219,92 +219,92 @@ system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% #
|
|||
system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2985206750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.totQLat 2975536250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.32 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 202789 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 50437 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1563256.04 # Average gap between requests
|
||||
system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 201381 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 50515 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1568843.58 # Average gap between requests
|
||||
system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 692.597962 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 693.035628 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 692.677886 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 693.143857 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 125749069 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 125749002 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 237537681 # DTB read hits
|
||||
system.cpu.dtb.read_misses 198468 # DTB read misses
|
||||
system.cpu.dtb.read_hits 237537715 # DTB read hits
|
||||
system.cpu.dtb.read_misses 198475 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 237736149 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98305023 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7212 # DTB write misses
|
||||
system.cpu.dtb.read_accesses 237736190 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98305031 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7188 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 98312235 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335842704 # DTB hits
|
||||
system.cpu.dtb.data_misses 205680 # DTB misses
|
||||
system.cpu.dtb.write_accesses 98312219 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335842746 # DTB hits
|
||||
system.cpu.dtb.data_misses 205663 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 336048384 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 317138761 # ITB hits
|
||||
system.cpu.dtb.data_accesses 336048409 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 317139351 # ITB hits
|
||||
system.cpu.itb.fetch_misses 120 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 317138881 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 317139471 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -318,67 +318,67 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 1119923029 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1123925982 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928789150 # Number of instructions committed
|
||||
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.205788 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.829333 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.210098 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.826379 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 776532 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 323503178 # number of overall hits
|
||||
system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 323503203 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 849082 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 849077 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
|
||||
|
|
@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002618
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -407,12 +407,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu
|
|||
system.cpu.dcache.writebacks::total 91489 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
|
||||
|
|
@ -421,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628
|
|||
system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -437,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10606 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 10603 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 317126411 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12350 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 317138761 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 317138761 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 317138761 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 634291048 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 634291048 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 317127004 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 317127004 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 317127004 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 317127004 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 317127004 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 317127004 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12347 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12347 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12347 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12347 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 354892250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 354892250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 354892250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 354892250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 354892250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 354892250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 317139351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 317139351 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 317139351 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 317139351 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 317139351 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 317139351 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28743.196728 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28743.196728 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28743.196728 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -508,66 +508,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12347 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12347 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12347 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335095750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 335095750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335095750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 335095750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335095750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 335095750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27139.851786 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27139.851786 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258740 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 32592.816287 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 523846 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.797218 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 83.731537 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29651.786103 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002555 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.904901 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2877.420242 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.474359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29630.921686 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087812 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002578 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.904264 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994654 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2647 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29487 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 9430 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 7436199 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 7436199 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 9427 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 499089 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9430 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9427 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501458 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9430 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 501455 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9427 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501458 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501455 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2920 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses
|
||||
|
|
@ -579,52 +579,52 @@ system.cpu.l2cache.demand_misses::total 291520 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2920 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291520 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201319000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16307399500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4353044250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 201319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 20660443750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 201319000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 20660443750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223766250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17942761250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18166527500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4880260500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4880260500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 223766250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22823021750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23046788000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 223766250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22823021750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23046788000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12347 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 723964 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12350 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12347 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12350 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 792975 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12347 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236437 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 792975 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236495 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.310616 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236437 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236495 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236437 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.367628 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236495 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -646,68 +646,68 @@ system.cpu.l2cache.demand_mshr_misses::total 291520
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
|
||||
|
|
@ -729,9 +729,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 358202 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.286250 # Number of seconds simulated
|
||||
sim_ticks 1286249820000 # Number of ticks simulated
|
||||
final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1286249817500 # Number of ticks simulated
|
||||
final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1681245 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2328806930 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298588 # Number of bytes of host memory used
|
||||
host_seconds 552.32 # Real time elapsed on the host
|
||||
host_inst_rate 1412500 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1956550284 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303116 # Number of bytes of host memory used
|
||||
host_seconds 657.41 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,30 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To
|
|||
system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 357362 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 357362 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 2572499640 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2572499635 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
|
|
@ -113,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu
|
|||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2572499640 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2572499635 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
|
|
@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 91660 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
|
||||
|
|
@ -181,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n
|
|||
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 6168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
|
||||
|
|
@ -199,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007
|
|||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -219,34 +304,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168
|
|||
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 257900 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy
|
||||
|
|
@ -284,17 +369,17 @@ system.cpu.l2cache.demand_misses::total 290679 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290679 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -319,17 +404,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.369493 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -351,17 +436,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290679
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -373,127 +458,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 91660 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
|
||||
|
|
@ -523,5 +499,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 357362 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 357362 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu
|
|||
sim_ticks 395726778000 # Number of ticks simulated
|
||||
final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1395078 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 861727739 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309420 # Number of bytes of host memory used
|
||||
host_seconds 459.22 # Real time elapsed on the host
|
||||
host_inst_rate 1601804 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 989420456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309588 # Number of bytes of host memory used
|
||||
host_seconds 399.96 # Real time elapsed on the host
|
||||
sim_insts 640654410 # Number of instructions simulated
|
||||
sim_ops 788730069 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929
|
|||
system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1022670352 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.043695 # Number of seconds simulated
|
||||
sim_ticks 1043695084000 # Number of ticks simulated
|
||||
final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1043695077500 # Number of ticks simulated
|
||||
final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 894518 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1460200235 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317628 # Number of bytes of host memory used
|
||||
host_seconds 714.76 # Real time elapsed on the host
|
||||
host_inst_rate 877071 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1431720298 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317788 # Number of bytes of host memory used
|
||||
host_seconds 728.98 # Real time elapsed on the host
|
||||
sim_insts 639366786 # Number of instructions simulated
|
||||
sim_ops 785501034 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 2087390168 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2087390155 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 639366786 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu
|
|||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364859 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730743 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003
|
|||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
|
|
@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n
|
|||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
|
||||
|
|
@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208
|
|||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 256932 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy
|
||||
|
|
@ -484,17 +484,17 @@ system.cpu.l2cache.demand_misses::total 289712 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 289712 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -519,17 +519,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.365636 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 289712
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -573,17 +573,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
|
|
@ -598,19 +598,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
|
|
@ -638,9 +636,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 355811 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.133635 # Number of seconds simulated
|
||||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.133634 # Number of seconds simulated
|
||||
sim_ticks 133634149500 # Number of ticks simulated
|
||||
final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1471745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2226337698 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297712 # Number of bytes of host memory used
|
||||
host_seconds 60.02 # Real time elapsed on the host
|
||||
host_inst_rate 1329181 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2010669405 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301232 # Number of bytes of host memory used
|
||||
host_seconds 66.46 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,41 +25,17 @@ system.physmem.num_reads::cpu.data 158389 # Nu
|
|||
system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 279135 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 279135 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
|
||||
system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 267269454 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 267268299 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88340673 # Number of instructions committed
|
||||
|
|
@ -113,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu
|
|||
system.cpu.num_load_insts 20366786 # Number of load instructions
|
||||
system.cpu.num_store_insts 14620629 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 267269454 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 267268299 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
|
|
@ -152,13 +128,120 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 88438073 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168375 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 74391 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id
|
||||
|
|
@ -181,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n
|
|||
system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 76436 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses
|
||||
|
|
@ -199,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864
|
|||
system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -219,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436
|
|||
system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 131235 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses
|
||||
|
|
@ -284,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 165153 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165153 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -319,17 +402,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.588194 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -351,17 +434,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165153
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -373,125 +456,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 200248 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 204344 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168375 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
|
||||
|
|
@ -521,5 +497,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 279135 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 279135 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
|
|||
sim_ticks 48960011000 # Number of ticks simulated
|
||||
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1376675 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 950486092 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308184 # Number of bytes of host memory used
|
||||
host_seconds 51.51 # Real time elapsed on the host
|
||||
host_inst_rate 1566427 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1081494789 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308080 # Number of bytes of host memory used
|
||||
host_seconds 45.27 # Real time elapsed on the host
|
||||
sim_insts 70913181 # Number of instructions simulated
|
||||
sim_ops 90688136 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556
|
|||
system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 120930618 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.127294 # Number of seconds simulated
|
||||
sim_ticks 127293983000 # Number of ticks simulated
|
||||
final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.127293 # Number of seconds simulated
|
||||
sim_ticks 127293405500 # Number of ticks simulated
|
||||
final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 894668 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1618302823 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317432 # Number of bytes of host memory used
|
||||
host_seconds 78.66 # Real time elapsed on the host
|
||||
host_inst_rate 802256 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1451138855 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317568 # Number of bytes of host memory used
|
||||
host_seconds 87.72 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 89847362 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu
|
|||
system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 254587966 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 254586811 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70373628 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu
|
|||
system.cpu.num_load_insts 22866262 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741485 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 90690083 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -230,8 +230,8 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits
|
||||
|
|
@ -240,28 +240,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42576328 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42576331 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 177384 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 177381 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220
|
|||
system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -304,12 +304,12 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128239 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
|
||||
|
|
@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140
|
|||
system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -340,26 +340,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
|
||||
|
|
@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
|
|||
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 18908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
|
||||
|
|
@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
|
|||
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -418,43 +418,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908
|
|||
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses
|
||||
|
|
@ -483,17 +483,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 127812 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -518,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -550,17 +550,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -572,17 +572,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
|
|
@ -597,19 +597,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
|
|
@ -627,19 +625,19 @@ system.membus.pkt_count::total 339533 # Pa
|
|||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214631 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 214640 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214631 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.snoop_fanout::total 214640 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.202242 # Number of seconds simulated
|
||||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 202242028500 # Number of ticks simulated
|
||||
final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1318449 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1983988186 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297988 # Number of bytes of host memory used
|
||||
host_seconds 101.94 # Real time elapsed on the host
|
||||
host_inst_rate 1201078 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1807368744 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300888 # Number of bytes of host memory used
|
||||
host_seconds 111.90 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,44 +25,20 @@ system.physmem.num_reads::cpu.data 122291 # Nu
|
|||
system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 30277 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 30277 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214401 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214401 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 404484520 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 404484057 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 134398962 # Number of instructions committed
|
||||
|
|
@ -81,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu
|
|||
system.cpu.num_load_insts 37275867 # Number of load instructions
|
||||
system.cpu.num_store_insts 20884381 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 404484519.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 12719095 # Number of branches fetched
|
||||
|
|
@ -120,13 +96,140 @@ system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 136293798 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 123970 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 184976 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
||||
|
|
@ -150,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n
|
|||
system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 187024 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses
|
||||
|
|
@ -168,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390
|
|||
system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024
|
|||
system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 98540 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy
|
||||
|
|
@ -253,17 +356,17 @@ system.cpu.l2cache.demand_misses::total 131533 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 131533 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -288,17 +391,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.389494 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -320,17 +423,17 @@ system.cpu.l2cache.demand_mshr_misses::total 131533
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -342,145 +445,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
|
||||
system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
|
||||
system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 150663 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 123970 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
|
||||
|
|
@ -510,5 +486,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 280536000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 30277 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 30277 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214401 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214401 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.623386 # Number of seconds simulated
|
||||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.623365 # Number of seconds simulated
|
||||
sim_ticks 2623365440500 # Number of ticks simulated
|
||||
final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1656263 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2387660297 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289632 # Number of bytes of host memory used
|
||||
host_seconds 1098.73 # Real time elapsed on the host
|
||||
host_inst_rate 1411989 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2035500124 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294160 # Number of bytes of host memory used
|
||||
host_seconds 1288.81 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,40 +26,16 @@ system.physmem.num_reads::total 1959663 # Nu
|
|||
system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977740 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977740 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 5246772452 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5246730881 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
|
|
@ -113,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu
|
|||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5246772452 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5246730881 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
|
|
@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693497 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
|
||||
|
|
@ -179,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
|
|||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
|
||||
|
|
@ -197,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -217,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
|
|||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42936500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42936500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 42936500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926937 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064589 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.464534 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses
|
||||
|
|
@ -279,17 +364,17 @@ system.cpu.l2cache.demand_misses::total 1959663 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42134500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61828353000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61870487500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018308500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41018308500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42134500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102846661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102888796000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42134500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102846661500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102888796000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -314,17 +399,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215051 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -346,17 +431,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959663
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32510000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47697633000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47730143000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642696500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642696500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32510000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79340329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 79372839500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32510000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79340329500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 79372839500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -368,127 +453,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693497 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
||||
|
|
@ -518,5 +494,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977740 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977740 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu
|
|||
sim_ticks 832017490000 # Number of ticks simulated
|
||||
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1680600 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 905297170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301428 # Number of bytes of host memory used
|
||||
host_seconds 919.05 # Real time elapsed on the host
|
||||
host_inst_rate 1937211 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1043527090 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301332 # Number of bytes of host memory used
|
||||
host_seconds 797.31 # Real time elapsed on the host
|
||||
sim_insts 1544563041 # Number of instructions simulated
|
||||
sim_ops 1664032433 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063
|
|||
system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2172060894 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.363671 # Number of seconds simulated
|
||||
sim_ticks 2363670998000 # Number of ticks simulated
|
||||
final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.363663 # Number of seconds simulated
|
||||
sim_ticks 2363662966500 # Number of ticks simulated
|
||||
final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1113267 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1710076181 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309628 # Number of bytes of host memory used
|
||||
host_seconds 1382.20 # Real time elapsed on the host
|
||||
host_inst_rate 1021163 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1568591191 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309800 # Number of bytes of host memory used
|
||||
host_seconds 1506.87 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1658228914 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,16 +26,16 @@ system.physmem.num_reads::total 1958774 # Nu
|
|||
system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4727341996 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4727325933 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759601 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu
|
|||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462426 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032480 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n
|
|||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235
|
|||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
|
|
@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
|||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
|
||||
|
|
@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -411,37 +411,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
|
|||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
|
|
@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -511,17 +511,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -543,17 +543,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -565,17 +565,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
|
|
@ -590,19 +590,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
|
|
@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2975972 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.882581 # Number of seconds simulated
|
||||
sim_ticks 5882580526000 # Number of ticks simulated
|
||||
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.882580 # Number of seconds simulated
|
||||
sim_ticks 5882580398500 # Number of ticks simulated
|
||||
final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 912016 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1783532526 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308940 # Number of bytes of host memory used
|
||||
host_seconds 3298.27 # Real time elapsed on the host
|
||||
host_inst_rate 733187 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1433815394 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313792 # Number of bytes of host memory used
|
||||
host_seconds 4102.75 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -27,7 +27,7 @@ system.physmem.num_writes::writebacks 1018421 # Nu
|
|||
system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21312106 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s)
|
||||
|
|
@ -35,37 +35,11 @@ system.physmem.bw_write::total 11079992 # Wr
|
|||
system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018421 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977330 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977330 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
system.physmem.bw_total::total 32392098 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11765161052 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11765160797 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
|
|
@ -86,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu
|
|||
system.cpu.num_load_insts 1239184746 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11765161051.998001 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11765160796.998001 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
|
|
@ -125,6 +99,115 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587033 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853917000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587033 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143328499000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382147000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57382147000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200710646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200710646000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200710646000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200710646000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22025.431824 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22025.431824 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3697956 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54547406500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 54547406500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 187041630500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 187041630500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
|
||||
|
|
@ -152,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n
|
|||
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37138500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 37138500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 37138500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 37138500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 37138500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 37138500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
|
||||
|
|
@ -170,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55020 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55020 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55020 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55020 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55020 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55020 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -190,34 +273,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675
|
|||
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36126000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 36126000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36126000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 36126000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36126000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 36126000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53520 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53520 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926197 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.249311 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768621000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy
|
||||
|
|
@ -252,17 +335,17 @@ system.cpu.l2cache.demand_misses::total 1958909 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35451000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61789308500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61824759500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41017993500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41017993500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 35451000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102807302000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102842753000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 35451000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102807302000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102842753000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -287,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214949 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52520 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -319,17 +402,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958909
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27350500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47666040500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47693391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642453500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642453500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27350500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79308494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 79335844500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27350500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79308494000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 79335844500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -341,127 +424,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3697956 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
|
||||
|
|
@ -493,5 +467,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018421 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977330 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977330 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7158077000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9794545500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.052167 # Number of seconds simulated
|
||||
sim_ticks 52167245000 # Number of ticks simulated
|
||||
final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.052202 # Number of seconds simulated
|
||||
sim_ticks 52201532500 # Number of ticks simulated
|
||||
final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 211928 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 211928 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 120297341 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286252 # Number of bytes of host memory used
|
||||
host_seconds 433.65 # Real time elapsed on the host
|
||||
host_inst_rate 357575 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 357575 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 203104604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300132 # Number of bytes of host memory used
|
||||
host_seconds 257.02 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5318 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 52167163500 # Total gap between requests
|
||||
system.physmem.totGap 52201444000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 32099750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 33415750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.05 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4338 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4331 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9809545.60 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 9815991.73 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.898193 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.967540 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.088108 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.083336 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 11476348 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 11476351 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 26977004 # DT
|
|||
system.cpu.dtb.data_misses 47407 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27024411 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 23068130 # ITB hits
|
||||
system.cpu.itb.fetch_hits 23068140 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 23068218 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 23068228 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 104334490 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 104403065 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.135266 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.880851 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.136013 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.880272 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
|
|
@ -320,16 +320,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26568138 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26568135 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses
|
||||
|
|
@ -338,22 +338,22 @@ system.cpu.dcache.demand_misses::cpu.data 3430 # n
|
|||
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses
|
||||
|
|
@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230
|
|||
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13871 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
|
|
@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 23052294 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 23052304 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15836 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 23068140 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 23068140 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 23068140 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -489,38 +489,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836
|
|||
system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
|
|
@ -554,17 +554,17 @@ system.cpu.l2cache.demand_misses::total 5318 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5318 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -589,17 +589,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.294381 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5318
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -641,17 +641,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution
|
||||
|
|
@ -678,9 +678,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 #
|
|||
system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 3599 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3599 # Transaction distribution
|
||||
|
|
@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5318 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.118729 # Number of seconds simulated
|
||||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 118729316500 # Number of ticks simulated
|
||||
final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1660785 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2145562848 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293264 # Number of bytes of host memory used
|
||||
host_seconds 55.34 # Real time elapsed on the host
|
||||
host_inst_rate 1507080 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1946992285 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297820 # Number of bytes of host memory used
|
||||
host_seconds 60.98 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In
|
|||
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4765 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4765 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.numCycles 237458632 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 237458633 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903056 # Number of instructions committed
|
||||
|
|
@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu
|
|||
system.cpu.num_load_insts 19996208 # Number of load instructions
|
||||
system.cpu.num_store_insts 6501126 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 237458632 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 237458633 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
|
|
@ -144,245 +121,13 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91903089 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 91894580 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8510 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 91577 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 91577 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
|
||||
|
|
@ -460,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -476,15 +221,247 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 6681 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 91894580 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 8510 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 91577 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 91577 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 5968 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2621 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 422 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3043 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4765 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.338676 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2621 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 422 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3043 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
|
|
@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4765 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4765 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,42 +1,42 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.131746 # Number of seconds simulated
|
||||
sim_ticks 131745950000 # Number of ticks simulated
|
||||
final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.131756 # Number of seconds simulated
|
||||
sim_ticks 131756455500 # Number of ticks simulated
|
||||
final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 165378 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 174335 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 126440065 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304748 # Number of bytes of host memory used
|
||||
host_seconds 1041.96 # Real time elapsed on the host
|
||||
host_inst_rate 249754 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 263281 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 190965456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316672 # Number of bytes of host memory used
|
||||
host_seconds 689.95 # Real time elapsed on the host
|
||||
sim_insts 172317809 # Number of instructions simulated
|
||||
sim_ops 181650742 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 247488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 247616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3867 # Number of read requests accepted
|
||||
system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3869 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side
|
||||
system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
|
|
@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe
|
|||
system.physmem.perBankRdBursts::1 217 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 135 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 313 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 308 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 307 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 305 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 222 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 249 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 218 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 295 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 199 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 201 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 183 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 218 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 224 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 203 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 204 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
||||
|
|
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 131745861500 # Total gap between requests
|
||||
system.physmem.totGap 131756361000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 3867 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 3869 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 28130750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst
|
||||
system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 26801000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 2950 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 2968 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 34069268.55 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 34054370.90 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.807422 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.773044 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.815773 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.806861 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 49935043 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 49934480 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
|
|
@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 263491900 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 263512911 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317809 # Number of instructions committed
|
||||
system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.529104 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.653978 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.529226 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.653925 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40718173 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40720863 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2436 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
|
||||
|
|
@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits
|
||||
|
|
@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810
|
|||
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2909 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 2891 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 71614329 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4706 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 71597357 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4689 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2631 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses
|
||||
system.cpu.l2cache.overall_hits::total 2613 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses
|
||||
system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::total 3886 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 2777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadReq 2779 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2779 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3867 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3869 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3867 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 3869 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu
|
|||
sim_ticks 99596491000 # Number of ticks simulated
|
||||
final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1699536 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 982302061 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304728 # Number of bytes of host memory used
|
||||
host_seconds 101.39 # Real time elapsed on the host
|
||||
host_inst_rate 1940320 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1121471108 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304628 # Number of bytes of host memory used
|
||||
host_seconds 88.81 # Real time elapsed on the host
|
||||
sim_insts 172317409 # Number of instructions simulated
|
||||
sim_ops 181650341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601
|
|||
system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 230024466 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 230024466 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.230173 # Number of seconds simulated
|
||||
sim_ticks 230173357000 # Number of ticks simulated
|
||||
final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 230173357500 # Number of ticks simulated
|
||||
final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1229194 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1646435898 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312932 # Number of bytes of host memory used
|
||||
host_seconds 139.80 # Real time elapsed on the host
|
||||
host_inst_rate 1098511 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1471393960 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313104 # Number of bytes of host memory used
|
||||
host_seconds 156.43 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 181165370 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 460346714 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 460346715 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 171842483 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu
|
|||
system.cpu.num_load_insts 27896144 # Number of load instructions
|
||||
system.cpu.num_store_insts 12644635 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300311 # Number of branches fetched
|
||||
|
|
@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 181650742 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
|
||||
|
|
@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788
|
|||
system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
|
||||
|
|
@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n
|
|||
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3051 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
|
||||
|
|
@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051
|
|||
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
|
|
@ -473,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3453
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
|
|
@ -585,19 +585,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -624,9 +622,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3453 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.270563 # Number of seconds simulated
|
||||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 270563082500 # Number of ticks simulated
|
||||
final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1449498 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2027353723 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294428 # Number of bytes of host memory used
|
||||
host_seconds 133.46 # Real time elapsed on the host
|
||||
host_inst_rate 1283602 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1795321724 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297332 # Number of bytes of host memory used
|
||||
host_seconds 150.70 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 850848 # In
|
|||
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5173 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5173 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 541126164 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 541126165 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 193444518 # Number of instructions committed
|
||||
|
|
@ -73,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu
|
|||
system.cpu.num_load_insts 57735091 # Number of load instructions
|
||||
system.cpu.num_store_insts 18998867 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 15132745 # Number of branches fetched
|
||||
|
|
@ -112,240 +89,13 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 193445773 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 193433248 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12288 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 8691 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id
|
||||
|
|
@ -437,16 +187,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575
|
|||
system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -457,17 +207,244 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10362 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 193433248 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12288 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2 # number of Writeback hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 8691 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 4095 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5173 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.320272 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
|
|
@ -497,5 +474,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5173 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5173 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.250954 # Number of seconds simulated
|
||||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 250953957500 # Number of ticks simulated
|
||||
final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 881800 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1675544377 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 333860 # Number of bytes of host memory used
|
||||
host_seconds 149.77 # Real time elapsed on the host
|
||||
host_inst_rate 722726 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 338728 # Number of bytes of host memory used
|
||||
host_seconds 182.74 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,35 +29,10 @@ system.physmem.bw_inst_read::total 724276 # In
|
|||
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4735 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4735 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 501907914 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 501907915 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 132071193 # Number of instructions committed
|
||||
|
|
@ -78,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu
|
|||
system.cpu.num_load_insts 56649587 # Number of load instructions
|
||||
system.cpu.num_store_insts 20515717 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 501907913.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 12326938 # Number of branches fetched
|
||||
|
|
@ -117,245 +92,13 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 221363385 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 173489673 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4694 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 41 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id
|
||||
|
|
@ -433,14 +176,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905
|
|||
system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -449,15 +192,247 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2836 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 173489673 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4694 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 7 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 7 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1864 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2840 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 320 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 3160 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4735 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 7 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.978593 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.629357 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
|
|
@ -489,5 +464,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4735 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4735 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,56 +1,56 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783867 # Number of seconds simulated
|
||||
sim_ticks 2783867165000 # Number of ticks simulated
|
||||
final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1374338 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26797569978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 615488 # Number of bytes of host memory used
|
||||
host_seconds 103.89 # Real time elapsed on the host
|
||||
sim_insts 142773109 # Number of instructions simulated
|
||||
sim_ops 173803334 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1378466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 614624 # Number of bytes of host memory used
|
||||
host_seconds 103.57 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865
|
|||
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31526301 # DTB read hits
|
||||
system.cpu.dtb.read_hits 31526223 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8581 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124463 # DTB write hits
|
||||
system.cpu.dtb.write_hits 23124452 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534882 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125911 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534804 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125900 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650764 # DTB hits
|
||||
system.cpu.dtb.hits 54650675 # DTB hits
|
||||
system.cpu.dtb.misses 10029 # DTB misses
|
||||
system.cpu.dtb.accesses 54660793 # DTB accesses
|
||||
system.cpu.dtb.accesses 54660704 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147039592 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147039346 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -202,37 +202,37 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
|
||||
system.cpu.itb.hits 147039592 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
|
||||
system.cpu.itb.hits 147039346 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147044354 # DTB accesses
|
||||
system.cpu.numCycles 5567737414 # number of cpu cycles simulated
|
||||
system.cpu.itb.accesses 147044108 # DTB accesses
|
||||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 142773109 # Number of instructions committed
|
||||
system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873879 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153162826 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873899 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153162683 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55939365 # number of memory refs
|
||||
system.cpu.num_load_insts 31855962 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083403 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55939276 # number of memory refs
|
||||
system.cpu.num_load_insts 31855884 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083392 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36397028 # Number of branches fetched
|
||||
system.cpu.Branches 36396981 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -261,18 +261,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177220138 # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 819403 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -282,24 +282,24 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
|
||||
|
|
@ -308,24 +308,24 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612
|
|||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814075 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||
|
|
@ -348,14 +348,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682060 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682059 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1699220 # number of replacements
|
||||
system.cpu.icache.tags.replacements 1699214 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
|
|
@ -366,26 +366,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342961 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699738 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342721 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699732 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
|
||||
|
|
@ -401,17 +401,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 110027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 110026 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
|
|
@ -428,34 +428,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||||
|
|
@ -464,21 +464,21 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 147864
|
|||
system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -487,19 +487,19 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922
|
|||
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
|
|
@ -508,12 +508,12 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657
|
|||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -524,51 +524,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101898 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101897 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
||||
|
|
@ -589,11 +587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
|
|||
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -614,17 +612,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
|
|||
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
@ -667,11 +665,11 @@ system.iocache.cache_copies 0 # nu
|
|||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 74235 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138088 # Transaction distribution
|
||||
system.membus.trans_dist::ReadReq 74227 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74227 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138087 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
|
|
@ -679,34 +677,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr
|
|||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 359047 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 359047 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 359045 # Request fanout histogram
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000035 # Number of seconds simulated
|
||||
sim_ticks 34993500 # Number of ticks simulated
|
||||
final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000038 # Number of seconds simulated
|
||||
sim_ticks 37928000 # Number of ticks simulated
|
||||
final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25302 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 25300 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 138325772 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279800 # Number of bytes of host memory used
|
||||
host_seconds 0.25 # Real time elapsed on the host
|
||||
host_inst_rate 174102 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 174036 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1031016392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293404 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6400 # Number of instructions simulated
|
||||
sim_ops 6400 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu
|
|||
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 533 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 34895000 # Total gap between requests
|
||||
system.physmem.totGap 37822500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3849750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3251500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.62 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 7.03 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 435 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 437 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 65469.04 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 70961.54 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 827.438306 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states
|
||||
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 815.785757 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 809.305525 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 1972 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 1968 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 385 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2254 # DT
|
|||
system.cpu.dtb.data_misses 14 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 2268 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2642 # ITB hits
|
||||
system.cpu.itb.fetch_hits 2639 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2659 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 2656 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 69987 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 75856 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6400 # Number of instructions committed
|
||||
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 10.935469 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.091446 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 11.852500 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.084370 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1973 # number of overall hits
|
||||
system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1975 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 227 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 226 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
||||
|
|
@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
|
|||
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12250000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5649 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2277 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5643 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2274 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
|
|||
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.091079 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.671740 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses
|
||||
|
|
@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24623500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7033500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5044000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 24623500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12077500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 24623500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12077500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
|
||||
|
|
@ -654,10 +654,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 #
|
|||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 460 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 460 # Transaction distribution
|
||||
|
|
@ -678,9 +678,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 533 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 32544500 # Number of ticks simulated
|
||||
final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 485157 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 484642 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2465828156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286540 # Number of bytes of host memory used
|
||||
host_inst_rate 643051 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 642147 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3266208350 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291356 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 446 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
|
||||
system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 65088 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 65089 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -105,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 65088 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 65089 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -144,230 +121,15 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 6122 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
|
||||
|
|
@ -438,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -454,15 +216,230 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 6122 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -491,5 +468,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 446 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 18733500 # Number of ticks simulated
|
||||
final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 20287000 # Number of ticks simulated
|
||||
final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 33056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 33048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 239448729 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278492 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 136939 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 136838 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1073215892 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292092 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu
|
|||
system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 308 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 18651500 # Total gap between requests
|
||||
system.physmem.totGap 20198000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1952250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1763250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 8.22 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 7.59 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 257 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 258 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 60556.82 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 65577.92 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 806.306964 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 803.504500 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 848.926575 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 838.851326 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 793 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 791 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 58 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT
|
|||
system.cpu.dtb.data_misses 13 # DTB misses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 829 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 974 # ITB hits
|
||||
system.cpu.itb.fetch_hits 969 # ITB hits
|
||||
system.cpu.itb.fetch_misses 13 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 987 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 982 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -293,29 +293,29 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 37467 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 40574 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2585 # Number of instructions committed
|
||||
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 14.494004 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.068994 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 15.695938 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.063711 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses
|
||||
|
|
@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n
|
|||
system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 104 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653
|
|||
system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2171 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 751 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2161 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 746 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 223 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223
|
|||
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.615214 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.919264 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003620 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
|
||||
|
|
@ -528,17 +528,17 @@ system.cpu.l2cache.demand_misses::total 308 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 308 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6303750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14661500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6303750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -561,17 +561,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -591,17 +591,17 @@ system.cpu.l2cache.demand_mshr_misses::total 308
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -613,17 +613,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
|
||||
|
|
@ -649,9 +649,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 #
|
|||
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 281 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 281 # Transaction distribution
|
||||
|
|
@ -672,9 +672,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 308 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 15.3 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 8.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16524000 # Number of ticks simulated
|
||||
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16524500 # Number of ticks simulated
|
||||
final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 428144 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 427151 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2733498759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286260 # Number of bytes of host memory used
|
||||
host_inst_rate 396950 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 396157 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2535599202 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290048 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu
|
|||
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 245 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 245 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 13.3 # Layer utilization (%)
|
||||
system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 33048 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 33049 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -105,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 33048 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 33049 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -144,222 +121,13 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2423 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
|
||||
|
|
@ -432,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82
|
|||
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -448,15 +216,224 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2423 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
|
|
@ -485,5 +462,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 245 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 245 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27981000 # Number of ticks simulated
|
||||
final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 30427500 # Number of ticks simulated
|
||||
final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 40383 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 47269 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 245344554 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297404 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 90683 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 106136 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 599001910 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308040 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4604 # Number of instructions simulated
|
||||
sim_ops 5390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
|
|||
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 421 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 27895500 # Total gap between requests
|
||||
system.physmem.totGap 30336000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -187,75 +187,76 @@ system.physmem.wrQLenPdf::61 0 # Wh
|
|||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2478000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 2605000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.52 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 6.92 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 350 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 348 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 66260.10 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 72057.01 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 856.107753 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states
|
||||
system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 848.018629 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 786.272135 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 782.664197 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 1926 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 1927 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 326 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -376,44 +377,44 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 55962 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 60855 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4604 # Number of instructions committed
|
||||
system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 12.155083 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.082270 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 13.217854 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.075655 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1900 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1899 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
|
||||
|
|
@ -422,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
|
|||
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 182 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -482,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
|
|||
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1919 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1920 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 322 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -572,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322
|
|||
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
|
||||
|
|
@ -628,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -661,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -697,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -719,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
|
|
@ -743,25 +744,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadReq 378 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 378 # Transaction distribution
|
||||
|
|
@ -782,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 421 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 2694500 # Number of ticks simulated
|
||||
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 396323 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 463654 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 232084410 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298640 # Number of bytes of host memory used
|
||||
host_inst_rate 771856 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 901727 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 450886881 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297796 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5377 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -347,18 +347,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
|
|||
system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 6531 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6531 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 2694500 # Number of ticks simulated
|
||||
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 370272 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 433210 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 216878622 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297624 # Number of bytes of host memory used
|
||||
host_inst_rate 801222 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 936270 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 468120222 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297024 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5377 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -228,18 +228,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139
|
|||
system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 6531 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6531 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
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Reference in a new issue