8909843a76
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
738 lines
84 KiB
Plaintext
738 lines
84 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.561963 # Number of seconds simulated
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sim_ticks 561962991000 # Number of ticks simulated
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final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 333136 # Simulator instruction rate (inst/s)
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host_op_rate 333136 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 201563357 # Simulator tick rate (ticks/s)
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host_mem_usage 305440 # Number of bytes of host memory used
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host_seconds 2788.02 # Real time elapsed on the host
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sim_insts 928789150 # Number of instructions simulated
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sim_ops 928789150 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 291519 # Number of read requests accepted
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system.physmem.writeReqs 66683 # Number of write requests accepted
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system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 17933 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18288 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18309 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18250 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18165 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18241 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18322 # Per bank write bursts
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system.physmem.perBankRdBursts::7 18300 # Per bank write bursts
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system.physmem.perBankRdBursts::8 18229 # Per bank write bursts
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system.physmem.perBankRdBursts::9 18227 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18214 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18389 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18260 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18047 # Per bank write bursts
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system.physmem.perBankRdBursts::14 17980 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18105 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4189 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 561962908000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 291519 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66683 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads
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system.physmem.totQLat 2975536250 # Total ticks spent queuing
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system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.32 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing
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system.physmem.readRowHits 201381 # Number of row buffer hits during reads
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system.physmem.writeRowHits 50515 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes
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system.physmem.avgGap 1568843.58 # Average gap between requests
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system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ)
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system.physmem_0.averagePower 693.035628 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states
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system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 693.143857 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 125749002 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 237537715 # DTB read hits
|
|
system.cpu.dtb.read_misses 198475 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 237736190 # DTB read accesses
|
|
system.cpu.dtb.write_hits 98305031 # DTB write hits
|
|
system.cpu.dtb.write_misses 7188 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 98312219 # DTB write accesses
|
|
system.cpu.dtb.data_hits 335842746 # DTB hits
|
|
system.cpu.dtb.data_misses 205663 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 336048409 # DTB accesses
|
|
system.cpu.itb.fetch_hits 317139351 # ITB hits
|
|
system.cpu.itb.fetch_misses 120 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 317139471 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 37 # Number of system calls
|
|
system.cpu.numCycles 1123925982 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 928789150 # Number of instructions committed
|
|
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.210098 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.826379 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 776532 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 323503203 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 849077 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 91489 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 780628 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 10603 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 634291048 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 634291048 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 317127004 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 317127004 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 317127004 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 317127004 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 317127004 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 317127004 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12347 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12347 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12347 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12347 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 354892250 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 354892250 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 354892250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 354892250 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 354892250 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 354892250 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 317139351 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 317139351 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 317139351 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 317139351 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 317139351 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 317139351 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28743.196728 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 28743.196728 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 28743.196728 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 12347 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 12347 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 12347 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335095750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 335095750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335095750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 335095750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335095750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 335095750 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27139.851786 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27139.851786 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 258740 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32592.816287 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 523846 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 1.797218 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2877.420242 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.474359 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29630.921686 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.087812 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002578 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.904264 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994654 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2647 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29487 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 7436199 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 7436199 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 9427 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 499089 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 9427 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 501455 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 9427 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 501455 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2920 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2920 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 288600 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2920 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 291520 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223766250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17942761250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 18166527500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4880260500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4880260500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 223766250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 22823021750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23046788000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 223766250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 22823021750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23046788000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 12347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 723964 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 12347 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 792975 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 12347 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 792975 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236495 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.310616 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236495 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.367628 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236495 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2920 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221955 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 224875 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2920 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 288600 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649721 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 649721 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924928 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22924928 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 358202 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 358202 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 358202 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks)
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|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks)
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|
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
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|
|
|
---------- End Simulation Statistics ----------
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