8909843a76
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
854 lines
98 KiB
Plaintext
854 lines
98 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.366359 # Number of seconds simulated
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sim_ticks 366358704500 # Number of ticks simulated
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final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 242855 # Simulator instruction rate (inst/s)
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host_op_rate 263044 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 175631724 # Simulator tick rate (ticks/s)
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host_mem_usage 316616 # Number of bytes of host memory used
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host_seconds 2085.95 # Real time elapsed on the host
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sim_insts 506582155 # Number of instructions simulated
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sim_ops 548695378 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 144183 # Number of read requests accepted
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system.physmem.writeReqs 96557 # Number of write requests accepted
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system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9347 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9007 # Per bank write bursts
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system.physmem.perBankRdBursts::2 8992 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8698 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9455 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9342 # Per bank write bursts
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system.physmem.perBankRdBursts::6 8946 # Per bank write bursts
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system.physmem.perBankRdBursts::7 8102 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8570 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8679 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8773 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9374 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9521 # Per bank write bursts
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system.physmem.perBankRdBursts::14 8712 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9073 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6191 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6098 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6005 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5815 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6163 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6174 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6014 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5494 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5727 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5822 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5961 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6445 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6308 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6277 # Per bank write bursts
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system.physmem.perBankWrBursts::14 5998 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6047 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 366358675500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 144183 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 96557 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads
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system.physmem.totQLat 1536843000 # Total ticks spent queuing
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system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.33 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing
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system.physmem.readRowHits 110982 # Number of row buffer hits during reads
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system.physmem.writeRowHits 64419 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 1521802.26 # Average gap between requests
|
|
system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 684.668623 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 684.496987 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 132587783 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 732717409 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 506582155 # Number of instructions committed
|
|
system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.446394 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.691375 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 1139887 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 168306394 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1555416 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1068568 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 17670 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 401957052 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 401957052 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 200949213 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 200949213 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 200949213 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 200949213 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 200949213 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 200949213 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 19542 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 19542 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 19542 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 19542 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 19542 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 19542 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 494400997 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 494400997 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 494400997 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 494400997 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 494400997 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 494400997 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 200968755 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 200968755 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 200968755 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 200968755 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 200968755 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 200968755 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25299.406253 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 25299.406253 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19542 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 19542 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 19542 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 19542 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 19542 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 19542 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 463701003 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 463701003 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 463701003 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 463701003 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 463701003 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 463701003 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23728.431225 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23728.431225 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 111429 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27648.762381 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1684764 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 142617 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 11.813206 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 163811788500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 23520.899956 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.576322 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.286102 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.717801 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.114053 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4941 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 18355761 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 18355761 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 16076 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 747713 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 763789 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1068568 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1068568 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 255536 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 255536 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 16076 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1003249 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1019325 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 16076 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1003249 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1019325 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3466 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 39870 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 43336 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 100864 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 100864 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3466 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 140734 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 144200 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3466 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 140734 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 144200 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275297000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3285022000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3560319000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7930866750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7930866750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 275297000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11215888750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11491185750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 275297000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11215888750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11491185750 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 19542 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 787583 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 807125 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1068568 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1068568 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356400 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 19542 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1143983 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1163525 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 19542 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1143983 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1163525 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177362 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050623 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.053692 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283008 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177362 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123021 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.123934 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177362 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123021 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.123934 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79427.870744 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82393.328317 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82156.151929 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78629.310259 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78629.310259 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79689.221567 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79689.221567 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 96557 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 96557 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39855 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 43319 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100864 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 100864 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 140719 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 144183 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 140719 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 144183 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231582500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2784547250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016129750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6669444250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6669444250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231582500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453991500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9685574000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231582500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453991500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 9685574000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050604 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053671 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283008 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66854.070439 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69866.948940 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69626.024377 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66123.138583 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66123.138583 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 43319 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 43319 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 96557 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 100864 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 100864 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 240740 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 240740 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|