8909843a76
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
1480 lines
171 KiB
Text
1480 lines
171 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.802895 # Number of seconds simulated
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sim_ticks 2802894699500 # Number of ticks simulated
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final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1337323 # Simulator instruction rate (inst/s)
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host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 25528979782 # Simulator tick rate (ticks/s)
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host_mem_usage 626168 # Number of bytes of host memory used
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host_seconds 109.79 # Real time elapsed on the host
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sim_insts 146828240 # Number of instructions simulated
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sim_ops 178908039 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
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system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 631 # Number of DMA write transactions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.dtb.walker.walks 7967 # Table walker walks requested
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system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors
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system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency
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system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
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system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated
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system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
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system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.read_hits 20339720 # DTB read hits
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system.cpu0.dtb.read_misses 6874 # DTB read misses
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system.cpu0.dtb.write_hits 16391078 # DTB write hits
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system.cpu0.dtb.write_misses 1093 # DTB write misses
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system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
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system.cpu0.dtb.read_accesses 20346594 # DTB read accesses
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system.cpu0.dtb.write_accesses 16392171 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.hits 36730798 # DTB hits
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system.cpu0.dtb.misses 7967 # DTB misses
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system.cpu0.dtb.accesses 36738765 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu0.itb.walker.walks 3358 # Table walker walks requested
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system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
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system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
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system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
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system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
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system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated
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system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated
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system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
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system.cpu0.itb.inst_hits 97439331 # ITB inst hits
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system.cpu0.itb.inst_misses 3358 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
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system.cpu0.itb.read_misses 0 # DTB read misses
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system.cpu0.itb.write_hits 0 # DTB write hits
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system.cpu0.itb.write_misses 0 # DTB write misses
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system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
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system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu0.itb.read_accesses 0 # DTB read accesses
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system.cpu0.itb.write_accesses 0 # DTB write accesses
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system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses
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system.cpu0.itb.hits 97439331 # DTB hits
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system.cpu0.itb.misses 3358 # DTB misses
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system.cpu0.itb.accesses 97442689 # DTB accesses
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system.cpu0.numCycles 5605791368 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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|
system.cpu0.committedInsts 95426926 # Number of instructions committed
|
|
system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 8000180 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 100762696 # number of integer instructions
|
|
system.cpu0.num_fp_insts 9755 # number of float instructions
|
|
system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 37873810 # number of memory refs
|
|
system.cpu0.num_load_insts 20597310 # Number of load instructions
|
|
system.cpu0.num_store_insts 17276500 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
|
|
system.cpu0.Branches 21941499 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 116882065 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
|
|
system.cpu0.dcache.tags.replacements 693477 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 769184 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 511896 # number of writebacks
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1109735 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 96331417 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1110256 # number of overall misses
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu0.l2cache.tags.replacements 252330 # number of replacements
|
|
system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use
|
|
system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks.
|
|
system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks.
|
|
system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor
|
|
system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id
|
|
system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses
|
|
system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits
|
|
system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits
|
|
system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits
|
|
system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits
|
|
system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits
|
|
system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses
|
|
system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses
|
|
system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses
|
|
system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses
|
|
system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses
|
|
system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses
|
|
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks
|
|
system.cpu0.l2cache.writebacks::total 192974 # number of writebacks
|
|
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
|
|
system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu0.toL2Bus.snoops 322019 # Total snoops (count)
|
|
system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 3358 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 12173916 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2852 # DTB read misses
|
|
system.cpu1.dtb.write_hits 7587209 # DTB write hits
|
|
system.cpu1.dtb.write_misses 506 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 12176768 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 7587715 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 19761125 # DTB hits
|
|
system.cpu1.dtb.misses 3358 # DTB misses
|
|
system.cpu1.dtb.accesses 19764483 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 1734 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors
|
|
system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 53671575 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 1734 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses
|
|
system.cpu1.itb.hits 53671575 # DTB hits
|
|
system.cpu1.itb.misses 1734 # DTB misses
|
|
system.cpu1.itb.accesses 53673309 # DTB accesses
|
|
system.cpu1.numCycles 5605320274 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 51401314 # Number of instructions committed
|
|
system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 56984241 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1792 # number of float instructions
|
|
system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 20026381 # number of memory refs
|
|
system.cpu1.num_load_insts 12289537 # Number of load instructions
|
|
system.cpu1.num_store_insts 7736844 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
|
|
system.cpu1.Branches 15217493 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 65459464 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
|
|
system.cpu1.dcache.tags.replacements 191938 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 259817 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 120855 # number of writebacks
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 523373 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 53148780 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 523885 # number of overall misses
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
|
|
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
|
system.cpu1.l2cache.tags.replacements 48604 # number of replacements
|
|
system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use
|
|
system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks.
|
|
system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks.
|
|
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor
|
|
system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id
|
|
system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses
|
|
system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits
|
|
system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits
|
|
system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits
|
|
system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits
|
|
system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits
|
|
system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses
|
|
system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses
|
|
system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses
|
|
system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses
|
|
system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses
|
|
system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses
|
|
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks
|
|
system.cpu1.l2cache.writebacks::total 32977 # number of writebacks
|
|
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu1.toL2Bus.snoops 499492 # Total snoops (count)
|
|
system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram
|
|
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 23195 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328284 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 107683 # number of replacements
|
|
system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 207875 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 4904261 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 4904261 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 225951 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 11484 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 14522 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 144063 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 27858 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 90006 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 11484 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 14522 # number of overall hits
|
|
system.l2c.overall_hits::total 144063 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 16901 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 11313 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 2365 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 1118 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 31708 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 10019 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3288 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 13307 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 752 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1179 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 136795 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 152617 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 16901 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 148108 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2365 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 184325 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 16901 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 148108 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2365 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16940 # number of overall misses
|
|
system.l2c.overall_misses::total 184325 # number of overall misses
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 78 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 44759 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 87381 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 94914 # number of writebacks
|
|
system.l2c.writebacks::total 94914 # number of writebacks
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 75966 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 75966 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 30891 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 30891 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 131104 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 196339 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 152220 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 496901 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 496901 # Request fanout histogram
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 36713 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram
|
|
|
|
---------- End Simulation Statistics ----------
|