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gem5/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
Andreas Hansson 8909843a76 stats: Update stats to reflect cache and interconnect changes 
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 05:04:20 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.054141 # Number of seconds simulated
sim_ticks 54141000000 # Number of ticks simulated
final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1893120 # Simulator instruction rate (inst/s)
host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1131265211 # Simulator tick rate (ticks/s)
host_mem_usage 433636 # Number of bytes of host memory used
host_seconds 47.86 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91053638 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory
system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 108282001 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602407 # Number of instructions committed
system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 112245 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
system.cpu.num_int_insts 72326352 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
system.cpu.num_mem_refs 27220755 # number of memory refs
system.cpu.num_load_insts 22475911 # Number of load instructions
system.cpu.num_store_insts 4744844 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 18732304 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 91054080 # Class of executed instruction
system.membus.trans_dist::ReadReq 130287905 # Transaction distribution
system.membus.trans_dist::ReadResp 130291792 # Transaction distribution
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031170 # Request fanout histogram
system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
system.membus.snoop_fanout::total 135031170 # Request fanout histogram
---------- End Simulation Statistics ----------
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