stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
This commit is contained in:
Andreas Hansson
parent
cc6523e2d6
commit
c4e91289ae
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@ -4,11 +4,11 @@ sim_seconds 0.061144 # Nu
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sim_ticks 61144411500 # Number of ticks simulated
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final_tick 61144411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 253751 # Simulator instruction rate (inst/s)
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host_op_rate 255015 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 171247115 # Simulator tick rate (ticks/s)
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host_mem_usage 451144 # Number of bytes of host memory used
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host_seconds 357.05 # Real time elapsed on the host
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host_inst_rate 269135 # Simulator instruction rate (inst/s)
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host_op_rate 270476 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 181629122 # Simulator tick rate (ticks/s)
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host_mem_usage 440052 # Number of bytes of host memory used
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host_seconds 336.64 # Real time elapsed on the host
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sim_insts 90602849 # Number of instructions simulated
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sim_ops 91054080 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 51 3.33% 52.19% # By
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system.physmem.bytesPerActivate::896-1023 28 1.83% 54.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 704 45.98% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation
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system.physmem.totQLat 71444000 # Total ticks spent queuing
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system.physmem.totMemAccLat 363456500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totQLat 71490500 # Total ticks spent queuing
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system.physmem.totMemAccLat 363503000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 4587.39 # Average queueing delay per DRAM burst
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system.physmem.avgQLat 4590.37 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 23337.39 # Average memory access latency per DRAM burst
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system.physmem.avgMemAccLat 23340.37 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 16.30 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 16.30 # Average system read bandwidth in MiByte/s
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@ -223,24 +223,32 @@ system.physmem.memoryStateTime::REF 2041520000 # Ti
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 3193563500 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.throughput 16301343 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 1030 # Transaction distribution
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system.membus.trans_dist::ReadResp 1030 # Transaction distribution
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system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
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system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 996736 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 21821000 # Layer occupancy (ticks)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 15574 # Request fanout histogram
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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system.membus.snoop_fanout::total 15574 # Request fanout histogram
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system.membus.reqLayer0.occupancy 21822000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 149563500 # Layer occupancy (ticks)
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system.membus.respLayer1.occupancy 149565000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 20748985 # Number of BP lookups
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system.cpu.branchPred.condPredicted 17053333 # Number of conditional branches predicted
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system.cpu.branchPred.lookups 20748984 # Number of BP lookups
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system.cpu.branchPred.condPredicted 17053332 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 764055 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 8969348 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 8846034 # Number of BTB hits
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@ -342,15 +350,15 @@ system.cpu.discardedOps 2027782 # Nu
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system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
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system.cpu.cpi 1.349724 # CPI: cycles per instruction
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system.cpu.ipc 0.740892 # IPC: instructions per cycle
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system.cpu.tickCycles 109176310 # Number of cycles that the object actually ticked
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system.cpu.idleCycles 13112513 # Total number of cycles that the object has spent stopped
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system.cpu.tickCycles 109176308 # Number of cycles that the object actually ticked
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system.cpu.idleCycles 13112515 # Total number of cycles that the object has spent stopped
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system.cpu.icache.tags.replacements 5 # number of replacements
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system.cpu.icache.tags.tagsinuse 690.927528 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 27773576 # Total number of references to valid blocks.
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system.cpu.icache.tags.tagsinuse 690.927522 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 27773574 # Total number of references to valid blocks.
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system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
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system.cpu.icache.tags.avg_refs 34587.267746 # Average number of references to valid blocks.
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system.cpu.icache.tags.avg_refs 34587.265255 # Average number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.tags.occ_blocks::cpu.inst 690.927528 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_blocks::cpu.inst 690.927522 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.337367 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.337367 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
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@ -358,44 +366,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 42
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system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.tag_accesses 55549561 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 55549561 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 27773576 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 27773576 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 27773576 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 27773576 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 27773576 # number of overall hits
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system.cpu.icache.overall_hits::total 27773576 # number of overall hits
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system.cpu.icache.tags.tag_accesses 55549557 # Number of tag accesses
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system.cpu.icache.tags.data_accesses 55549557 # Number of data accesses
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system.cpu.icache.ReadReq_hits::cpu.inst 27773574 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 27773574 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 27773574 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 27773574 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 27773574 # number of overall hits
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system.cpu.icache.overall_hits::total 27773574 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
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system.cpu.icache.overall_misses::total 803 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 55308998 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 55308998 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 55308998 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 55308998 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 55308998 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 55308998 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 27774379 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 27774379 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 27774379 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 27774379 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 27774379 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 27774379 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 55313498 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 55313498 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 55313498 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 55313498 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 55313498 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 55313498 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 27774377 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 27774377 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 27774377 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 27774377 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 27774377 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 27774377 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68877.955168 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 68877.955168 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 68877.955168 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 68877.955168 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 68877.955168 # average overall miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68883.559153 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 68883.559153 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 68883.559153 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 68883.559153 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 68883.559153 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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@ -410,26 +418,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803
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system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53368002 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 53368002 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53368002 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 53368002 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53368002 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 53368002 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53373502 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 53373502 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53373502 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 53373502 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53373502 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 53373502 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66460.774595 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66460.774595 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66460.774595 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 66460.774595 # average overall mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66467.623910 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66467.623910 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66467.623910 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 66467.623910 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.throughput 1982677223 # Throughput (bytes/s)
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system.cpu.toL2Bus.trans_dist::ReadReq 904183 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadResp 904183 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::Writeback 943269 # Transaction distribution
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@ -438,25 +445,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46761 # T
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843551 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 2845157 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.tot_pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.data_through_bus 121229632 # Total data (bytes)
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system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121178240 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size::total 121229632 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1894213 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 1894213 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1894213 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1890375500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1371998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1371498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1428578994 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1428579494 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10264.635484 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 10264.635477 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1831263 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.713119 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9373.658869 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976615 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 890.976609 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.286061 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.027190 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.313252 # Average percentage of cache occupancy
|
||||
|
|
@ -487,14 +508,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 15582 #
|
|||
system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 15582 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71727250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71727250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959621000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 959621000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1031348250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1031348250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1031348250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1031348250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71732750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 71732750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 959611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 959611500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1031344250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1031344250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1031344250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1031344250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 904183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 904183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 943269 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -513,14 +534,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016386
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016386 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69101.396917 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69101.396917 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65980.541804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65980.541804 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66188.438583 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.438583 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66188.438583 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69106.695568 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.695568 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65979.888614 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65979.888614 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 66188.181877 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66188.181877 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 66188.181877 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -543,14 +564,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 15574
|
|||
system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 15574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58365000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58365000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772683000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772683000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 831048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831048000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 831048000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58370500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58370500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 772672000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 772672000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 831042500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 831042500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 831042500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 831042500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.001139 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.311028 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -559,14 +580,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016377
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56665.048544 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56665.048544 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53127.268977 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53127.268977 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.243097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53361.243097 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56670.388350 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56670.388350 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53126.512651 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53126.512651 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53360.889945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53360.889945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 946045 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3618.157159 # Cycle average of tags in use
|
||||
|
|
@ -606,12 +627,12 @@ system.cpu.dcache.overall_misses::cpu.inst 988793 #
|
|||
system.cpu.dcache.overall_misses::total 988793 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 11909486494 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11909486494 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342585500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2342585500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 14252071994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14252071994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 14252071994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14252071994 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 2342568500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2342568500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 14252054994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14252054994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 14252054994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14252054994 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 22511647 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22511647 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 4734981 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -634,12 +655,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.036290
|
|||
system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 13017.297569 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.297569 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31701.113727 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31701.113727 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14413.605268 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.605268 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14413.605268 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 31700.883674 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31700.883674 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14413.588076 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 14413.588076 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14413.588076 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -668,12 +689,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 950141
|
|||
system.cpu.dcache.overall_mshr_misses::total 950141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 9958325256 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958325256 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334905750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334905750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293231006 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11293231006 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293231006 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11293231006 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1334896250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1334896250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 11293221506 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11293221506 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 11293221506 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11293221506 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.040129 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009876 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -684,12 +705,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.034872
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 11023.406823 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.406823 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.416651 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.416651 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.847475 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.847475 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28547.213490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28547.213490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 11885.837477 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11885.837477 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu
|
|||
sim_ticks 54141000000 # Number of ticks simulated
|
||||
final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1737374 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1038196846 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 439336 # Number of bytes of host memory used
|
||||
host_seconds 52.15 # Real time elapsed on the host
|
||||
host_inst_rate 2068738 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2079040 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1236208278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 428768 # Number of bytes of host memory used
|
||||
host_seconds 43.80 # Real time elapsed on the host
|
||||
sim_insts 90602407 # Number of instructions simulated
|
||||
sim_ops 91053638 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 349238802 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9978534124 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 540247816 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 130287905 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 130291792 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 4734981 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 4734981 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 510 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 510 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 135031170 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 135031170 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147041 # Nu
|
|||
sim_ticks 147041218000 # Number of ticks simulated
|
||||
final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1067718 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1733318334 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449084 # Number of bytes of host memory used
|
||||
host_seconds 84.83 # Real time elapsed on the host
|
||||
host_inst_rate 1130471 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1136089 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1835190843 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 438268 # Number of bytes of host memory used
|
||||
host_seconds 80.12 # Real time elapsed on the host
|
||||
sim_insts 90576861 # Number of instructions simulated
|
||||
sim_ops 91026990 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 251576 # In
|
|||
system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 6676767 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 981760 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15340 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15340 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks)
|
||||
|
|
@ -559,7 +567,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
|
|
@ -568,11 +575,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu
|
|||
sim_ticks 122215823500 # Number of ticks simulated
|
||||
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2362566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2362664 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1184221154 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 397240 # Number of bytes of host memory used
|
||||
host_seconds 103.20 # Real time elapsed on the host
|
||||
host_inst_rate 2069444 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2069529 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1037295392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412436 # Number of bytes of host memory used
|
||||
host_seconds 117.82 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -37,9 +37,29 @@ system.physmem.bw_write::total 749543606 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11438757576 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1397997177 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 326641931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 326641931 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 22901951 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 22901951 # Transaction distribution
|
||||
system.membus.trans_dist::SwapReq 3886 # Transaction distribution
|
||||
system.membus.trans_dist::SwapResp 3886 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 349547768 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 349547768 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 244431648 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu
|
|||
sim_ticks 361488530000 # Number of ticks simulated
|
||||
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1070091 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1070135 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1586487053 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 406976 # Number of bytes of host memory used
|
||||
host_seconds 227.85 # Real time elapsed on the host
|
||||
host_inst_rate 1379749 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2045576865 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 421936 # Number of bytes of host memory used
|
||||
host_seconds 176.72 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 155623 # In
|
|||
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2762444 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 998592 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 15603 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
|
||||
|
|
@ -463,7 +471,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
|
|
@ -472,11 +479,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1875719 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1875719 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1875719 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061857 # Nu
|
|||
sim_ticks 61857343500 # Number of ticks simulated
|
||||
final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 85967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 151374 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 33658728 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 393056 # Number of bytes of host memory used
|
||||
host_seconds 1837.78 # Real time elapsed on the host
|
||||
host_inst_rate 115241 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 202921 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45120347 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449832 # Number of bytes of host memory used
|
||||
host_seconds 1370.94 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Wr
|
|||
system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 130872750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 700329000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 131010750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4309.14 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23059.14 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -249,7 +249,6 @@ system.physmem.memoryStateTime::REF 2065440000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 31718918 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1465 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1462 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 197 # Transaction distribution
|
||||
|
|
@ -258,11 +257,20 @@ system.membus.trans_dist::ReadExResp 28998 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1962048 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 30660 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30660 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks)
|
||||
|
|
@ -574,7 +582,6 @@ system.cpu.cc_regfile_reads 107699117 # nu
|
|||
system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 4287758914 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution
|
||||
|
|
@ -583,11 +590,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 265229376 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu
|
|||
sim_ticks 168950040000 # Number of ticks simulated
|
||||
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1054637 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1857047 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1127809594 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414920 # Number of bytes of host memory used
|
||||
host_seconds 149.80 # Real time elapsed on the host
|
||||
host_inst_rate 1180838 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1262766288 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 436624 # Number of bytes of host memory used
|
||||
host_seconds 133.79 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,33 @@ system.physmem.bw_write::total 1439319677 # Wr
|
|||
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 15992825110 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2701988442 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 339915363 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365989065000 # Number of ticks simulated
|
||||
final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 596728 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1050742 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1382352440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 424660 # Number of bytes of host memory used
|
||||
host_seconds 264.76 # Real time elapsed on the host
|
||||
host_inst_rate 756908 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1753418925 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 446124 # Number of bytes of host memory used
|
||||
host_seconds 208.73 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 17487 # To
|
|||
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 5272114 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1025 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1025 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 100 # Transaction distribution
|
||||
|
|
@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 29024 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 1929536 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 30149 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30149 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
|
||||
|
|
@ -457,7 +465,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
|
||||
|
|
@ -466,11 +473,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu
|
|||
sim_ticks 279362297500 # Number of ticks simulated
|
||||
final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1833232 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1010964168 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309500 # Number of bytes of host memory used
|
||||
host_seconds 276.33 # Real time elapsed on the host
|
||||
host_inst_rate 2087081 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1150953174 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299952 # Number of bytes of host memory used
|
||||
host_seconds 242.72 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 548694828 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 773431583 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9684076374 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2705365825 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 630711790 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 632200331 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 54239306 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 54239306 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 687930749 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 687930749 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu
|
|||
sim_ticks 707539023000 # Number of ticks simulated
|
||||
final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1172742 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1643133313 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319240 # Number of bytes of host memory used
|
||||
host_seconds 430.60 # Real time elapsed on the host
|
||||
host_inst_rate 1199909 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1681197618 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309428 # Number of bytes of host memory used
|
||||
host_seconds 420.85 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 546878104 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 8679369 # To
|
|||
system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21582595 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 41855 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 41855 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 95953 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 100794 # Tr
|
|||
system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15270528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 238603 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 238603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
|
||||
|
|
@ -564,7 +572,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
||||
|
|
@ -573,11 +580,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu
|
|||
sim_ticks 885229328000 # Number of ticks simulated
|
||||
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1112999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2058060 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1191542406 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288080 # Number of bytes of host memory used
|
||||
host_seconds 742.93 # Real time elapsed on the host
|
||||
host_inst_rate 1229934 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1316729165 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308776 # Number of bytes of host memory used
|
||||
host_seconds 672.29 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,33 @@ system.physmem.bw_write::total 1120443517 # Wr
|
|||
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13357308966 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 11824281640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu
|
|||
sim_ticks 1647872849000 # Number of ticks simulated
|
||||
final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 654522 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1210285 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1304389188 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297832 # Number of bytes of host memory used
|
||||
host_seconds 1263.33 # Real time elapsed on the host
|
||||
host_inst_rate 845545 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1685075999 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318276 # Number of bytes of host memory used
|
||||
host_seconds 977.92 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 11351788 # To
|
|||
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 26154600 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 174452 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 174452 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 292286 # Transaction distribution
|
||||
|
|
@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 206691 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 43099456 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 673429 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 673429 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
|
||||
|
|
@ -459,7 +467,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
|
||||
|
|
@ -468,11 +475,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.220941 # Nu
|
|||
sim_ticks 220941341500 # Number of ticks simulated
|
||||
final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 303038 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 303038 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 167944827 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273400 # Number of bytes of host memory used
|
||||
host_seconds 1315.56 # Real time elapsed on the host
|
||||
host_inst_rate 328458 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 328458 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 182032431 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297876 # Number of bytes of host memory used
|
||||
host_seconds 1213.75 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6821 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # By
|
|||
system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52730250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 53358500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 201014750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6775.68 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25525.68 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -223,20 +223,28 @@ system.physmem.memoryStateTime::REF 7377500000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 2281148 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4737 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4737 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3138 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3138 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 504000 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7875 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7875 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7875 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9512000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 74011500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 46221231 # Number of BP lookups
|
||||
|
|
@ -290,15 +298,15 @@ system.cpu.discardedOps 4446127 # Nu
|
|||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.108407 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.902196 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 437732110 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 4150573 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 3195 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1919.708570 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708570 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
|
|
@ -321,12 +329,12 @@ system.cpu.icache.demand_misses::cpu.inst 5173 # n
|
|||
system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5173 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293560000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 293560000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 293560000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 293560000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 293560000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 293560000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses
|
||||
|
|
@ -339,12 +347,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000053
|
|||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56748.501836 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56748.501836 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56748.501836 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56748.501836 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56748.501836 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -359,26 +367,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173
|
|||
system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281592000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281592000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281592000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281592000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54434.950706 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54434.950706 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54434.950706 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54434.950706 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
||||
|
|
@ -387,25 +394,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9992 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 9992 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9992 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8570500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4427.627399 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543479 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy
|
||||
|
|
@ -435,14 +452,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 #
|
|||
system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7875 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325756750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 325756750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212895750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 212895750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 538652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 538652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 538652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 538652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -461,14 +478,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68768.577159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68768.577159 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67844.407266 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67844.407266 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68400.317460 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68400.317460 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68400.317460 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -485,14 +502,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875
|
|||
system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266376250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266376250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173100750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173100750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439477000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 439477000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439477000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 439477000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -501,22 +518,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56233.111674 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56233.111674 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55162.762906 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55162.762906 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55806.603175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55806.603175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3291.748199 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748199 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
|
|
@ -544,14 +561,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7119 # n
|
|||
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81019000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 81019000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393760000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393760000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 474779000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 474779000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 474779000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 474779000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -568,14 +585,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68893.707483 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68893.707483 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66256.099613 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66256.099613 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66691.810648 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66691.810648 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66691.810648 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -602,14 +619,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4165
|
|||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64462750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64462750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216604250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 216604250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281067000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 281067000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281067000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 281067000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -618,14 +635,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66593.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66593.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67752.345949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67752.345949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67483.073229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67483.073229 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.069652 # Nu
|
|||
sim_ticks 69651704000 # Number of ticks simulated
|
||||
final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 185769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 185769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34451530 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243176 # Number of bytes of host memory used
|
||||
host_seconds 2021.73 # Real time elapsed on the host
|
||||
host_inst_rate 258321 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 258321 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 47906543 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298148 # Number of bytes of host memory used
|
||||
host_seconds 1453.91 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4229 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 291 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1354 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 350.251108 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 208.626324 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 348.782669 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 425 31.39% 31.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 330 24.37% 55.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 151 11.15% 66.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 84 6.20% 73.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 54 3.99% 77.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 42 3.10% 80.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 39 2.88% 83.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 25 1.85% 84.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 204 15.07% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1354 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 65436750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 205274250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 66704750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8774.03 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27524.03 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,31 +216,39 @@ system.physmem.busUtilRead 0.05 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6095 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6096 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9339181.35 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.72 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 66207100500 # Time in different power states
|
||||
system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 2325700000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1115479500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 6852840 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4328 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4328 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 477312 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9424500 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7458 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7458 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 69714000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 51167476 # Number of BP lookups
|
||||
|
|
@ -288,11 +296,11 @@ system.cpu.workload.num_syscalls 215 # Nu
|
|||
system.cpu.numCycles 139303411 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 52063836 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 85692293 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
|
||||
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
|
|
@ -300,11 +308,11 @@ system.cpu.fetch.PendingTrapStallCycles 13783 # Nu
|
|||
system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 139036498 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 3.287587 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 58307253 41.94% 41.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -316,11 +324,11 @@ system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 139036498 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 45112294 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 16348159 # Number of cycles decode is blocked
|
||||
system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing
|
||||
|
|
@ -329,16 +337,16 @@ system.cpu.decode.BranchMispred 4245 # Nu
|
|||
system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 47010937 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 5663540 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 519055 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 10271568 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 3600584 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups
|
||||
|
|
@ -359,23 +367,23 @@ system.cpu.iq.iqSquashedInstsIssued 484036 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 139036498 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.926684 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23891417 17.18% 17.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 19616673 14.11% 31.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 22677490 16.31% 47.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 19609415 14.10% 75.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 14153869 10.18% 85.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 9626408 6.92% 92.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 139036498 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available
|
||||
|
|
@ -448,7 +456,7 @@ system.cpu.iq.FU_type_0::total 406915916 # Ty
|
|||
system.cpu.iq.rate 2.921076 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 625896967 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads
|
||||
|
|
@ -468,7 +476,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 381699 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 4471522 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch
|
||||
|
|
@ -492,8 +500,8 @@ system.cpu.iew.exec_stores 79416096 # Nu
|
|||
system.cpu.iew.exec_rate 2.894098 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 198000447 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 283955601 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 198000445 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back
|
||||
|
|
@ -501,23 +509,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr
|
|||
system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 133310645 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.990493 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 48555640 36.42% 36.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 18055919 13.54% 49.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 6426213 4.82% 68.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 2616134 1.96% 77.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 133310645 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -563,12 +571,12 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 542989019 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 542988978 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 884890973 # The number of ROB writes
|
||||
system.cpu.timesIdled 3471 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 266913 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction
|
||||
|
|
@ -581,7 +589,6 @@ system.cpu.fp_regfile_reads 157938395 # nu
|
|||
system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 8238478 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution
|
||||
|
|
@ -590,24 +597,34 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 573824 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6699750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 2164 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1832.364341 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364341 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
|
||||
|
|
@ -630,12 +647,12 @@ system.cpu.icache.demand_misses::cpu.inst 5678 # n
|
|||
system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5678 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 339990499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 339990499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 339990499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 339990499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 339990499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 339990499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses
|
||||
|
|
@ -648,12 +665,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000111
|
|||
system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59878.566221 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59878.566221 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59878.566221 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59878.566221 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59878.566221 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
||||
|
|
@ -674,34 +691,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4091
|
|||
system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249912250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 249912250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249912250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 249912250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249912250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 249912250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249962500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 249962500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249962500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 249962500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249962500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 249962500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61088.303593 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61088.303593 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61088.303593 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61088.303593 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61100.586654 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61100.586654 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4021.632114 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.133815 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663024 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835276 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy
|
||||
|
|
@ -738,17 +755,17 @@ system.cpu.l2cache.demand_misses::total 7458 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7458 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239520750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65288250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 304809000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231991500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 231991500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 239520750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 297279750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 536800500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 239520750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 297279750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 536800500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 536732500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 239571000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 297161500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 536732500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -773,17 +790,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.899421 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69185.658579 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75390.588915 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70427.218115 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.690096 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.690096 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71976.468222 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69185.658579 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74394.331832 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71976.468222 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -803,17 +820,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7458
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195634750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54618250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250253000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193410500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193410500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195634750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 248028750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 443663500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195634750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 248028750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 443663500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -825,25 +842,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56509.170999 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63069.572748 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57821.857671 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61792.492013 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61792.492013 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56509.170999 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62069.256757 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59488.267632 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 798 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3297.113069 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113069 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id
|
||||
|
|
@ -873,14 +890,14 @@ system.cpu.dcache.demand_misses::cpu.data 21715 # n
|
|||
system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 21715 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114614250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 114614250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125204835 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1125204835 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1239819085 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1239819085 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1239819085 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1239819085 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -899,19 +916,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000138
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62905.735456 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62905.735456 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56562.853014 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56562.853014 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57095.053419 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57095.053419 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57095.053419 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 46429 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 948 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.975738 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -933,14 +950,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4201
|
|||
system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67699250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 67699250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 236024500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 236024500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303723750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 303723750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303723750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 303723750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -949,14 +966,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67834.919840 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67834.919840 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73688.573213 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73688.573213 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72297.964770 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72297.964770 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu
|
|||
sim_ticks 199332411500 # Number of ticks simulated
|
||||
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3159999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1579999901 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261616 # Number of bytes of host memory used
|
||||
host_seconds 126.16 # Real time elapsed on the host
|
||||
host_inst_rate 2820224 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2820224 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1410112599 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 285836 # Number of bytes of host memory used
|
||||
host_seconds 141.36 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 2470028804 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13793364824 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2749464673 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 493419140 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 493419140 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 73520729 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 73520729 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 566939869 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 566939869 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1556013 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2214344764 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270340 # Number of bytes of host memory used
|
||||
host_seconds 256.21 # Real time elapsed on the host
|
||||
host_inst_rate 1606485 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2286169690 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295576 # Number of bytes of host memory used
|
||||
host_seconds 248.16 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 361550 # In
|
|||
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 809285 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 459136 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7174 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7174 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
|
||||
|
|
@ -477,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
|
|
@ -486,11 +493,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7346 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 16299 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 8474 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 8474 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 8474 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.212377 # Nu
|
|||
sim_ticks 212377413000 # Number of ticks simulated
|
||||
final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166098 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 199419 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 129195965 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326468 # Number of bytes of host memory used
|
||||
host_seconds 1643.84 # Real time elapsed on the host
|
||||
host_inst_rate 164145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 197075 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 127677508 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316656 # Number of bytes of host memory used
|
||||
host_seconds 1663.39 # Real time elapsed on the host
|
||||
sim_insts 273037856 # Number of instructions simulated
|
||||
sim_ops 327812213 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # By
|
|||
system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52122500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194303750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 52768250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6873.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25623.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -223,29 +223,37 @@ system.physmem.memoryStateTime::REF 7091500000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 2285139 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2853 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2853 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 485312 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 8812000 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 7583 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7583 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 70869000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 33146135 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 33146132 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 18038083 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 86.605827 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
|
|
@ -338,19 +346,19 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037856 # Number of instructions committed
|
||||
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 4318160 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.555663 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.642813 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 420995897 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3758929 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 36952 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1924.941242 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 73208047 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1882.487259 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941242 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
||||
|
|
@ -360,44 +368,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 33
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 146532763 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 146532763 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 73208047 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 73208047 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 73208047 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 73208047 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 73208047 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 73208047 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 73208046 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38890 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 704978746 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 704978746 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 704978746 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 704978746 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 704978746 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 704978746 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 73246937 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 73246937 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 73246937 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 73246937 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 73246937 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 73246937 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18127.506968 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18127.506968 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18127.506968 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18127.506968 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18127.506968 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38890
|
|||
system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625804254 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 625804254 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625804254 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 625804254 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625804254 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 625804254 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16091.649627 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16091.649627 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16091.649627 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16091.649627 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 13382365 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution
|
||||
|
|
@ -440,25 +447,39 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 2842112 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 59031746 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7495460 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4198.136947 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.492029 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644919 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy
|
||||
|
|
@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7626 #
|
|||
system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 328392750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194194500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 194194500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 522587250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 522587250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 522587250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 522587250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.168448 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.168448 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68066.771819 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68066.771819 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68527.045633 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68527.045633 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68527.045633 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583
|
|||
system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266719500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266719500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158382000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158382000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425101500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 425101500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425101500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 425101500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56388.900634 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56388.900634 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55514.195584 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55514.195584 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56059.804827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56059.804827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1353 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3085.890933 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890933 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
|
|
@ -608,14 +629,14 @@ system.cpu.dcache.demand_misses::cpu.inst 7291 # n
|
|||
system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7291 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127204208 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 127204208 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358851000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 358851000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 486055208 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 486055208 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 486055208 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 486055208 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -636,14 +657,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61600.100726 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61600.100726 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68666.475316 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68666.475316 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66665.095049 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66665.095049 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66665.095049 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -670,14 +691,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 4510
|
|||
system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100713040 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 100713040 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197262500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 197262500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297975540 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 297975540 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297975540 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 297975540 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -686,14 +707,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61372.967703 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61372.967703 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68756.535378 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68756.535378 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66069.964523 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66069.964523 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu
|
|||
sim_ticks 201717313500 # Number of ticks simulated
|
||||
final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1169681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864148101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314684 # Number of bytes of host memory used
|
||||
host_seconds 233.43 # Real time elapsed on the host
|
||||
host_inst_rate 1306299 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 965080142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305108 # Number of bytes of host memory used
|
||||
host_seconds 209.02 # Real time elapsed on the host
|
||||
sim_insts 273037594 # Number of instructions simulated
|
||||
sim_ops 327811949 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 1983209850 # Wr
|
|||
system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11280132734 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2275398071 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 434895827 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 434906722 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 517024351 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 517024351 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.517235 # Nu
|
|||
sim_ticks 517235411000 # Number of ticks simulated
|
||||
final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 749544 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 324416 # Number of bytes of host memory used
|
||||
host_seconds 363.87 # Real time elapsed on the host
|
||||
host_inst_rate 795879 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 955482 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1509341441 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314596 # Number of bytes of host memory used
|
||||
host_seconds 342.69 # Real time elapsed on the host
|
||||
sim_insts 272739285 # Number of instructions simulated
|
||||
sim_ops 327433743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 322824 # In
|
|||
system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 845356 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 437248 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 6833 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6833 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
|
||||
|
|
@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
|
|
@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31206 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 41160 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.555548 # Number of seconds simulated
|
||||
sim_ticks 555548307000 # Number of ticks simulated
|
||||
final_tick 555548307000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.555533 # Number of seconds simulated
|
||||
sim_ticks 555532734000 # Number of ticks simulated
|
||||
final_tick 555532734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 201077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 201077 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 120272803 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246132 # Number of bytes of host memory used
|
||||
host_seconds 4619.07 # Real time elapsed on the host
|
||||
host_inst_rate 337976 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 337976 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 202152446 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300884 # Number of bytes of host memory used
|
||||
host_seconds 2748.09 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -23,43 +23,43 @@ system.physmem.num_reads::cpu.inst 291518 # Nu
|
|||
system.physmem.num_reads::total 291518 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 33583312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33583312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 336043 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 336043 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7681982 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7681982 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7681982 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 33583312 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41265294 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 33584253 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 33584253 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 336052 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 336052 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7682197 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7682197 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7682197 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 33584253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41266450 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291518 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66683 # Number of write requests accepted
|
||||
system.physmem.readBursts 291518 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18639168 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 17984 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 17088 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18657152 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 281 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 267 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 17934 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18286 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 17939 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18284 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18304 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18252 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18169 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18242 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18316 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 18295 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18254 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18163 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18248 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18324 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 18299 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18226 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18227 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18210 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18385 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18260 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18048 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18226 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18216 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18389 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18256 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18039 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 17980 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18103 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18104 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
|
||||
|
|
@ -69,7 +69,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe
|
|||
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4185 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4190 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
|
||||
|
|
@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 555548231500 # Total gap between requests
|
||||
system.physmem.totGap 555532658500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 290743 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 468 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 290760 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -140,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 970 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4048 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 981 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4046 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 104858 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 218.415915 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 140.780585 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 268.040689 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 39691 37.85% 37.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43831 41.80% 79.65% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8352 7.97% 87.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1265 1.21% 88.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 732 0.70% 89.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 905 0.86% 90.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1060 1.01% 91.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 884 0.84% 92.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8138 7.76% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 104858 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 70.322621 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.136998 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 770.555291 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.85% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.88% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 105079 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 217.968119 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 139.907625 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 270.030152 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 40113 38.17% 38.17% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 44071 41.94% 80.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8455 8.05% 88.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 717 0.68% 88.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 543 0.52% 89.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 672 0.64% 90.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1241 1.18% 91.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1153 1.10% 92.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8114 7.72% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 105079 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 71.423096 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.196398 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 785.521839 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::14336-16383 3 0.07% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::16384-18431 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.479852 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.458537 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.855483 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3076 76.04% 76.04% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 966 23.88% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2434432250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7895126000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1456185000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8358.94 # Average queueing delay per DRAM burst
|
||||
system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.485163 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.463667 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.859123 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3065 75.79% 75.79% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 975 24.11% 99.90% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2419619750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7880576000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8307.68 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27108.94 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27057.68 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 33.55 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.68 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 33.58 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -236,19 +236,18 @@ system.physmem.busUtil 0.32 # Da
|
|||
system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 202612 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 50417 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.57 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1550939.92 # Average gap between requests
|
||||
system.physmem.pageHitRate 70.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 275426566250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 18550740000 # Time in different power states
|
||||
system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 202343 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 50484 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.47 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1550896.45 # Average gap between requests
|
||||
system.physmem.pageHitRate 70.64 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 275459224750 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 18550220000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 261564123750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 261516412250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 41265294 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 224874 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224874 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
|
|
@ -256,23 +255,32 @@ system.membus.trans_dist::ReadExReq 66644 # Tr
|
|||
system.membus.trans_dist::ReadExResp 66644 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649719 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 649719 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22924864 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 954576500 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22924864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22924864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 358201 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 358201 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 358201 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 954482500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2724054750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2723745500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 125108663 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 80505378 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condPredicted 80505376 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 12157226 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 103330872 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 82874855 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 103330871 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 82874854 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 80.203383 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 18690214 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.usedRAS 18690215 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 9442 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -290,10 +298,10 @@ system.cpu.dtb.data_hits 335842628 # DT
|
|||
system.cpu.dtb.data_misses 205618 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 336048246 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 315070348 # ITB hits
|
||||
system.cpu.itb.fetch_hits 315070347 # ITB hits
|
||||
system.cpu.itb.fetch_misses 120 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 315070468 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 315070467 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -307,24 +315,24 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 1111096614 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1111065468 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928789150 # Number of instructions committed
|
||||
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 23870770 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 23870771 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.196285 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.835921 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.196252 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.835945 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1052548202 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 58548412 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.idleCycles 58517266 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 10608 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1686.445112 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 315057997 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1686.446779 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 315057996 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25510.768988 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 25510.768907 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1686.445112 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1686.446779 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.823460 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.823460 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id
|
||||
|
|
@ -334,44 +342,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 630153046 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 630153046 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 315057997 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 315057997 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 315057997 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 315057997 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 315057997 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 315057997 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 630153044 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 630153044 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 315057996 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 315057996 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 315057996 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 315057996 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 315057996 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 315057996 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 12351 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 334622500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 334622500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 334622500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 334622500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 334622500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 334622500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 315070348 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 315070348 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 315070348 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 315070348 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 315070348 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 315070348 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 334498250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 334498250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 334498250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 334498250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 334498250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 334498250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 315070347 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 315070347 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 315070347 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 315070347 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 315070347 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 315070347 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27092.745527 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27092.745527 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27092.745527 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27092.745527 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27092.745527 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27082.685613 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27082.685613 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27082.685613 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27082.685613 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27082.685613 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -386,26 +394,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12351
|
|||
system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308669500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 308669500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308669500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 308669500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308669500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 308669500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 308545750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 308545750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 308545750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 308545750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 308545750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 308545750 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24991.458182 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24991.458182 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24991.458182 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24991.458182 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24981.438750 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24981.438750 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24981.438750 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24981.438750 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 101892158 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723971 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution
|
||||
|
|
@ -414,28 +421,38 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69010 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652749 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1677450 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56606016 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56606016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 884470 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 884470 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 884470 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533724000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 19151500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 19151250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1222065750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1221989250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 258739 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32601.591220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32601.629306 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 523854 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291475 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.797252 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2866.071604 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.519616 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087466 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994922 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2865.774027 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.855280 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087456 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907466 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994923 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
||||
|
|
@ -463,14 +480,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291519 #
|
|||
system.cpu.l2cache.demand_misses::total 291519 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 291519 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291519 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15957253750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15957253750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4332290500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4332290500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20289544250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20289544250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20289544250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20289544250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15924584250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15924584250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4349858250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4349858250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20274442500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20274442500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20274442500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20274442500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 723971 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 723971 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -489,14 +506,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367624
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.367624 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.367624 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70960.550306 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70960.550306 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65006.459696 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.459696 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69599.388891 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69599.388891 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69599.388891 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70815.271818 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70815.271818 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65270.065572 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65270.065572 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69547.585235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69547.585235 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69547.585235 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -515,14 +532,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291519
|
|||
system.cpu.l2cache.demand_mshr_misses::total 291519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 291519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13140394750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13140394750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3498793500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3498793500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16639188250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16639188250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16639188250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16639188250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13108086750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13108086750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3516385750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3516385750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16624472500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16624472500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16624472500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16624472500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310613 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965715 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -531,22 +548,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367624
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.367624 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.367624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58434.217899 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58434.217899 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52499.752416 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52499.752416 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.542973 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57077.542973 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58290.546971 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58290.546971 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52763.725917 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.725917 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57027.063416 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57027.063416 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 776534 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.879870 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 322859768 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4092.879782 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 322859767 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780630 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 413.588727 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 413.588726 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 839965250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879870 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.879782 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.999238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -556,16 +573,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 950
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1629 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 648198338 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 648198338 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 224695721 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 224695721 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 648198336 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 648198336 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 224695720 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 224695720 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 322859768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 322859768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 322859768 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 322859768 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 322859767 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 322859767 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 322859767 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 322859767 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 711933 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711933 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 137153 # number of WriteReq misses
|
||||
|
|
@ -574,22 +591,22 @@ system.cpu.dcache.demand_misses::cpu.inst 849086 # n
|
|||
system.cpu.dcache.demand_misses::total 849086 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 849086 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 849086 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22864552750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 22864552750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8987445000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8987445000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 31851997750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31851997750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 31851997750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31851997750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 225407654 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 225407654 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 22831828750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 22831828750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9022635000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9022635000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 31854463750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31854463750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 31854463750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31854463750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 225407653 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 225407653 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 323708854 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 323708854 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 323708854 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 323708854 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 323708853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 323708853 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 323708853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 323708853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003158 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001395 # miss rate for WriteReq accesses
|
||||
|
|
@ -598,14 +615,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002623
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.002623 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32116.158051 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32116.158051 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65528.606738 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65528.606738 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37513.276335 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37513.276335 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37513.276335 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32070.193052 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 32070.193052 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65785.181513 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65785.181513 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37516.180634 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 37516.180634 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37516.180634 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -632,14 +649,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780630
|
|||
system.cpu.dcache.demand_mshr_misses::total 780630 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 780630 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780630 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21363533750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21363533750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4424989000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4424989000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25788522750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25788522750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25788522750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25788522750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21330988000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21330988000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4442556750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4442556750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 25773544750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 25773544750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 25773544750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 25773544750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003157 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -648,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002412
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002412 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002412 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002412 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30020.985568 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.985568 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64120.982466 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64120.982466 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33035.526114 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33035.526114 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 29975.250836 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29975.250836 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64375.550645 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64375.550645 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33016.339047 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33016.339047 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu
|
|||
sim_ticks 464394627000 # Number of ticks simulated
|
||||
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1843860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 922130037 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234352 # Number of bytes of host memory used
|
||||
host_seconds 503.61 # Real time elapsed on the host
|
||||
host_inst_rate 2843750 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1422183537 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289848 # Number of bytes of host memory used
|
||||
host_seconds 326.54 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 1588466830 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13156831461 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 6109961839 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 98301200 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 98301200 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.286250 # Nu
|
|||
sim_ticks 1286249820000 # Number of ticks simulated
|
||||
final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 839019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 839019 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1162182391 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244120 # Number of bytes of host memory used
|
||||
host_seconds 1106.75 # Real time elapsed on the host
|
||||
host_inst_rate 1681245 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2328806930 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298588 # Number of bytes of host memory used
|
||||
host_seconds 552.32 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To
|
|||
system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 17781280 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66648 # Tr
|
|||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22871168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 357362 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 357362 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks)
|
||||
|
|
@ -486,7 +494,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
|
||||
|
|
@ -495,11 +502,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.537826 # Nu
|
|||
sim_ticks 537826498500 # Number of ticks simulated
|
||||
final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 114564 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 141043 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 96175687 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263048 # Number of bytes of host memory used
|
||||
host_seconds 5592.13 # Real time elapsed on the host
|
||||
host_inst_rate 160425 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 197504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 134676016 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315984 # Number of bytes of host memory used
|
||||
host_seconds 3993.48 # Real time elapsed on the host
|
||||
sim_insts 640655084 # Number of instructions simulated
|
||||
sim_ops 788730743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,30 +36,30 @@ system.physmem.readReqs 290531 # Nu
|
|||
system.physmem.writeReqs 66098 # Number of write requests accepted
|
||||
system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 19200 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 300 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 18291 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18140 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18223 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18187 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18258 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18313 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18090 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17910 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 17943 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 17966 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18023 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18118 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18159 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18277 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18081 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18183 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18268 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18315 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18099 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17920 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 17939 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 17964 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18020 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18110 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18148 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18270 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18079 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18262 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4174 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4102 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4137 # Per bank write bursts
|
||||
|
|
@ -67,13 +67,13 @@ system.physmem.perBankWrBursts::3 4147 # Pe
|
|||
system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 4225 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 4171 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4093 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4093 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4091 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
|
|
@ -93,7 +93,7 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 289832 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -140,8 +140,8 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 983 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see
|
||||
|
|
@ -149,15 +149,15 @@ system.physmem.wrQLenPdf::20 4008 # Wh
|
|||
system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -189,44 +189,44 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 111650 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 204.222194 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 132.352958 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 255.940958 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 47308 42.37% 42.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43452 38.92% 81.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 8609 7.71% 89.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 837 0.75% 89.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 1286 1.15% 90.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1285 1.15% 92.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 530 0.47% 92.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 473 0.42% 92.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111650 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 36.062915 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 507.683026 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 3341298000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst
|
||||
system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.489643 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3025 75.49% 75.49% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 3 0.07% 75.57% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 978 24.41% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 3341982750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8783814000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11514.91 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30264.91 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -236,19 +236,18 @@ system.physmem.busUtil 0.33 # Da
|
|||
system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 194846 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 49995 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes
|
||||
system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 194589 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 50052 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 67.05 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.72 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1508083.78 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states
|
||||
system.physmem.pageHitRate 68.66 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 253474796750 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 17958980000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 266386143250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 42437954 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 224439 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224439 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
|
|
@ -256,13 +255,22 @@ system.membus.trans_dist::ReadExReq 66092 # Tr
|
|||
system.membus.trans_dist::ReadExResp 66092 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22824256 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 356629 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 356629 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 356629 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 974401000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2738560500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 154837020 # Number of BP lookups
|
||||
|
|
@ -368,17 +376,17 @@ system.cpu.discardedOps 25219021 # Nu
|
|||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.678989 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.595596 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 1020176456 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 55476541 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 23597 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1711.183580 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1711.183580 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.835539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.835539 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
||||
|
|
@ -398,12 +406,12 @@ system.cpu.icache.demand_misses::cpu.inst 25348 # n
|
|||
system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 25348 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 480691746 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 480691746 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 480691746 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 480691746 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 480691746 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 480691746 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses
|
||||
|
|
@ -416,12 +424,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000087
|
|||
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18963.695203 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18963.695203 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18963.695203 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18963.695203 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18963.695203 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -436,26 +444,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25348
|
|||
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428895254 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 428895254 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428895254 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 428895254 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428895254 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 428895254 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16920.279864 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16920.279864 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16920.279864 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 16920.279864 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution
|
||||
|
|
@ -464,28 +471,42 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 899188 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 899188 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 899188 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 38571746 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1224928725 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 257750 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32583.011088 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2866.114553 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.896535 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.087467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906888 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994355 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
|
||||
|
|
@ -513,14 +534,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 290561 #
|
|||
system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290561 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16739408750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 16739408750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4422117750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4422117750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 21161526500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21161526500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 21161526500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21161526500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -539,14 +560,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74573.365364 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74573.365364 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66908.517672 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66908.517672 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 72829.892862 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72829.892862 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 72829.892862 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -571,14 +592,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532
|
|||
system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13904175250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13904175250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3593710250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3593710250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497885500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17497885500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497885500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17497885500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -587,14 +608,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61950.522411 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61950.522411 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54374.360740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54374.360740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60227.050721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60227.050721 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 778324 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use
|
||||
|
|
@ -634,14 +655,14 @@ system.cpu.dcache.demand_misses::cpu.inst 851434 # n
|
|||
system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 851434 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23700601220 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 23700601220 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9183787250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9183787250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 32884388470 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 32884388470 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 32884388470 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 32884388470 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -662,14 +683,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33201.094376 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 33201.094376 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66750.401573 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66750.401573 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 38622.357658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.357658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 38622.357658 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -696,14 +717,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 782420
|
|||
system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22188801525 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22188801525 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4523752250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4523752250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26712553775 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26712553775 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26712553775 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26712553775 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -712,14 +733,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.105558 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31116.105558 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65256.152359 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65256.152359 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34140.939361 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34140.939361 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu
|
|||
sim_ticks 395726778000 # Number of ticks simulated
|
||||
final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 935276 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 577711928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250216 # Number of bytes of host memory used
|
||||
host_seconds 684.99 # Real time elapsed on the host
|
||||
host_inst_rate 1695212 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2087030 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1047118075 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304696 # Number of bytes of host memory used
|
||||
host_seconds 377.92 # Real time elapsed on the host
|
||||
sim_insts 640654410 # Number of instructions simulated
|
||||
sim_ops 788730069 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 1322421029 # Wr
|
|||
system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10718373779 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 4241547521 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 893703777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 893709516 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755796 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 2045340704 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1022670352 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.043695 # Nu
|
|||
sim_ticks 1043695084000 # Number of ticks simulated
|
||||
final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 520727 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 639745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 850028397 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259968 # Number of bytes of host memory used
|
||||
host_seconds 1227.84 # Real time elapsed on the host
|
||||
host_inst_rate 974812 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1197616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1591272225 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314196 # Number of bytes of host memory used
|
||||
host_seconds 655.89 # Real time elapsed on the host
|
||||
sim_insts 639366786 # Number of instructions simulated
|
||||
sim_ops 785501034 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 4053168 # To
|
|||
system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21818480 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 223619 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 223619 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 66093 # Tr
|
|||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22771840 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 355811 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 355811 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 355811 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
|
||||
|
|
@ -569,7 +577,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
|
||||
|
|
@ -578,11 +585,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,84 +1,84 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.058327 # Number of seconds simulated
|
||||
sim_ticks 58326668000 # Number of ticks simulated
|
||||
final_tick 58326668000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.058385 # Number of seconds simulated
|
||||
sim_ticks 58384546000 # Number of ticks simulated
|
||||
final_tick 58384546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 319236 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 319236 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 210542764 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275532 # Number of bytes of host memory used
|
||||
host_seconds 277.03 # Real time elapsed on the host
|
||||
host_inst_rate 341517 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 341516 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 225460414 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300016 # Number of bytes of host memory used
|
||||
host_seconds 258.96 # Real time elapsed on the host
|
||||
sim_insts 88438073 # Number of instructions simulated
|
||||
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 10663104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 10663104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 515520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 515520 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 166611 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 166611 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 182816958 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 182816958 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 8838496 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 8838496 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 125141248 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 125141248 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 125141248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 182816958 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 307958205 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 182635727 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 182635727 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 8826445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 8826445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 125017192 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 125017192 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 125017192 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 182635727 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 307652919 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 166611 # Number of read requests accepted
|
||||
system.physmem.writeReqs 114048 # Number of write requests accepted
|
||||
system.physmem.readBursts 166611 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadDRAM 10662592 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 7297152 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 10663104 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 10470 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10514 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 10468 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10513 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 10311 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 10091 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 10432 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 10090 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 10431 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 10426 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 9845 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 10300 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 9846 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 10302 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 10593 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 10643 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 10596 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 10595 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 10255 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 10302 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 10651 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 10528 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 10648 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 10649 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 7087 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 7261 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 6999 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 7126 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 7177 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 7178 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 6771 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 7084 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 7221 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 7079 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 7222 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 6940 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 7095 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 7097 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 6991 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6965 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 6967 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 7289 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 7284 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 58326641500 # Total gap between requests
|
||||
system.physmem.totGap 58384519500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -93,9 +93,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 114048 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 164954 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1625 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 164957 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1618 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -140,29 +140,29 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 730 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 752 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 6989 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 7028 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 7025 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 7044 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 7045 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 7061 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 7078 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7102 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 7119 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 7114 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 7066 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 727 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 754 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 6184 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 6978 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 7021 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 7028 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 7031 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 7040 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 7069 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 7068 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 7078 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 7206 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 7162 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 7083 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 7403 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 7126 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
||||
|
|
@ -189,70 +189,68 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 54563 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 329.133809 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 195.314569 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.108035 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 19364 35.49% 35.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 11887 21.79% 57.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5658 10.37% 67.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3635 6.66% 74.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2734 5.01% 79.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2059 3.77% 83.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1592 2.92% 86.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1526 2.80% 88.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6108 11.19% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 54563 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 54365 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 330.333707 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 195.729973 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.976327 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 19356 35.60% 35.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 11696 21.51% 57.12% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5632 10.36% 67.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3623 6.66% 74.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2688 4.94% 79.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2044 3.76% 82.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1686 3.10% 85.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1497 2.75% 88.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6143 11.30% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 54365 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 23.733438 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 348.155819 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 23.733295 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 348.126500 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 7019 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.244052 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.228462 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.746507 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 6270 89.33% 89.33% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 11 0.16% 89.49% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 572 8.15% 97.63% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 129 1.84% 99.47% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 27 0.38% 99.86% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 6 0.09% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 1 0.01% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.244194 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.228515 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.751123 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 6265 89.26% 89.26% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 18 0.26% 89.51% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 572 8.15% 97.66% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 131 1.87% 99.53% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 24 0.34% 99.87% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 4 0.06% 99.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 7019 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1962392500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 5086236250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11778.71 # Average queueing delay per DRAM burst
|
||||
system.physmem.totQLat 2006026500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 5129832750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 833015000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 12040.76 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30528.71 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 182.81 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 182.82 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 125.14 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 30790.76 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 182.63 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 124.98 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 182.64 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 125.02 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 2.41 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 2.40 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 144808 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 81240 # Number of row buffer hits during writes
|
||||
system.physmem.avgWrQLen 23.87 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 144815 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 81433 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 86.92 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 207820.31 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 31774168500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1947400000 # Time in different power states
|
||||
system.physmem.writeRowHitRate 71.40 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 208026.54 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 31935315750 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1949480000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 24597717750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 24496780500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 307958205 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 35730 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 35730 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 114048 # Transaction distribution
|
||||
|
|
@ -260,44 +258,53 @@ system.membus.trans_dist::ReadExReq 130881 # Tr
|
|||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447270 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 447270 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17962176 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1302233000 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 280659 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 280659 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 280659 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1302108500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1600678750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1600532000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 14594840 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9449166 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 378473 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 10265774 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6368296 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 14593516 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9448617 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 379109 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 10302575 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6369350 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 62.034251 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1700711 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 73330 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.BTBHitPct 61.822894 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1700742 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 73233 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20553993 # DTB read hits
|
||||
system.cpu.dtb.read_misses 96885 # DTB read misses
|
||||
system.cpu.dtb.read_hits 20554145 # DTB read hits
|
||||
system.cpu.dtb.read_misses 96857 # DTB read misses
|
||||
system.cpu.dtb.read_acv 9 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20650878 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14665827 # DTB write hits
|
||||
system.cpu.dtb.write_misses 9394 # DTB write misses
|
||||
system.cpu.dtb.read_accesses 20651002 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 14666071 # DTB write hits
|
||||
system.cpu.dtb.write_misses 9396 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 14675221 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35219820 # DTB hits
|
||||
system.cpu.dtb.data_misses 106279 # DTB misses
|
||||
system.cpu.dtb.write_accesses 14675467 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 35220216 # DTB hits
|
||||
system.cpu.dtb.data_misses 106253 # DTB misses
|
||||
system.cpu.dtb.data_acv 9 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 35326099 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25536643 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5175 # ITB misses
|
||||
system.cpu.dtb.data_accesses 35326469 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 25540027 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5176 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 25541818 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 25545203 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -311,70 +318,70 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
||||
system.cpu.numCycles 116653336 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 116769092 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 88438073 # Number of instructions committed
|
||||
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1184863 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1185538 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.319040 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.758127 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 90780036 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 25873300 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 152673 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1933.703122 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25381921 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 154721 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 164.049618 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 41483619250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1933.703122 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.944191 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.944191 # Average percentage of cache occupancy
|
||||
system.cpu.cpi 1.320349 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.757376 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 90792552 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 25976540 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 153164 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1933.730829 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 25384814 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 155212 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 163.549300 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 41528149250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1933.730829 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.944205 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.944205 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 51228007 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 51228007 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25381921 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25381921 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25381921 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25381921 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25381921 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25381921 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 154722 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 154722 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 154722 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 154722 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 154722 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 154722 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2515300997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2515300997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2515300997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2515300997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2515300997 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2515300997 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25536643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25536643 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25536643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25536643 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25536643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25536643 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006059 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.006059 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.006059 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.006059 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.006059 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.006059 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16256.905915 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16256.905915 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16256.905915 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16256.905915 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16256.905915 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 51235266 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 51235266 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 25384814 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 25384814 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 25384814 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 25384814 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 25384814 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 25384814 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 155213 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 155213 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 155213 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 155213 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 155213 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 155213 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2516319497 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 2516319497 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 2516319497 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 2516319497 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 2516319497 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 2516319497 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 25540027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 25540027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 25540027 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 25540027 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 25540027 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 25540027 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006077 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.006077 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.006077 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.006077 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.006077 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.006077 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16212.040854 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16212.040854 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16212.040854 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16212.040854 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16212.040854 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -383,81 +390,90 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 154722 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 154722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 154722 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 154722 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 154722 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202760003 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2202760003 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202760003 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2202760003 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202760003 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2202760003 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006059 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006059 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006059 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006059 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14236.889408 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14236.889408 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14236.889408 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14236.889408 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155213 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 155213 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 155213 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 155213 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 155213 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 155213 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2202806503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 2202806503 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2202806503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 2202806503 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2202806503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 2202806503 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006077 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006077 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006077 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006077 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14192.152094 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14192.152094 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14192.152094 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14192.152094 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 579498078 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 216032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 216031 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168534 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309443 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578280 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 887723 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9902144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 33800192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 33800192 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 432598500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 216522 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 216521 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168531 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 143561 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 143561 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310425 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578271 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 888696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9933568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 33831232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 528614 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 528614 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 528614 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 432838000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 233630997 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 234362497 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 343195750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 343210750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 132688 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30472.596016 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 219541 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 30473.454944 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 220028 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.332465 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.335421 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26246.298923 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.297093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.800973 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128976 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.929950 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26247.246790 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4226.208154 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.801002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128974 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.929976 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32075 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11966 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18841 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1029 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11968 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18838 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978851 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4533358 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4533358 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 180301 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 180301 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168534 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168534 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 12682 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12682 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 192983 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 192983 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 192983 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 192983 # number of overall hits
|
||||
system.cpu.l2cache.tags.tag_accesses 4537236 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4537236 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 180791 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 180791 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 168531 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 168531 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.inst 12680 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 12680 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 193471 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 193471 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 193471 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 193471 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 35731 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 35731 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses
|
||||
|
|
@ -466,40 +482,40 @@ system.cpu.l2cache.demand_misses::cpu.inst 166612 #
|
|||
system.cpu.l2cache.demand_misses::total 166612 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 166612 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 166612 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608847500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2608847500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9666752250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 9666752250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12275599750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12275599750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12275599750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12275599750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 216032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 216032 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168534 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168534 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143563 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143563 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 359595 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 359595 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 359595 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 359595 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165397 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.165397 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911662 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911662 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463332 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.463332 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463332 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.463332 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73013.559654 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73013.559654 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73859.095285 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73859.095285 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73677.764807 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73677.764807 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73677.764807 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2608794250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2608794250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9709899750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 9709899750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12318694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12318694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12318694000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12318694000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 216522 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 216522 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 168531 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 168531 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143561 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 143561 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 360083 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 360083 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 360083 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 360083 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165022 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.165022 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911675 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911675 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462704 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.462704 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462704 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.462704 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73012.069352 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73012.069352 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 74188.764985 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74188.764985 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73936.415144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73936.415144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73936.415144 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -518,95 +534,95 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 166612
|
|||
system.cpu.l2cache.demand_mshr_misses::total 166612 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 166612 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 166612 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155704000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155704000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7981949750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7981949750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10137653750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10137653750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10137653750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10137653750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165397 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165397 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911662 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911662 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.463332 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463332 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.463332 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60331.476869 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60331.476869 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60986.313903 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60986.313903 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60845.879949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60845.879949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2155637750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2155637750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 8025242250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8025242250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10180880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10180880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10180880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10180880000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911675 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911675 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.462704 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462704 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.462704 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.622737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.622737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61317.091480 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61317.091480 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61105.322546 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61105.322546 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 200777 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4071.421073 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34597319 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204873 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 168.872028 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.replacements 200774 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4071.445438 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 34597334 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 204870 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 168.874574 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 644670250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.421073 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.445438 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.994005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.994005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 754 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 755 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3288 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 70138517 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 70138517 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 20264045 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20264045 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 14333274 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14333274 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 34597319 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34597319 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 34597319 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34597319 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 89400 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 89400 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 280103 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 280103 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 369503 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 369503 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 369503 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 369503 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4413515000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4413515000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20003600250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20003600250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 24417115250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24417115250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 24417115250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24417115250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20353445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20353445 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.tags.tag_accesses 70138572 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 70138572 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 20264067 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20264067 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 14333267 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 14333267 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 34597334 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 34597334 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 34597334 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 34597334 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 89407 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 89407 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 280110 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 280110 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 369517 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 369517 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 369517 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 369517 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4423552750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4423552750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20095524250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20095524250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 24519077000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24519077000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 24519077000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24519077000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20353474 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20353474 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 34966822 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34966822 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 34966822 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34966822 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 34966851 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 34966851 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 34966851 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 34966851 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.010567 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010567 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.010567 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010567 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49368.176734 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49368.176734 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71415.158888 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 71415.158888 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66080.966190 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66080.966190 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66080.966190 # average overall miss latency
|
||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.010568 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.010568 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.010568 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49476.581811 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49476.581811 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 71741.545286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 71741.545286 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66354.395062 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66354.395062 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66354.395062 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -615,32 +631,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 168534 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168534 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28089 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 28089 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136541 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 164630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 164630 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 164630 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 164630 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61311 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 61311 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143562 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143562 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 204873 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204873 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 204873 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204873 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2425671500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2425671500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937173250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937173250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12362844750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12362844750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12362844750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12362844750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.writebacks::writebacks 168531 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 168531 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28097 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 28097 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 136550 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 164647 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 164647 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 164647 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 164647 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143560 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 143560 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 204870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 204870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 204870 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204870 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2430963250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2430963250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9980296000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9980296000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12411259250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12411259250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12411259250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12411259250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -649,14 +665,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39563.398085 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39563.398085 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69218.687745 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69218.687745 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60343.943565 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60343.943565 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.354755 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39650.354755 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69520.033435 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69520.033435 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60581.145360 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60581.145360 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
|
|||
sim_ticks 44221003000 # Number of ticks simulated
|
||||
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3162077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1582850501 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263736 # Number of bytes of host memory used
|
||||
host_seconds 27.94 # Real time elapsed on the host
|
||||
host_inst_rate 2813944 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1408584494 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287952 # Number of bytes of host memory used
|
||||
host_seconds 31.39 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 2072610067 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12937468537 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 572107835 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 108714711 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 108714711 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14613377 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 14613377 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 123328088 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
|||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1560477 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2360564466 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272464 # Number of bytes of host memory used
|
||||
host_seconds 56.61 # Real time elapsed on the host
|
||||
host_inst_rate 1471745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2226337698 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297712 # Number of bytes of host memory used
|
||||
host_seconds 60.02 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 54587966 # To
|
|||
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 133682617 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 34272 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 34272 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 113982 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 130881 # Tr
|
|||
system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17864640 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 279135 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 279135 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
|
||||
|
|
@ -484,7 +492,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
|
||||
|
|
@ -493,11 +500,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.056337 # Number of seconds simulated
|
||||
sim_ticks 56337328500 # Number of ticks simulated
|
||||
final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.056374 # Number of seconds simulated
|
||||
sim_ticks 56374399500 # Number of ticks simulated
|
||||
final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 184341 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 235745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 146446418 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326872 # Number of bytes of host memory used
|
||||
host_seconds 384.70 # Real time elapsed on the host
|
||||
host_inst_rate 197105 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 252068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 156689619 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315764 # Number of bytes of host memory used
|
||||
host_seconds 359.78 # Real time elapsed on the host
|
||||
sim_insts 70915127 # Number of instructions simulated
|
||||
sim_ops 90690083 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -23,22 +23,22 @@ system.physmem.num_reads::cpu.inst 128862 # Nu
|
|||
system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 128862 # Number of read requests accepted
|
||||
system.physmem.writeReqs 83951 # Number of write requests accepted
|
||||
system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
|
|
@ -60,13 +60,13 @@ system.physmem.perBankRdBursts::12 7881 # Pe
|
|||
system.physmem.perBankRdBursts::13 7876 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 8004 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 5198 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
|
||||
|
|
@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 5451 # Pe
|
|||
system.physmem.perBankWrBursts::15 5224 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 56337297000 # Total gap between requests
|
||||
system.physmem.totGap 56374368000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 83951 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -140,26 +140,26 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
|
|
@ -189,69 +189,68 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1494390000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1533288750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.89 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 112251 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 62167 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 264726.76 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1881100000 # Time in different power states
|
||||
system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 112227 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 264900.96 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 241758570 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 26583 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 26583 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 83951 # Transaction distribution
|
||||
|
|
@ -259,22 +258,31 @@ system.membus.trans_dist::ReadExReq 102279 # Tr
|
|||
system.membus.trans_dist::ReadExResp 102279 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13620032 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 212813 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 212813 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 14808792 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 14808790 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
|
|
@ -362,70 +370,70 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 112674657 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 112748799 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70915127 # Number of instructions committed
|
||||
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.588866 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.629380 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.589912 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.628966 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 42434 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24948252 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24948244 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 44477 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -440,26 +448,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 44477
|
|||
system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution
|
||||
|
|
@ -468,33 +475,47 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 95725 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses
|
||||
|
|
@ -517,14 +538,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 128934 #
|
|||
system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128934 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -543,14 +564,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -575,14 +596,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863
|
|||
system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -591,87 +612,87 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 156424 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42632380 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42632417 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 262082 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 262053 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -684,12 +705,12 @@ system.cpu.dcache.writebacks::writebacks 128423 # nu
|
|||
system.cpu.dcache.writebacks::total 128423 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses
|
||||
|
|
@ -698,14 +719,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 160520
|
|||
system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -714,14 +735,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
|
|||
sim_ticks 48960011000 # Number of ticks simulated
|
||||
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1457592 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1006352889 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314048 # Number of bytes of host memory used
|
||||
host_seconds 48.65 # Real time elapsed on the host
|
||||
host_inst_rate 264072 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 337712 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 182321320 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304496 # Number of bytes of host memory used
|
||||
host_seconds 268.54 # Real time elapsed on the host
|
||||
sim_insts 70913181 # Number of instructions simulated
|
||||
sim_ops 90688136 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 1606621596 # Wr
|
|||
system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10167763810 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 497813828 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 100925135 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 100941054 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 19849901 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 19849901 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 120930618 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 120930618 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.127294 # Nu
|
|||
sim_ticks 127293983000 # Number of ticks simulated
|
||||
final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 875914 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1584379759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323804 # Number of bytes of host memory used
|
||||
host_seconds 80.34 # Real time elapsed on the host
|
||||
host_inst_rate 949441 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1717378261 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313972 # Number of bytes of host memory used
|
||||
host_seconds 74.12 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 89847362 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 42187194 # To
|
|||
system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 106447639 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 25532 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 25532 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 83909 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 102280 # Tr
|
|||
system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13550144 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214631 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214631 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks)
|
||||
|
|
@ -568,7 +576,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
|
||||
|
|
@ -577,11 +584,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu
|
|||
sim_ticks 68148672000 # Number of ticks simulated
|
||||
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2339703 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2369997 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1186374997 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273296 # Number of bytes of host memory used
|
||||
host_seconds 57.44 # Real time elapsed on the host
|
||||
host_inst_rate 2078407 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1053881878 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288492 # Number of bytes of host memory used
|
||||
host_seconds 64.66 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -37,9 +37,29 @@ system.physmem.bw_write::total 1318924454 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11383698247 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 775783918 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 171784870 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 171784870 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 20864304 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 20864304 # Transaction distribution
|
||||
system.membus.trans_dist::SwapReq 15916 # Transaction distribution
|
||||
system.membus.trans_dist::SwapResp 15916 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 192665090 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 192665090 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 136297345 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu
|
|||
sim_ticks 202242260000 # Number of ticks simulated
|
||||
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1069571 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1083420 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1609480248 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 282012 # Number of bytes of host memory used
|
||||
host_seconds 125.66 # Real time elapsed on the host
|
||||
host_inst_rate 1318449 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1983988186 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297988 # Number of bytes of host memory used
|
||||
host_seconds 101.94 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 26223758 # To
|
|||
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 67847660 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 30277 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 30277 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82868 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 101256 # Tr
|
|||
system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13721664 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214401 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214401 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
|
||||
|
|
@ -473,7 +481,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
|
||||
|
|
@ -482,11 +489,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
|
|||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3321406 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1666724755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255644 # Number of bytes of host memory used
|
||||
host_seconds 547.89 # Real time elapsed on the host
|
||||
host_inst_rate 2928853 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2928852 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1469736098 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 279876 # Number of bytes of host memory used
|
||||
host_seconds 621.33 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 906468506 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11068994882 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 10108087278 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 160728502 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 160728502 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
|||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1619868 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2335193556 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265412 # Number of bytes of host memory used
|
||||
host_seconds 1123.41 # Real time elapsed on the host
|
||||
host_inst_rate 1656263 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2387660297 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289632 # Number of bytes of host memory used
|
||||
host_seconds 1098.73 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 24836956 # To
|
|||
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 72644797 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018077 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 781301 # Tr
|
|||
system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190575360 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977740 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977740 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
|
||||
|
|
@ -481,7 +489,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
|
||||
|
|
@ -490,11 +497,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916965 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21918569 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819534784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819586112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 12806033 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 12806033 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 12806033 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu
|
|||
sim_ticks 832017490000 # Number of ticks simulated
|
||||
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1782051 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 959946236 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306272 # Number of bytes of host memory used
|
||||
host_seconds 866.73 # Real time elapsed on the host
|
||||
host_inst_rate 2048371 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1103406177 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296712 # Number of bytes of host memory used
|
||||
host_seconds 754.04 # Real time elapsed on the host
|
||||
sim_insts 1544563041 # Number of instructions simulated
|
||||
sim_ops 1664032433 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 750174605 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10076480987 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 8383808419 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2172060894 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.363671 # Nu
|
|||
sim_ticks 2363670998000 # Number of ticks simulated
|
||||
final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1066052 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1637550718 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316024 # Number of bytes of host memory used
|
||||
host_seconds 1443.42 # Real time elapsed on the host
|
||||
host_inst_rate 1205605 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1851916301 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306192 # Number of bytes of host memory used
|
||||
host_seconds 1276.34 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1658228914 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 27542188 # To
|
|||
system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 80578984 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
|
||||
|
|
@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 780876 # Tr
|
|||
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190462208 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2975972 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2975972 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
|
||||
|
|
@ -561,7 +569,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
|
||||
|
|
@ -570,11 +577,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
|
|||
sim_ticks 2846007227500 # Number of ticks simulated
|
||||
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1186122 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1848085 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1122213991 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278740 # Number of bytes of host memory used
|
||||
host_seconds 2536.06 # Real time elapsed on the host
|
||||
host_inst_rate 1299561 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1229541445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299440 # Number of bytes of host memory used
|
||||
host_seconds 2314.69 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,33 @@ system.physmem.bw_write::total 542745211 # Wr
|
|||
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13588998587 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 38674388193 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu
|
|||
sim_ticks 5882580526000 # Number of ticks simulated
|
||||
final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 693030 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1355284560 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288492 # Number of bytes of host memory used
|
||||
host_seconds 4340.48 # Real time elapsed on the host
|
||||
host_inst_rate 912016 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1783532526 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308940 # Number of bytes of host memory used
|
||||
host_seconds 3298.27 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 11079992 # To
|
|||
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 32392097 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1018421 # Transaction distribution
|
||||
|
|
@ -45,11 +44,20 @@ system.membus.trans_dist::ReadExResp 781295 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190549120 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2977330 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2977330 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
|
||||
|
|
@ -454,7 +462,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
|
||||
|
|
@ -463,11 +470,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu
|
|||
sim_ticks 51522973500 # Number of ticks simulated
|
||||
final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 335661 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 335661 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188179142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271092 # Number of bytes of host memory used
|
||||
host_seconds 273.80 # Real time elapsed on the host
|
||||
host_inst_rate 356175 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 356175 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 199679816 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295568 # Number of bytes of host memory used
|
||||
host_seconds 258.03 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 4906 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 389 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35079750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 963 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 352.232606 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 215.271932 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.609683 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 308 31.98% 31.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 198 20.56% 52.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 99 10.28% 62.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 77 8.00% 70.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 83 8.62% 79.44% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 29 3.01% 82.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 26 2.70% 85.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 28 2.91% 88.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 115 11.94% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 963 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35638500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 135276000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6706.53 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25456.53 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -212,41 +212,49 @@ system.physmem.busUtilRead 0.05 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4339 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4346 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.78 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9695689.12 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states
|
||||
system.physmem.pageHitRate 81.78 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 48467499750 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1720420000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1333970250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 6600861 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3595 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3595 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 340096 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5314 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5314 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5314 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6106500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 49715250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 11407320 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 11407319 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.usedRAS 1172952 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -264,10 +272,10 @@ system.cpu.dtb.data_hits 26969994 # DT
|
|||
system.cpu.dtb.data_misses 47245 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27017239 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22956162 # ITB hits
|
||||
system.cpu.itb.fetch_hits 22956157 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 22956250 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 22956245 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -286,21 +294,21 @@ system.cpu.numWorkItemsStarted 0 # nu
|
|||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2250214 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.121246 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.891865 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 100852672 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2193275 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 13697 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1640.302767 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22940496 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1464.816806 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.302767 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800929 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800929 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
|
|
@ -308,44 +316,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22940501 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 45927975 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45927975 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22940496 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22940496 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22940496 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22940496 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22940496 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22940496 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15661 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 386976750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 386976750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 386976750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 386976750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 386976750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 386976750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22956157 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22956157 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22956157 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22956157 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22956157 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22956157 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24709.581125 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24709.581125 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24709.581125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24709.581125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24709.581125 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -360,26 +368,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661
|
|||
system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354287250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 354287250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354287250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 354287250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354287250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 354287250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22622.262308 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22622.262308 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22622.262308 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22622.262308 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
|
|
@ -388,25 +395,35 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 17998 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 17998 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 17998 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 24175250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.584038 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.793761 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy
|
||||
|
|
@ -437,14 +454,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 #
|
|||
system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5314 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 246128750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 246128750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116497000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 116497000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 362625750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 362625750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 362625750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 362625750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -463,14 +480,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68464.186370 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68464.186370 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67770.215241 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67770.215241 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68239.697027 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68239.697027 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68239.697027 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -487,14 +504,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314
|
|||
system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200952250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200952250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 94943500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 94943500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295895750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 295895750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295895750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 295895750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -503,22 +520,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55897.705146 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55897.705146 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55231.820826 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55231.820826 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55682.301468 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55682.301468 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1448.555792 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.555792 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
|
|
@ -546,14 +563,14 @@ system.cpu.dcache.demand_misses::cpu.inst 3430 # n
|
|||
system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 37054000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 37054000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196991000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 196991000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 234045000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 234045000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 234045000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 234045000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -570,14 +587,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71394.990366 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71394.990366 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67671.246994 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 67671.246994 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 68234.693878 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68234.693878 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 68234.693878 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -604,14 +621,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 2230
|
|||
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118502500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 118502500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152008500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 152008500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152008500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 152008500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -620,14 +637,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69084.536082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69084.536082 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67909.742120 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67909.742120 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68165.246637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68165.246637 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.022159 # Nu
|
|||
sim_ticks 22159411000 # Number of ticks simulated
|
||||
final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 150496 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 150496 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39616568 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240828 # Number of bytes of host memory used
|
||||
host_seconds 559.35 # Real time elapsed on the host
|
||||
host_inst_rate 217065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 217065 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57140149 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296848 # Number of bytes of host memory used
|
||||
host_seconds 387.81 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # By
|
|||
system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 40678250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 138778250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 41291750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 139391750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7774.89 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7892.15 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26524.89 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26642.15 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -222,25 +222,33 @@ system.physmem.readRowHitRate 83.22 # Ro
|
|||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 4235344.32 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 20544029500 # Time in different power states
|
||||
system.physmem.memoryStateTime::IDLE 20543925500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 739700000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 868593500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 868697500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 15110871 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3523 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3523 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1709 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1709 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 334848 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6531000 # Layer occupancy (ticks)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5232 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5232 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6530000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 48922250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 48921000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 16298030 # Number of BP lookups
|
||||
|
|
@ -288,22 +296,22 @@ system.cpu.workload.num_syscalls 389 # Nu
|
|||
system.cpu.numCycles 44318823 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 16859425 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 16859440 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 26218432 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 26218420 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 44094959 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 44094962 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 19653194 44.57% 44.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 19653197 44.57% 44.57% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -315,11 +323,11 @@ system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 44094959 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 44094962 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 13063421 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 8246941 # Number of cycles decode is blocked
|
||||
system.cpu.decode.IdleCycles 13063436 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 8246929 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing
|
||||
|
|
@ -328,9 +336,9 @@ system.cpu.decode.BranchMispred 12053 # Nu
|
|||
system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 14206611 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4728529 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8933 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.IdleCycles 14206626 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4728528 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 3626870 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename
|
||||
|
|
@ -353,28 +361,28 @@ system.cpu.memDep0.conflictingLoads 3541499 # Nu
|
|||
system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 100102495 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 21886195 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 44094959 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 44094962 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11535003 26.16% 26.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 7754472 17.59% 43.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7555417 17.13% 60.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5737107 13.01% 73.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 4489381 10.18% 84.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2977390 6.75% 90.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 2013843 4.57% 95.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 7754469 17.59% 43.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 4489383 10.18% 84.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 2977389 6.75% 90.82% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 44094959 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 44094962 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available
|
||||
|
|
@ -410,7 +418,7 @@ system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 60895265 60.83% 60.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued
|
||||
|
|
@ -439,23 +447,23 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 24980976 24.96% 92.74% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 100102495 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued
|
||||
system.cpu.iq.rate 2.258690 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 231175572 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 231175585 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 90008845 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 94135365 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 1908745 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed
|
||||
|
|
@ -468,31 +476,31 @@ system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Nu
|
|||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 3707628 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 461880 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewUnblockCycles 461879 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 414958 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 414957 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 98729732 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1372763 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 10997095 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 12532490 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 7162603 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.227716 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 97918366 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 97175585 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 67088116 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 95122373 # num instructions consuming a value
|
||||
system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 67088119 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 95122375 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back
|
||||
|
|
@ -500,23 +508,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr
|
|||
system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 39466883 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 39466886 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 14969501 37.93% 37.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 8597580 21.78% 59.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3898486 9.88% 69.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 1956471 4.96% 74.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1378247 3.49% 78.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1028776 2.61% 80.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 694004 1.76% 82.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 14969499 37.93% 37.93% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 39466883 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 39466886 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -564,23 +572,22 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% #
|
|||
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 156894387 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 156894390 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 251967276 # The number of ROB writes
|
||||
system.cpu.timesIdled 4538 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 223864 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 223861 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 133358099 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 73122879 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 133358103 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 73122882 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 718773 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 40079044 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution
|
||||
|
|
@ -589,24 +596,34 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 888128 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17856750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17856500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.icache.tags.replacements 9583 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1600.631079 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1600.631019 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631079 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631019 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
|
||||
|
|
@ -630,12 +647,12 @@ system.cpu.icache.demand_misses::cpu.inst 14533 # n
|
|||
system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14533 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 419582750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 419582750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 419582750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 419582750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 419582750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 419582750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 419606250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 419606250 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 419606250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 419606250 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 419606250 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 419606250 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses
|
||||
|
|
@ -648,12 +665,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000901
|
|||
system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28871.034886 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28871.034886 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28871.034886 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28871.034886 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28871.034886 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28872.651896 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 28872.651896 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 28872.651896 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28872.651896 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 28872.651896 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -674,34 +691,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11519
|
|||
system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306553250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 306553250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306553250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 306553250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306553250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 306553250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306578000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 306578000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306578000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 306578000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306578000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 306578000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.835316 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.835316 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.835316 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.835316 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26614.983940 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26614.983940 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26614.983940 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26614.983940 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2401.991352 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2401.991277 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.703655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347251 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940446 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.703654 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347182 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940441 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy
|
||||
|
|
@ -739,17 +756,17 @@ system.cpu.l2cache.demand_misses::total 5232 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5232 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210486500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35117500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 245604000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123627750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 123627750 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 210486500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 158745250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 369231750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 210486500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 158745250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 369231750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210511250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35108000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 245619250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123622250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 123622250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 210511250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 158730250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 369241500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 210511250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 158730250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 369241500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -774,17 +791,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.380039 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68674.225122 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76675.764192 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69714.447914 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72339.233470 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72339.233470 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68674.225122 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73255.768343 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70571.817661 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68674.225122 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73255.768343 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70571.817661 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68682.300163 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76655.021834 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69718.776611 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72336.015214 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72336.015214 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70573.681193 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68682.300163 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73248.846331 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70573.681193 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -804,17 +821,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5232
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29432500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201091500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102767750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102767750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132200250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 303859250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132200250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 303859250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171684750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29423500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201108250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102762250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102762250 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171684750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132185750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 303870500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171684750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132185750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 303870500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -826,25 +843,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.199021 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64263.100437 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57079.619642 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60133.265067 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60133.265067 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.199021 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.199021 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61006.114444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58077.073777 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56014.600326 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64243.449782 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57084.374113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60130.046811 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60130.046811 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56014.600326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60999.423166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.224006 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 160 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1457.564736 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28680752 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1457.564755 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12758.341637 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564736 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564755 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id
|
||||
|
|
@ -853,48 +870,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 131
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 57382574 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 57382574 # Number of data accesses
|
||||
system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492734 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492734 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 28680490 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 28680490 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 28680490 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 28680490 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1041 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1041 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8369 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8369 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 28680491 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9410 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65428750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 65428750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 523784968 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 523784968 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 65491750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 65491750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 523624968 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 523624968 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 589213718 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 589213718 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 589213718 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 589213718 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22188797 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22188797 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 589116718 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 589116718 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 589116718 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 589116718 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 28689900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 28689900 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 28689900 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 28689900 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses
|
||||
|
|
@ -905,16 +922,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000328
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.825168 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.825168 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62586.326682 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62586.326682 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62851.967370 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62851.967370 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62574.685468 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62574.685468 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62615.697981 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62615.697981 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62615.697981 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62605.389798 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62605.389798 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62605.389798 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 29209 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked
|
||||
|
|
@ -925,10 +942,10 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 110 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 110 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 528 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 528 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6635 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6635 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits
|
||||
|
|
@ -943,16 +960,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2247
|
|||
system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36170500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36170500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125701245 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 125701245 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36161000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36161000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125695745 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 125695745 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161871745 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 161871745 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161871745 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 161871745 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161856745 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 161856745 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161856745 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 161856745 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -963,16 +980,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70507.797271 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70507.797271 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72492.067474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72492.067474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70489.278752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70489.278752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72488.895617 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72488.895617 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72039.049844 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72039.049844 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72032.374277 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72032.374277 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu
|
|||
sim_ticks 45951567500 # Number of ticks simulated
|
||||
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 3319618 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1659808736 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259284 # Number of bytes of host memory used
|
||||
host_seconds 27.68 # Real time elapsed on the host
|
||||
host_inst_rate 2845952 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2845951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1422976169 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 283520 # Number of bytes of host memory used
|
||||
host_seconds 32.29 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 672903574 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11030545389 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 506870851 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 111899287 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 111899287 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 6501103 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 6501103 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 118400390 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 118400390 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
|||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1742639 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2251309988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268020 # Number of bytes of host memory used
|
||||
host_seconds 52.74 # Real time elapsed on the host
|
||||
host_inst_rate 1660785 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2145562848 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293264 # Number of bytes of host memory used
|
||||
host_seconds 55.34 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 1412827 # In
|
|||
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 2568532 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3043 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 304960 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4765 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4765 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
|
||||
|
|
@ -477,7 +485,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
|
|
@ -486,11 +493,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 21573 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 544640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 693760 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 10840 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 10840 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 10840 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.131652 # Nu
|
|||
sim_ticks 131652469500 # Number of ticks simulated
|
||||
final_tick 131652469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 235317 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 248063 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 179784828 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321352 # Number of bytes of host memory used
|
||||
host_seconds 732.28 # Real time elapsed on the host
|
||||
host_inst_rate 246188 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 259522 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188090070 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311300 # Number of bytes of host memory used
|
||||
host_seconds 699.94 # Real time elapsed on the host
|
||||
sim_insts 172317809 # Number of instructions simulated
|
||||
sim_ops 181650742 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 240 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 241 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -182,26 +182,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 903 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 272.372093 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 179.073064 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 280.203163 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 262 29.01% 29.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 352 38.98% 68.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 86 9.52% 77.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 48 5.32% 82.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 35 3.88% 86.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 23 2.55% 89.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 17 1.88% 91.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 16 1.77% 92.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 64 7.09% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 903 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27589000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100132750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 904 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 272.070796 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 178.793599 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 280.048713 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 264 29.20% 29.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 351 38.83% 68.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 86 9.51% 77.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 48 5.31% 82.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 35 3.87% 86.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 23 2.54% 89.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 17 1.88% 91.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 16 1.77% 92.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 64 7.08% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 904 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 27698500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100242250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7130.78 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7159.09 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25880.78 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25909.09 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -212,31 +212,39 @@ system.physmem.busUtilRead 0.01 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 2961 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 2960 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.53 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 76.51 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 34027495.86 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.53 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 125800689500 # Time in different power states
|
||||
system.physmem.pageHitRate 76.51 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 125800686500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 4396080000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1453432500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1453435500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1880831 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 2779 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2779 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1090 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 247616 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3869 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3869 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4528000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 36223250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 36225250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 49915423 # Number of BP lookups
|
||||
|
|
@ -345,12 +353,12 @@ system.cpu.ipc 0.654442 # IP
|
|||
system.cpu.tickCycles 255940225 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 7364714 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 2881 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.983797 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1424.983856 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 71509873 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4678 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15286.420051 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983797 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.983856 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695793 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695793 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
|
||||
|
|
@ -374,12 +382,12 @@ system.cpu.icache.demand_misses::cpu.inst 4679 # n
|
|||
system.cpu.icache.demand_misses::total 4679 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4679 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4679 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 184764496 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 184764496 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 184764496 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 184764496 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 184764496 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 184764496 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 184816496 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 184816496 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 184816496 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 184816496 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 184816496 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 184816496 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71514552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 71514552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 71514552 # number of demand (read+write) accesses
|
||||
|
|
@ -392,12 +400,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000065
|
|||
system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39488.030776 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 39488.030776 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 39488.030776 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39488.030776 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 39488.030776 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39499.144262 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 39499.144262 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 39499.144262 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 39499.144262 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 39499.144262 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,26 +420,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4679
|
|||
system.cpu.icache.demand_mshr_misses::total 4679 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4679 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4679 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174487504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 174487504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174487504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 174487504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174487504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 174487504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 174539504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 174539504 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 174539504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 174539504 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 174539504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 174539504 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37291.622996 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37291.622996 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37291.622996 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37291.622996 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37302.736482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37302.736482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37302.736482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 37302.736482 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3161293 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5390 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
|
|
@ -440,11 +447,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9357 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3634 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 12991 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 416192 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 416192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6504 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 6504 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6504 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3268000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7477496 # Layer occupancy (ticks)
|
||||
|
|
@ -452,13 +473,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L
|
|||
system.cpu.toL2Bus.respLayer1.occupancy 2996735 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2001.642880 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2001.642948 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2592 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.930032 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.028976 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613905 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1998.613972 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060993 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061085 # Average percentage of cache occupancy
|
||||
|
|
@ -489,14 +510,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 3889 #
|
|||
system.cpu.l2cache.demand_misses::total 3889 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3889 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3889 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190654250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 190654250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75964500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 75964500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 266618750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 266618750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 266618750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 266618750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 190706250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 190706250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 75951500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 75951500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 266657750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 266657750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 266657750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 266657750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 5390 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5390 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -515,14 +536,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.599414
|
|||
system.cpu.l2cache.demand_miss_rate::total 0.599414 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.599414 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.599414 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68115.130404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68115.130404 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69692.201835 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69692.201835 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68557.148367 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68557.148367 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68557.148367 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68133.708467 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68133.708467 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69680.275229 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69680.275229 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68567.176652 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68567.176652 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68567.176652 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -545,14 +566,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 3870
|
|||
system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154631750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154631750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62298500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62298500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216930250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 216930250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216930250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 216930250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154681250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 154681250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 62286000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62286000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216967250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 216967250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216967250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 216967250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515770 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.515770 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -561,22 +582,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.596486
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.596486 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.596486 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.596486 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55622.931655 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55622.931655 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57154.587156 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57154.587156 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56054.328165 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56054.328165 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55640.737410 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55640.737410 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57143.119266 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57143.119266 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.888889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56063.888889 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1376.810162 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1376.810186 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40745471 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1809 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22523.754008 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810162 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1376.810186 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.336135 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336135 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1767 # Occupied blocks per task id
|
||||
|
|
@ -610,12 +631,12 @@ system.cpu.dcache.overall_misses::cpu.inst 2411 #
|
|||
system.cpu.dcache.overall_misses::total 2411 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 52005983 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 52005983 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115778750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 115778750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 167784733 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 167784733 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 167784733 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 167784733 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 115743750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 115743750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 167749733 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 167749733 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 167749733 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 167749733 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 28338781 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28338781 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 12364287 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -638,12 +659,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000059
|
|||
system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 67804.410691 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67804.410691 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70425.030414 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70425.030414 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 69591.345085 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69591.345085 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 69591.345085 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70403.740876 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70403.740876 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 69576.828287 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 69576.828287 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 69576.828287 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -672,12 +693,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 1809
|
|||
system.cpu.dcache.overall_mshr_misses::total 1809 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 47475265 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47475265 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77144500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77144500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124619765 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 124619765 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124619765 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 124619765 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77131500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77131500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 124606765 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 124606765 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 124606765 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 124606765 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -688,12 +709,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000044
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66772.524613 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66772.524613 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70259.107468 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70259.107468 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68888.758983 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68888.758983 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70247.267760 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70247.267760 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68881.572692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68881.572692 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu
|
|||
sim_ticks 99596491000 # Number of ticks simulated
|
||||
final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1821315 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1052688537 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309564 # Number of bytes of host memory used
|
||||
host_seconds 94.61 # Real time elapsed on the host
|
||||
host_inst_rate 2060285 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2171872 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1190808654 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300012 # Number of bytes of host memory used
|
||||
host_seconds 83.64 # Real time elapsed on the host
|
||||
sim_insts 172317409 # Number of instructions simulated
|
||||
sim_ops 181650341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,36 @@ system.physmem.bw_write::total 454362795 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9189347896 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 915226805 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 217614902 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 217637309 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 12364287 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 12364287 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFReq 463 # Transaction distribution
|
||||
system.membus.trans_dist::SoftPFResp 463 # Transaction distribution
|
||||
system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution
|
||||
system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 230024466 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram
|
||||
system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 230024466 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.230173 # Nu
|
|||
sim_ticks 230173357000 # Number of ticks simulated
|
||||
final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1246866 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1670106565 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319316 # Number of bytes of host memory used
|
||||
host_seconds 137.82 # Real time elapsed on the host
|
||||
host_inst_rate 1215411 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1281349 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1627973861 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309492 # Number of bytes of host memory used
|
||||
host_seconds 141.39 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 181165370 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 480751 # In
|
|||
system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 960111 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 220992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3453 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3453 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks)
|
||||
|
|
@ -555,7 +563,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
|
|
@ -564,11 +571,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6102 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3594 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 9696 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu
|
|||
sim_ticks 96722945000 # Number of ticks simulated
|
||||
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2358558 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2358560 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1179286883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269756 # Number of bytes of host memory used
|
||||
host_seconds 82.02 # Real time elapsed on the host
|
||||
host_inst_rate 2119754 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2119756 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1059884256 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 284956 # Number of bytes of host memory used
|
||||
host_seconds 91.26 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -37,9 +37,29 @@ system.physmem.bw_write::total 745070490 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11057254439 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1069490213 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 251180603 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 251180603 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 18976439 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 18976439 # Transaction distribution
|
||||
system.membus.trans_dist::SwapReq 22406 # Transaction distribution
|
||||
system.membus.trans_dist::SwapResp 22406 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 270179448 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 270179448 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 401 # Number of system calls
|
||||
system.cpu.numCycles 193445891 # number of cpu cycles simulated
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu
|
|||
sim_ticks 270563082000 # Number of ticks simulated
|
||||
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1069922 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1069924 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1496457293 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278484 # Number of bytes of host memory used
|
||||
host_seconds 180.80 # Real time elapsed on the host
|
||||
host_inst_rate 1449498 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2027353723 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294428 # Number of bytes of host memory used
|
||||
host_seconds 133.46 # Real time elapsed on the host
|
||||
sim_insts 193444518 # Number of instructions simulated
|
||||
sim_ops 193444756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 850848 # In
|
|||
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 1223641 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4095 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 331072 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 5173 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5173 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks)
|
||||
|
|
@ -460,7 +468,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
|
||||
|
|
@ -469,11 +476,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24576 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 786432 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 13866 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 13866 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 13866 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu
|
|||
sim_ticks 131393279000 # Number of ticks simulated
|
||||
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1131336 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1896222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1125528252 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303676 # Number of bytes of host memory used
|
||||
host_seconds 116.74 # Real time elapsed on the host
|
||||
host_inst_rate 1264426 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 324376 # Number of bytes of host memory used
|
||||
host_seconds 104.45 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,33 @@ system.physmem.bw_write::total 759720678 # Wr
|
|||
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13685638205 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 1798200879 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
|
||||
system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 250692103 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu
|
|||
sim_ticks 250953957000 # Number of ticks simulated
|
||||
final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 652190 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1093130 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1239252699 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313428 # Number of bytes of host memory used
|
||||
host_seconds 202.50 # Real time elapsed on the host
|
||||
host_inst_rate 881800 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1675544377 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 333860 # Number of bytes of host memory used
|
||||
host_seconds 149.77 # Real time elapsed on the host
|
||||
sim_insts 132071193 # Number of instructions simulated
|
||||
sim_ops 221363385 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -29,7 +29,6 @@ system.physmem.bw_inst_read::total 724276 # In
|
|||
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 1207552 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
|
||||
|
|
@ -37,11 +36,20 @@ system.membus.trans_dist::ReadExResp 1575 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 303040 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4735 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4735 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
|
||||
|
|
@ -450,7 +458,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
|
||||
|
|
@ -459,11 +466,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9388 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 13205 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,58 +1,90 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332049000 # Number of ticks simulated
|
||||
final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1829331993500 # Number of ticks simulated
|
||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2314619 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70524837278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315304 # Number of bytes of host memory used
|
||||
host_seconds 25.94 # Real time elapsed on the host
|
||||
sim_insts 60038433 # Number of instructions simulated
|
||||
sim_ops 60038433 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 2920462 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 88984410684 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 366200 # Number of bytes of host memory used
|
||||
host_seconds 20.56 # Real time elapsed on the host
|
||||
sim_insts 60038469 # Number of instructions simulated
|
||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 41099809 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 75185198 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 948404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948404 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 74279 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116985 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116985 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1174168 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1174168 # Request fanout histogram
|
||||
system.iocache.tags.replacements 41686 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor
|
||||
system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
@ -108,15 +140,15 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710428 # DTB read hits
|
||||
system.cpu.dtb.read_hits 9710423 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6352498 # DTB write hits
|
||||
system.cpu.dtb.write_hits 6352496 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062926 # DTB hits
|
||||
system.cpu.dtb.data_hits 16062919 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
|
|
@ -136,32 +168,32 @@ system.cpu.itb.data_hits 0 # DT
|
|||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658664099 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3658670345 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038433 # Number of instructions committed
|
||||
system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 60038469 # Number of instructions committed
|
||||
system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913650 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913692 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115710 # number of memory refs
|
||||
system.cpu.num_load_insts 9747514 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064413 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.num_mem_refs 16115703 # number of memory refs
|
||||
system.cpu.num_load_insts 9747509 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064428 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
|
|
@ -189,11 +221,11 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050271 # Class of executed instruction
|
||||
system.cpu.op_class::total 60050307 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
|
||||
|
|
@ -207,11 +239,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu
|
|||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
|
|
@ -275,9 +307,9 @@ system.cpu.kern.mode_switch_good::kernel 0.320726 # fr
|
|||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
|
|
@ -310,15 +342,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
|||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.iobus.throughput 1480181 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2707742 # Total data (bytes)
|
||||
system.cpu.icache.tags.replacements 919591 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor
|
||||
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.icache.tags.replacements 919603 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
|
|
@ -326,26 +393,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130053 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920218 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130077 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920230 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
|
|
@ -361,17 +428,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992295 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 992289 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||
|
|
@ -381,64 +448,64 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -447,14 +514,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74285 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74279 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2042683 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
|
|
@ -464,52 +531,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13656011 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026051 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -518,11 +585,35 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833484 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,18 +1,30 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.321351 # Number of seconds simulated
|
||||
sim_ticks 2321351025500 # Number of ticks simulated
|
||||
final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.321335 # Number of seconds simulated
|
||||
sim_ticks 2321335404000 # Number of ticks simulated
|
||||
final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 818788 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 430844 # Number of bytes of host memory used
|
||||
host_seconds 73.78 # Real time elapsed on the host
|
||||
host_inst_rate 1308981 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50301976363 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 455960 # Number of bytes of host memory used
|
||||
host_seconds 46.15 # Real time elapsed on the host
|
||||
sim_insts 60406834 # Number of instructions simulated
|
||||
sim_ops 72742429 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
|
||||
|
|
@ -33,47 +45,127 @@ system.physmem.num_reads::total 13921575 # Nu
|
|||
system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55568847 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 128994799 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 14973631 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 14973631 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 763122 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 763122 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 57873 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 131874 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 131874 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 214751 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 214751 # Request fanout histogram
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.iobus.throughput 48459111 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 112490607 # Total data (bytes)
|
||||
system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 8131 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 8131 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
|
|
@ -98,7 +190,7 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT
|
|||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 13142244 # DTB read hits
|
||||
system.cpu.dtb.read_hits 13142243 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7297 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11216207 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2181 # DTB write misses
|
||||
|
|
@ -111,12 +203,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 13149541 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 13149540 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11218388 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 24358451 # DTB hits
|
||||
system.cpu.dtb.hits 24358450 # DTB hits
|
||||
system.cpu.dtb.misses 9478 # DTB misses
|
||||
system.cpu.dtb.accesses 24367929 # DTB accesses
|
||||
system.cpu.dtb.accesses 24367928 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
|
|
@ -159,7 +251,7 @@ system.cpu.itb.inst_accesses 61434478 # IT
|
|||
system.cpu.itb.hits 61430007 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 61434478 # DTB accesses
|
||||
system.cpu.numCycles 4642702052 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4642753590 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60406834 # Number of instructions committed
|
||||
|
|
@ -179,10 +271,10 @@ system.cpu.num_cc_register_writes 28977741 # nu
|
|||
system.cpu.num_mem_refs 25221274 # number of memory refs
|
||||
system.cpu.num_load_insts 13499937 # Number of load instructions
|
||||
system.cpu.num_store_insts 11721337 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
|
||||
system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.984109 # Percentage of idle cycles
|
||||
system.cpu.Branches 10298517 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
|
||||
|
|
@ -221,35 +313,35 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::total 72875708 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 850515 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.replacements 850504 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 60581751 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.689630 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 60581740 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851027 # number of overall misses
|
||||
system.cpu.icache.tags.tag_accesses 62283783 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 62283783 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 60581751 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 60581751 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 60581751 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 60581751 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 60581751 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 60581751 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851016 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851016 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851016 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851016 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851016 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851016 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
|
||||
|
|
@ -272,21 +364,21 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 62250 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 50006.820137 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1669876 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.avg_refs 13.083214 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959772 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993972 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.485209 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.561537 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.563016 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107033 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092935 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
|
||||
|
|
@ -298,29 +390,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 17035355 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 17035355 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7540 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 838782 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 366774 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1216247 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 592630 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 592630 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 113709 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 113709 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7540 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 838782 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 480483 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1329956 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7540 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 838782 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 480483 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1329956 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses
|
||||
|
|
@ -340,46 +432,46 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 3
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7545 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849390 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 376645 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1236734 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 592630 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 592630 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247183 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247183 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7545 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 849390 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 623828 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1483917 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7545 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 849390 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 623828 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1483917 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539981 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539981 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229783 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.103753 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229783 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.103753 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -391,11 +483,11 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57873 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 623329 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 623316 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 21798557 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.943217 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -405,36 +497,36 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 291
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 90313368 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 90313368 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11240238 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11240238 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9961313 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9961313 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236011 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236011 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 21201551 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21201551 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21312407 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21312407 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 292017 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 292017 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250126 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250126 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615595 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11186 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11186 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 542143 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 542143 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615585 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615585 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 11532255 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -443,20 +535,20 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21743694 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21927992 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21927992 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025322 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.025322 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.024933 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.024933 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -467,12 +559,44 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 592642 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 592630 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 592630 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,89 +1,129 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112126 # Number of seconds simulated
|
||||
sim_ticks 5112125984500 # Number of ticks simulated
|
||||
final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.112127 # Number of seconds simulated
|
||||
sim_ticks 5112126720000 # Number of ticks simulated
|
||||
final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1274105 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32578287771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 593532 # Number of bytes of host memory used
|
||||
host_seconds 156.92 # Real time elapsed on the host
|
||||
sim_insts 199930130 # Number of instructions simulated
|
||||
sim_ops 409344539 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1627732 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41616843658 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 647148 # Number of bytes of host memory used
|
||||
host_seconds 122.84 # Real time elapsed on the host
|
||||
sim_insts 199947158 # Number of instructions simulated
|
||||
sim_ops 409371517 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9050072 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 46265107 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.tags.replacements 47569 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use
|
||||
system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 13903648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903648 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13796 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13796 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 98213 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134490 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134485 # Transaction distribution
|
||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 328402 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 328402 # Request fanout histogram
|
||||
system.iocache.tags.replacements 47573 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor
|
||||
system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 428616 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428616 # Number of data accesses
|
||||
system.iocache.tags.tag_accesses 428652 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428652 # Number of data accesses
|
||||
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
|
||||
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 904 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
|
||||
system.iocache.overall_misses::total 904 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 908 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
|
||||
system.iocache.overall_misses::total 908 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
|
|
@ -111,39 +151,92 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0
|
|||
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
||||
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iobus.throughput 2555207 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 13062542 # Total data (bytes)
|
||||
system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57577 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteResp 10857 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224253344 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224257410 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199930130 # Number of instructions committed
|
||||
system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 199947158 # Number of instructions committed
|
||||
system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2307745 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374365317 # number of integer instructions
|
||||
system.cpu.num_func_calls 2307997 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374392167 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35661072 # number of memory refs
|
||||
system.cpu.num_load_insts 27238907 # Number of load instructions
|
||||
system.cpu.num_store_insts 8422165 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
|
||||
system.cpu.Branches 43125613 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35671209 # number of memory refs
|
||||
system.cpu.num_load_insts 27243676 # Number of load instructions
|
||||
system.cpu.num_store_insts 8427533 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955619 # Percentage of idle cycles
|
||||
system.cpu.Branches 43128209 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
|
||||
|
|
@ -170,18 +263,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409345569 # Class of executed instruction
|
||||
system.cpu.op_class::total 409372552 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 790679 # number of replacements
|
||||
system.cpu.icache.tags.replacements 791918 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
|
||||
|
|
@ -189,34 +282,35 @@ system.cpu.icache.tags.occ_percent::total 0.997393 # A
|
|||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243526070 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791198 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
|
||||
system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243546972 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 792437 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -226,50 +320,51 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
|||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
|
||||
system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses
|
||||
system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
|
||||
system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses
|
||||
system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits
|
||||
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
|
||||
system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses
|
||||
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses
|
||||
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses
|
||||
system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -278,49 +373,49 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428199 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -329,65 +424,65 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1622084 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.replacements 1623316 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20173085 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624882 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses
|
||||
system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20123101 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20123101 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20182000 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20182000 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905995 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1223040 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1626101 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1626101 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12928863 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8417278 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461960 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21346141 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21346141 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21808101 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21808101 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070075 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070075 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037666 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037666 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872502 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057296 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057296 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074564 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -396,118 +491,148 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535815 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1536734 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.tags.replacements 105997 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 279540499 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4020451 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.108195 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 3972823 98.82% 98.82% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram
|
||||
system.cpu.l2cache.tags.replacements 106060 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.551712 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792069 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159032 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989107 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 32243624 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 32243624 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7334 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 779106 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1276189 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2065966 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1540333 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1540333 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 180012 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 180012 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7334 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779106 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1456201 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2245978 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7334 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779106 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1456201 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2245978 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13318 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 32226 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 45550 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1809 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1809 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134768 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134768 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13318 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166994 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180318 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13318 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166994 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180318 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7335 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792424 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -516,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98154 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98213 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,50 +1,81 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.200409 # Number of seconds simulated
|
||||
sim_ticks 200409284500 # Number of ticks simulated
|
||||
final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 200409271000 # Number of ticks simulated
|
||||
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 23274047 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 23274036 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8904961694 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 483300 # Number of bytes of host memory used
|
||||
host_seconds 22.51 # Real time elapsed on the host
|
||||
sim_insts 523790075 # Number of instructions simulated
|
||||
sim_ops 523790075 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 15445218 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 15445213 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5909651303 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 534848 # Number of bytes of host memory used
|
||||
host_seconds 33.91 # Real time elapsed on the host
|
||||
sim_insts 523780905 # Number of instructions simulated
|
||||
sim_ops 523780905 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
testsys.clk_domain.clock 1000 # Clock period in ticks
|
||||
testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory
|
||||
testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
|
||||
testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory
|
||||
testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory
|
||||
testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory
|
||||
testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
|
||||
testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory
|
||||
testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.membus.throughput 916540501 # Throughput (bytes/s)
|
||||
testsys.membus.data_through_bus 183683226 # Total data (bytes)
|
||||
testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
|
||||
testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
|
||||
testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution
|
||||
testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution
|
||||
testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution
|
||||
testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution
|
||||
testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution
|
||||
testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.snoops 0 # Total snoops (count)
|
||||
testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
|
||||
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -62,22 +93,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT
|
|||
testsys.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
testsys.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
testsys.cpu.dtb.read_hits 3916918 # DTB read hits
|
||||
testsys.cpu.dtb.read_hits 3916768 # DTB read hits
|
||||
testsys.cpu.dtb.read_misses 3287 # DTB read misses
|
||||
testsys.cpu.dtb.read_acv 80 # DTB read access violations
|
||||
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
|
||||
testsys.cpu.dtb.write_hits 2316885 # DTB write hits
|
||||
testsys.cpu.dtb.write_hits 2316721 # DTB write hits
|
||||
testsys.cpu.dtb.write_misses 528 # DTB write misses
|
||||
testsys.cpu.dtb.write_acv 81 # DTB write access violations
|
||||
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
|
||||
testsys.cpu.dtb.data_hits 6233803 # DTB hits
|
||||
testsys.cpu.dtb.data_hits 6233489 # DTB hits
|
||||
testsys.cpu.dtb.data_misses 3815 # DTB misses
|
||||
testsys.cpu.dtb.data_acv 161 # DTB access violations
|
||||
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
|
||||
testsys.cpu.itb.fetch_hits 4052211 # ITB hits
|
||||
testsys.cpu.itb.fetch_hits 4052237 # ITB hits
|
||||
testsys.cpu.itb.fetch_misses 1497 # ITB misses
|
||||
testsys.cpu.itb.fetch_acv 69 # ITB acv
|
||||
testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses
|
||||
testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses
|
||||
testsys.cpu.itb.read_hits 0 # DTB read hits
|
||||
testsys.cpu.itb.read_misses 0 # DTB read misses
|
||||
testsys.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -90,31 +121,31 @@ testsys.cpu.itb.data_hits 0 # DT
|
|||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 400804755 # number of cpu cycles simulated
|
||||
testsys.cpu.numCycles 400825859 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 20257704 # Number of instructions committed
|
||||
testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses
|
||||
testsys.cpu.committedInsts 20257044 # Number of instructions committed
|
||||
testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed
|
||||
testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses
|
||||
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
|
||||
testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 18837017 # number of integer instructions
|
||||
testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured
|
||||
testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls
|
||||
testsys.cpu.num_int_insts 18836392 # number of integer instructions
|
||||
testsys.cpu.num_fp_insts 17380 # number of float instructions
|
||||
testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written
|
||||
testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read
|
||||
testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written
|
||||
testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
|
||||
testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
|
||||
testsys.cpu.num_mem_refs 6263046 # number of memory refs
|
||||
testsys.cpu.num_load_insts 3944033 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 2319013 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 2929848 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 12147338 59.95% 63.47% # Class of executed instruction
|
||||
testsys.cpu.num_mem_refs 6262732 # number of memory refs
|
||||
testsys.cpu.num_load_insts 3943883 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 2318849 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 2929782 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction
|
||||
|
|
@ -143,34 +174,34 @@ testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Cl
|
|||
testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction
|
||||
testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction
|
||||
testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction
|
||||
testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
testsys.cpu.op_class::total 20261680 # Class of executed instruction
|
||||
testsys.cpu.op_class::total 20261020 # Class of executed instruction
|
||||
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed
|
||||
testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl
|
||||
testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl
|
||||
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl
|
||||
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
|
||||
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
|
||||
|
|
@ -195,27 +226,27 @@ testsys.cpu.kern.syscall::118 2 2.41% 100.00% # nu
|
|||
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
|
||||
testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 128307 # number of callpals executed
|
||||
testsys.cpu.kern.callpal::total 128309 # number of callpals executed
|
||||
testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
|
||||
testsys.cpu.kern.mode_good::kernel 707
|
||||
testsys.cpu.kern.mode_good::user 702
|
||||
testsys.cpu.kern.mode_good::kernel 711
|
||||
testsys.cpu.kern.mode_good::user 706
|
||||
testsys.cpu.kern.mode_good::idle 5
|
||||
testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches
|
||||
testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode
|
||||
testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
|
||||
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
|
||||
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
|
||||
|
|
@ -267,14 +298,32 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to
|
|||
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
testsys.iobus.throughput 290423421 # Throughput (bytes/s)
|
||||
testsys.iobus.data_through_bus 58203550 # Total data (bytes)
|
||||
testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution
|
||||
testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution
|
||||
testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution
|
||||
testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
drivesys.clk_domain.clock 1000 # Clock period in ticks
|
||||
drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory
|
||||
drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory
|
||||
|
|
@ -282,27 +331,58 @@ drivesys.physmem.bytes_written::tsunami.ethernet 1064
|
|||
drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory
|
||||
drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory
|
||||
drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory
|
||||
drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.membus.throughput 874808223 # Throughput (bytes/s)
|
||||
drivesys.membus.data_through_bus 175319690 # Total data (bytes)
|
||||
drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
drivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
|
||||
drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
|
||||
drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution
|
||||
drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution
|
||||
drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution
|
||||
drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution
|
||||
drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution
|
||||
drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.snoops 0 # Total snoops (count)
|
||||
drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
|
||||
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -348,7 +428,7 @@ drivesys.cpu.itb.data_hits 0 # DT
|
|||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated
|
||||
drivesys.cpu.numCycles 801651324 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 19050784 # Number of instructions committed
|
||||
|
|
@ -366,10 +446,10 @@ drivesys.cpu.num_fp_register_writes 766 # nu
|
|||
drivesys.cpu.num_mem_refs 5830788 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 3746196 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 2084592 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
|
||||
drivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles
|
||||
drivesys.cpu.Branches 2793313 # Number of branches fetched
|
||||
drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction
|
||||
|
|
@ -476,9 +556,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu
|
|||
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
|
||||
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
|
||||
drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA
|
||||
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
|
||||
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
|
||||
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
|
||||
|
|
@ -505,7 +585,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av
|
|||
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR
|
||||
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||||
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||||
|
|
@ -513,25 +593,39 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu
|
|||
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||||
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||||
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.iobus.throughput 290456573 # Throughput (bytes/s)
|
||||
drivesys.iobus.data_through_bus 58210194 # Total data (bytes)
|
||||
drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000407 # Number of seconds simulated
|
||||
sim_ticks 407341500 # Number of ticks simulated
|
||||
final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 11799945954 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 11797124974 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9171074905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 483300 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 523862353 # Number of instructions simulated
|
||||
sim_ops 523862353 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 7893991697 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7892445581 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6135954870 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 534848 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 523853183 # Number of instructions simulated
|
||||
sim_ops 523853183 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
testsys.clk_domain.clock 1000 # Clock period in ticks
|
||||
testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
|
||||
|
|
@ -560,9 +654,40 @@ testsys.physmem.bw_total::cpu.inst 354749025 # To
|
|||
testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
|
||||
testsys.membus.throughput 835780297 # Throughput (bytes/s)
|
||||
testsys.membus.data_through_bus 340448 # Total data (bytes)
|
||||
testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
|
||||
testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
|
||||
testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution
|
||||
testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution
|
||||
testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
|
||||
testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
|
||||
testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
|
||||
testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.snoops 0 # Total snoops (count)
|
||||
testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
|
||||
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -608,7 +733,7 @@ testsys.cpu.itb.data_hits 0 # DT
|
|||
testsys.cpu.itb.data_misses 0 # DTB misses
|
||||
testsys.cpu.itb.data_acv 0 # DTB access violations
|
||||
testsys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
testsys.cpu.numCycles 821016 # number of cpu cycles simulated
|
||||
testsys.cpu.numCycles 821056 # number of cpu cycles simulated
|
||||
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
testsys.cpu.committedInsts 36126 # Number of instructions committed
|
||||
|
|
@ -626,10 +751,10 @@ testsys.cpu.num_fp_register_writes 0 # nu
|
|||
testsys.cpu.num_mem_refs 11041 # number of memory refs
|
||||
testsys.cpu.num_load_insts 7105 # Number of load instructions
|
||||
testsys.cpu.num_store_insts 3936 # Number of store instructions
|
||||
testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles
|
||||
testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles
|
||||
testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles
|
||||
testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles
|
||||
testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 5238 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction
|
||||
|
|
@ -739,8 +864,22 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to
|
|||
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
|
||||
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
testsys.iobus.throughput 290429529 # Throughput (bytes/s)
|
||||
testsys.iobus.data_through_bus 118304 # Total data (bytes)
|
||||
testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution
|
||||
testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution
|
||||
testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution
|
||||
testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
drivesys.clk_domain.clock 1000 # Clock period in ticks
|
||||
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
|
||||
|
|
@ -769,9 +908,40 @@ drivesys.physmem.bw_total::cpu.inst 355004339 # To
|
|||
drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
|
||||
drivesys.membus.throughput 836094530 # Throughput (bytes/s)
|
||||
drivesys.membus.data_through_bus 340576 # Total data (bytes)
|
||||
drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
|
||||
drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
|
||||
drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution
|
||||
drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution
|
||||
drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution
|
||||
drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution
|
||||
drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution
|
||||
drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.snoops 0 # Total snoops (count)
|
||||
drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
|
||||
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -817,7 +987,7 @@ drivesys.cpu.itb.data_hits 0 # DT
|
|||
drivesys.cpu.itb.data_misses 0 # DTB misses
|
||||
drivesys.cpu.itb.data_acv 0 # DTB access violations
|
||||
drivesys.cpu.itb.data_accesses 0 # DTB accesses
|
||||
drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated
|
||||
drivesys.cpu.numCycles 1626281 # number of cpu cycles simulated
|
||||
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
drivesys.cpu.committedInsts 36152 # Number of instructions committed
|
||||
|
|
@ -835,10 +1005,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu
|
|||
drivesys.cpu.num_mem_refs 11043 # number of memory refs
|
||||
drivesys.cpu.num_load_insts 7109 # Number of load instructions
|
||||
drivesys.cpu.num_store_insts 3934 # Number of store instructions
|
||||
drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles
|
||||
drivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles
|
||||
drivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles
|
||||
drivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles
|
||||
drivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles
|
||||
drivesys.cpu.Branches 5243 # Number of branches fetched
|
||||
drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction
|
||||
|
|
@ -948,7 +1118,21 @@ drivesys.tsunami.ethernet.totalRxOrn 0 # to
|
|||
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
|
||||
drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
|
||||
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
drivesys.iobus.throughput 290488448 # Throughput (bytes/s)
|
||||
drivesys.iobus.data_through_bus 118328 # Total data (bytes)
|
||||
drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution
|
||||
drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000035 # Number of seconds simulated
|
||||
sim_ticks 35015500 # Number of ticks simulated
|
||||
final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 35024500 # Number of ticks simulated
|
||||
final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 57020 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 57008 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 311836228 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 240292 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 173753 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 173686 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 950177695 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289108 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6400 # Number of instructions simulated
|
||||
sim_ops 6400 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu
|
|||
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 533 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 34917000 # Total gap between requests
|
||||
system.physmem.totGap 34926000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By
|
|||
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3823500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 3928000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.61 # Data bus utilization in percentage
|
||||
|
|
@ -216,24 +216,32 @@ system.physmem.readRowHits 435 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 65510.32 # Average gap between requests
|
||||
system.physmem.avgGap 65527.20 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 30385500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 974197141 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 460 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 460 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34112 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 533 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 533 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
|
||||
|
|
@ -281,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 70031 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 70049 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6400 # Number of instructions committed
|
||||
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 10.942344 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.091388 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 10.945156 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.091365 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
|
||||
|
|
@ -319,12 +327,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n
|
|||
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses
|
||||
|
|
@ -337,12 +345,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138783
|
|||
system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -357,26 +365,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
|
|||
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
|
||||
|
|
@ -396,14 +413,14 @@ system.cpu.toL2Bus.respLayer0.utilization 1.8 # L
|
|||
system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
|
||||
|
|
@ -426,12 +443,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 533 #
|
|||
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -450,12 +467,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -472,14 +489,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533
|
|||
system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -488,24 +505,24 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127
|
|||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
|
|
@ -528,10 +545,10 @@ system.cpu.dcache.demand_misses::cpu.inst 227 # n
|
|||
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 227 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
|
||||
|
|
@ -552,10 +569,10 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417
|
|||
system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
|
||||
|
|
@ -584,10 +601,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 169
|
|||
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
|
||||
|
|
@ -600,10 +617,10 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20537500 # Number of ticks simulated
|
||||
final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 46749 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 46745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 150649735 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236424 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_inst_rate 100086 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100066 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 322455292 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290128 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # By
|
|||
system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 4551750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13683000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 4742750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9346.51 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28096.51 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15339250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1517614121 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 415 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 415 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 31168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 487 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 487 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 3.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks)
|
||||
|
|
@ -579,7 +587,6 @@ system.cpu.fp_regfile_reads 8 # nu
|
|||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1520730371 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
|
||||
|
|
@ -587,11 +594,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 72 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 3208000 # Number of ticks simulated
|
||||
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 172950 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 172880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 86758979 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253924 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 1057772 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1055326 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 528762156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277832 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 2087281796 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12806733167 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 41084 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 7583 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 7583 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 865 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 865 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 8448 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 8448 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32544000 # Number of ticks simulated
|
||||
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 550056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 549394 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2794675827 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262632 # Number of bytes of host memory used
|
||||
host_inst_rate 485157 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 484642 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2465828156 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286540 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 546705998 # In
|
|||
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 877089479 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 28544 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 446 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
|
||||
|
|
@ -455,7 +463,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -463,11 +470,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
|
|||
sim_ticks 18662000 # Number of ticks simulated
|
||||
final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 32674 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 32664 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 235769003 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238980 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 154264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154144 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1111892278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287792 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # By
|
|||
system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1654250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7429250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1719250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 5370.94 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24120.94 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -223,17 +223,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1056264066 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 281 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 281 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 19712 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 308 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 308 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks)
|
||||
|
|
@ -376,7 +384,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1056264066 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
|
|
@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 27 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 19712 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 11765500 # Number of ticks simulated
|
||||
final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45706 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45696 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 225189511 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236100 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 81487 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 81445 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 401265305 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288836 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # By
|
|||
system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1710500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 6810500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1802000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6288.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25038.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 260000 # Ti
|
|||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 7778000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 1479580128 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 248 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 248 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 17408 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 272 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 272 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks)
|
||||
|
|
@ -577,7 +585,6 @@ system.cpu.int_regfile_writes 2774 # nu
|
|||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.toL2Bus.throughput 1479580128 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
|
|
@ -585,11 +592,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 24 # T
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks)
|
||||
|
|
@ -717,14 +734,14 @@ system.cpu.l2cache.overall_misses::total 272 # nu
|
|||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1692250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1692250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6143750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18850000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6143750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18850000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -750,14 +767,14 @@ system.cpu.l2cache.overall_miss_rate::total 1 #
|
|||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -780,14 +797,14 @@ system.cpu.l2cache.overall_mshr_misses::total 272
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1398750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1398750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5100750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15449500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5100750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15449500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -802,22 +819,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 46.118379 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 46.118379 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
|
|
@ -842,14 +859,14 @@ system.cpu.dcache.demand_misses::cpu.data 198 # n
|
|||
system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 198 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7443000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7443000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5304000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5304000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12747000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12747000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12747000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12747000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -866,14 +883,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.213592
|
|||
system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64378.787879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64378.787879 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
|
|
@ -900,12 +917,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6230250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6230250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6230250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6230250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -916,12 +933,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000001 # Nu
|
|||
sim_ticks 1297500 # Number of ticks simulated
|
||||
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 741583 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 738395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 370291096 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253628 # Number of bytes of host memory used
|
||||
host_inst_rate 828617 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 824640 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 413479924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 276508 # Number of bytes of host memory used
|
||||
host_seconds 0.00 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -35,9 +35,27 @@ system.physmem.bw_write::total 1586127168 # Wr
|
|||
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11879768786 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 15414 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.trans_dist::ReadReq 3000 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3000 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 294 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 294 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3294 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3294 # Request fanout histogram
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
|
|||
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Reference in a new issue