c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
971 lines
111 KiB
Text
971 lines
111 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.061857 # Number of seconds simulated
|
|
sim_ticks 61857343500 # Number of ticks simulated
|
|
final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 115241 # Simulator instruction rate (inst/s)
|
|
host_op_rate 202921 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 45120347 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 449832 # Number of bytes of host memory used
|
|
host_seconds 1370.94 # Real time elapsed on the host
|
|
sim_insts 157988547 # Number of instructions simulated
|
|
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 12608 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 197 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 30463 # Number of read requests accepted
|
|
system.physmem.writeReqs 197 # Number of write requests accepted
|
|
system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 1927 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 2067 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 2027 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 1932 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 2026 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 1903 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 1964 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 1863 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 1937 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 1937 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 1804 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 1796 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 1818 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 1778 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 15 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 94 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 13 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 21 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 7 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 7 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 12 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 5 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 3 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 61857329000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 30463 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 197 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 131010750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 700467000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 4313.68 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 23063.68 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.25 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 27696 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 119 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 2017525.41 # Average gap between requests
|
|
system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 55617527500 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 2065440000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 4171276250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.trans_dist::ReadReq 1465 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1462 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 197 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 28998 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 28998 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 30660 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 30660 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 43500000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 291787250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 37414357 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions.
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.workload.num_syscalls 444 # Number of system calls
|
|
system.cpu.numCycles 123714688 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 28240184 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 94568947 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1664994 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 13285380 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 63221157 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 18592313 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 54481539 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 48119118 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 475 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 30107103 24.35% 24.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 16727631 13.53% 53.68% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 16031842 12.96% 80.45% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 12684149 10.26% 90.71% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 5762402 4.66% 95.37% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 4173790 3.38% 98.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1554838 1.26% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 316998 7.53% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued
|
|
system.cpu.iq.rate 2.489411 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 4211171 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 743874544 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 312154273 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 58255906 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 31536734 # Number of branches executed
|
|
system.cpu.iew.exec_stores 33824606 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.480687 # Inst execution rate
|
|
system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 231632885 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 336126878 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 117208009 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 52857681 45.10% 45.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 10970810 9.36% 68.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 8748486 7.46% 75.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1731777 1.48% 78.66% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 117208009 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 157988547 # Number of instructions committed
|
|
system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 122219137 # Number of memory references committed
|
|
system.cpu.commit.loads 90779385 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 29309705 # Number of branches committed
|
|
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 4237596 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 419324214 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 657627212 # The number of ROB writes
|
|
system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 157988547 # Number of Instructions Simulated
|
|
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 493625450 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 240898259 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 178 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 135 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3121417500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 62 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 27848273 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1347 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 92883749 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 92883749 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 92883749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 92883749 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 92883749 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 92883749 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68956.012621 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 68956.012621 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 68956.012621 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 68956.012621 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 68956.012621 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 321 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 321 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 321 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72336999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 72336999 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72336999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 72336999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72336999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 72336999 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70503.897661 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70503.897661 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70503.897661 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 70503.897661 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 515 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 20693.420536 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319871 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 784 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1397 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27627 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913361 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 33266205 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 33266205 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1994012 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1994028 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2066654 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2066654 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 53067 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 53067 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2047079 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2047095 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2047079 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2047095 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 1010 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 455 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1465 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 30463 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71141750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31680000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 102821750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1901914500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 71141750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1933594500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 2004736250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 71141750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1933594500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 2004736250 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2076532 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2077558 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1026 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2076532 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2077558 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984405 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000228 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000734 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70437.376238 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69626.373626 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70185.494881 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.781916 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.781916 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 65808.891114 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70437.376238 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65650.171460 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 65808.891114 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 197 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58482750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26096500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84579250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58482750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556138500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1614621250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58482750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556138500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1614621250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57903.712871 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57354.945055 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.276451 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.707842 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.707842 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57903.712871 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.634842 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.699997 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 2072433 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 68459744 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 32.968354 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 144502463 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 144502463 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 37113881 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 37113881 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 68459744 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 68459744 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 68459744 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 68459744 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2753223 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861058000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 31861058000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155744 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2765155744 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 34626213744 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 34626213744 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 34626213744 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 34626213744 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 39773215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 39773215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 71212967 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 71212967 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 71212967 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 71212967 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.841068 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.841068 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.328100 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.328100 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12576.610665 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.610665 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12576.610665 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2066654 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009130500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009130500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972494 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972494 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524102994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 24524102994 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524102994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 24524102994 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.916789 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.916789 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.058269 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.058269 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.125244 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.125244 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|