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gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes 
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.056374 # Number of seconds simulated
sim_ticks 56374399500 # Number of ticks simulated
final_tick 56374399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 197105 # Simulator instruction rate (inst/s)
host_op_rate 252068 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 156689619 # Simulator tick rate (ticks/s)
host_mem_usage 315764 # Number of bytes of host memory used
host_seconds 359.78 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory
system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory
system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 146292787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 146292787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5745587 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5745587 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 95306807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 95306807 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 95306807 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 146292787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 241599593 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128862 # Number of read requests accepted
system.physmem.writeReqs 83951 # Number of write requests accepted
system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 8164 # Per bank write bursts
system.physmem.perBankRdBursts::1 8373 # Per bank write bursts
system.physmem.perBankRdBursts::2 8238 # Per bank write bursts
system.physmem.perBankRdBursts::3 8169 # Per bank write bursts
system.physmem.perBankRdBursts::4 8316 # Per bank write bursts
system.physmem.perBankRdBursts::5 8449 # Per bank write bursts
system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
system.physmem.perBankRdBursts::7 7969 # Per bank write bursts
system.physmem.perBankRdBursts::8 8071 # Per bank write bursts
system.physmem.perBankRdBursts::9 7635 # Per bank write bursts
system.physmem.perBankRdBursts::10 7816 # Per bank write bursts
system.physmem.perBankRdBursts::11 7830 # Per bank write bursts
system.physmem.perBankRdBursts::12 7881 # Per bank write bursts
system.physmem.perBankRdBursts::13 7876 # Per bank write bursts
system.physmem.perBankRdBursts::14 7976 # Per bank write bursts
system.physmem.perBankRdBursts::15 8004 # Per bank write bursts
system.physmem.perBankWrBursts::0 5186 # Per bank write bursts
system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
system.physmem.perBankWrBursts::4 5265 # Per bank write bursts
system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
system.physmem.perBankWrBursts::6 5196 # Per bank write bursts
system.physmem.perBankWrBursts::7 5049 # Per bank write bursts
system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
system.physmem.perBankWrBursts::9 5086 # Per bank write bursts
system.physmem.perBankWrBursts::10 5252 # Per bank write bursts
system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
system.physmem.perBankWrBursts::15 5224 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 56374368000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 128862 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 83951 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 126558 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2276 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5162 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5201 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38259 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 355.901827 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 215.943020 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 337.187447 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12097 31.62% 31.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 8058 21.06% 52.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4075 10.65% 63.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2806 7.33% 70.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2532 6.62% 77.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1601 4.18% 81.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1324 3.46% 84.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1160 3.03% 87.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4606 12.04% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38259 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5153 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.995537 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 361.849882 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 5150 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5153 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5153 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.286435 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.268739 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.792681 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 4505 87.42% 87.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 6 0.12% 87.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 503 9.76% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 112 2.17% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 16 0.31% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 4 0.08% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 5 0.10% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5153 # Writes before turning the bus around for reads
system.physmem.totQLat 1533288750 # Total ticks spent queuing
system.physmem.totMemAccLat 3949338750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11899.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30649.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 146.29 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 95.28 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 146.29 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 95.31 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.89 # Data bus utilization in percentage
system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing
system.physmem.readRowHits 112227 # Number of row buffer hits during reads
system.physmem.writeRowHits 62289 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.20 # Row buffer hit rate for writes
system.physmem.avgGap 264900.96 # Average gap between requests
system.physmem.pageHitRate 82.01 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 30998356250 # Time in different power states
system.physmem.memoryStateTime::REF 1882400000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 23491967500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.trans_dist::ReadReq 26583 # Transaction distribution
system.membus.trans_dist::ReadResp 26583 # Transaction distribution
system.membus.trans_dist::Writeback 83951 # Transaction distribution
system.membus.trans_dist::ReadExReq 102279 # Transaction distribution
system.membus.trans_dist::ReadExResp 102279 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 212813 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 212813 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 212813 # Request fanout histogram
system.membus.reqLayer0.occupancy 942245500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 1221409750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 2.2 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 14808790 # Number of BP lookups
system.cpu.branchPred.condPredicted 9910130 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 393084 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9534894 # Number of BTB lookups
system.cpu.branchPred.BTBHits 6736290 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 70.648819 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 112748799 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 70915127 # Number of instructions committed
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1227279 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.589912 # CPI: cycles per instruction
system.cpu.ipc 0.628966 # IPC: instructions per cycle
system.cpu.tickCycles 93715149 # Number of cycles that the object actually ticked
system.cpu.idleCycles 19033650 # Total number of cycles that the object has spent stopped
system.cpu.icache.tags.replacements 42434 # number of replacements
system.cpu.icache.tags.tagsinuse 1857.503994 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 24948244 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 560.937225 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1857.503994 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.906984 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.906984 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 50029918 # Number of tag accesses
system.cpu.icache.tags.data_accesses 50029918 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 24948244 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 24948244 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 24948244 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 24948244 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 24948244 # number of overall hits
system.cpu.icache.overall_hits::total 24948244 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses
system.cpu.icache.overall_misses::total 44477 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 894634739 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 894634739 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 894634739 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 894634739 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 894634739 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 894634739 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 24992721 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 24992721 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 24992721 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 24992721 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 24992721 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 24992721 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20114.547721 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20114.547721 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20114.547721 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20114.547721 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20114.547721 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 803759261 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 803759261 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 803759261 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 803759261 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 803759261 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 803759261 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18071.346111 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18071.346111 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18071.346111 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18071.346111 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 333420 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 333420 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 333420 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 67675739 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 268453439 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 95725 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29925.727358 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26686.334760 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3239.392599 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.814402 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098858 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.913261 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9850 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19418 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits
system.cpu.l2cache.overall_hits::total 76063 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses
system.cpu.l2cache.overall_misses::total 128934 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1985312250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1985312250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7483113000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7483113000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 9468425250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9468425250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 9468425250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9468425250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74481.795160 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74481.795160 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73163.728625 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73163.728625 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73436.217367 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.217367 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73436.217367 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks
system.cpu.l2cache.writebacks::total 83951 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1642872250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1642872250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6184053500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6184053500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7826925750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 7826925750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7826925750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 7826925750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61799.287165 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61799.287165 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60462.592517 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60462.592517 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60738.348091 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60738.348091 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 156424 # number of replacements
system.cpu.dcache.tags.tagsinuse 4068.200974 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 42664255 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.787783 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.200974 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst 0.993213 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993213 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86013136 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86013136 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.inst 22988554 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 22988554 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.inst 19643863 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 19643863 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.inst 42632417 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 42632417 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.inst 42632417 # number of overall hits
system.cpu.dcache.overall_hits::total 42632417 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.inst 206038 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 206038 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.inst 262053 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 262053 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.inst 262053 # number of overall misses
system.cpu.dcache.overall_misses::total 262053 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2150622439 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 2150622439 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15250404250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 15250404250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.inst 17401026689 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17401026689 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.inst 17401026689 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17401026689 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.inst 23044569 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23044569 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.inst 42894470 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42894470 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.inst 42894470 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 42894470 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010380 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010380 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.inst 0.006109 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.006109 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.inst 0.006109 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.006109 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38393.688101 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 38393.688101 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 74017.434891 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74017.434891 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66402.699794 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66402.699794 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66402.699794 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks
system.cpu.dcache.writebacks::total 128423 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99000 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 99000 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.inst 101533 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 101533 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.inst 101533 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 101533 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 107038 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1992994061 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1992994061 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7637775000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7637775000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9630769061 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9630769061 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9630769061 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9630769061 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37264.763117 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37264.763117 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71355.733478 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71355.733478 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59997.315356 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59997.315356 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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