c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
1138 lines
129 KiB
Plaintext
1138 lines
129 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.057713 # Number of seconds simulated
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sim_ticks 57712782000 # Number of ticks simulated
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final_tick 57712782000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 133015 # Simulator instruction rate (inst/s)
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host_op_rate 133677 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 84740771 # Simulator tick rate (ticks/s)
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host_mem_usage 440040 # Number of bytes of host memory used
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host_seconds 681.05 # Real time elapsed on the host
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sim_insts 90589798 # Number of instructions simulated
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sim_ops 91041029 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 8896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 68416 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 1042048 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1119360 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 8896 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 8896 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 73600 # Number of bytes written to this memory
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system.physmem.bytes_written::total 73600 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 139 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1069 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 16282 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 17490 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1150 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1150 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 154143 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1185457 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 18055758 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 19395357 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 154143 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 154143 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1275281 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1275281 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1275281 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 154143 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1185457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 18055758 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 20670638 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 17490 # Number of read requests accepted
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system.physmem.writeReqs 1150 # Number of write requests accepted
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system.physmem.readBursts 17490 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1150 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 1100032 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue
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system.physmem.bytesWritten 71488 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 1119360 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 73600 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 1094 # Per bank write bursts
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system.physmem.perBankRdBursts::1 953 # Per bank write bursts
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system.physmem.perBankRdBursts::2 1083 # Per bank write bursts
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system.physmem.perBankRdBursts::3 1113 # Per bank write bursts
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system.physmem.perBankRdBursts::4 1125 # Per bank write bursts
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system.physmem.perBankRdBursts::5 1235 # Per bank write bursts
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system.physmem.perBankRdBursts::6 1314 # Per bank write bursts
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system.physmem.perBankRdBursts::7 1243 # Per bank write bursts
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system.physmem.perBankRdBursts::8 1060 # Per bank write bursts
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system.physmem.perBankRdBursts::9 962 # Per bank write bursts
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system.physmem.perBankRdBursts::10 1021 # Per bank write bursts
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system.physmem.perBankRdBursts::11 923 # Per bank write bursts
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system.physmem.perBankRdBursts::12 921 # Per bank write bursts
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system.physmem.perBankRdBursts::13 987 # Per bank write bursts
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system.physmem.perBankRdBursts::14 1105 # Per bank write bursts
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system.physmem.perBankRdBursts::15 1049 # Per bank write bursts
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system.physmem.perBankWrBursts::0 72 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 62 # Per bank write bursts
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system.physmem.perBankWrBursts::3 19 # Per bank write bursts
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system.physmem.perBankWrBursts::4 14 # Per bank write bursts
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system.physmem.perBankWrBursts::5 111 # Per bank write bursts
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system.physmem.perBankWrBursts::6 193 # Per bank write bursts
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system.physmem.perBankWrBursts::7 122 # Per bank write bursts
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system.physmem.perBankWrBursts::8 49 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 68 # Per bank write bursts
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system.physmem.perBankWrBursts::11 20 # Per bank write bursts
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system.physmem.perBankWrBursts::12 15 # Per bank write bursts
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system.physmem.perBankWrBursts::13 94 # Per bank write bursts
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system.physmem.perBankWrBursts::14 168 # Per bank write bursts
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system.physmem.perBankWrBursts::15 110 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 57712604500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 17490 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1150 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 11254 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 2508 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 618 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 551 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 423 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 408 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 392 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 391 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 120 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 51 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 59 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 61 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 62 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 70 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 2975 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 393.336471 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 197.951950 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 413.488148 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1360 45.71% 45.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 404 13.58% 59.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 131 4.40% 63.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 68 2.29% 65.98% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 81 2.72% 68.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 67 2.25% 70.96% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 54 1.82% 72.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 34 1.14% 73.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 776 26.08% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 2975 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 63 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 272.444444 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 27.585882 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 1910.173610 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-511 62 98.41% 98.41% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14848-15359 1 1.59% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 63 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 63 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.730159 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.698769 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.080716 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 12 19.05% 19.05% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1 1.59% 20.63% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 46 73.02% 93.65% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 3 4.76% 98.41% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 1 1.59% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 63 # Writes before turning the bus around for reads
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system.physmem.totQLat 228948216 # Total ticks spent queuing
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system.physmem.totMemAccLat 551223216 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 85940000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 13320.24 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 32070.24 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 19.06 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 1.24 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 19.40 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 1.28 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.16 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.15 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 14.66 # Average write queue length when enqueuing
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system.physmem.readRowHits 14950 # Number of row buffer hits during reads
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system.physmem.writeRowHits 375 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes
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system.physmem.avgGap 3096169.77 # Average gap between requests
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system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 51355249007 # Time in different power states
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system.physmem.memoryStateTime::REF 1927120000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 4429633993 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.trans_dist::ReadReq 17158 # Transaction distribution
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system.membus.trans_dist::ReadResp 17158 # Transaction distribution
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system.membus.trans_dist::Writeback 1150 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
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system.membus.trans_dist::ReadExReq 332 # Transaction distribution
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system.membus.trans_dist::ReadExResp 332 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 36134 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 36134 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1192960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 1192960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 18642 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 18642 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 18642 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 32019899 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 163550691 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 28272297 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 23289786 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 837936 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 11858499 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 11790100 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 99.423207 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 75765 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 442 # Number of system calls
|
|
system.cpu.numCycles 115425565 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 745807 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 135034231 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 28272297 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 11865865 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 113822766 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1679444 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 53 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 32316581 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 456 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 115408607 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.175345 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.320714 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 57851940 50.13% 50.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 13925142 12.07% 62.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 9174755 7.95% 70.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 34456770 29.86% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 115408607 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.244940 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.169881 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8865132 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 63135589 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 33034927 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 9545475 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 827484 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 4101291 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 12346 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 114392929 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 1987160 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 827484 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 15218972 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 49233807 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 108012 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 35472939 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 14547393 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 110855235 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 1413432 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 11041669 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 1056479 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1457795 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 455993 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 129914313 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 483072528 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 119436601 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 22601394 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 21215231 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 26814209 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 5348913 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 553765 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 291016 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 109685133 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 101428277 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1059458 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 18454529 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 41507183 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 115408607 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.878862 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.000028 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 54542432 47.26% 47.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 30109521 26.09% 73.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 22147517 19.19% 92.54% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7413143 6.42% 98.96% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1195677 1.04% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 115408607 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9750275 48.86% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 9493870 47.57% 96.43% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 712253 3.57% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 71987588 70.97% 70.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 56 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 24380841 24.04% 95.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 5048955 4.98% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 101428277 # Type of FU issued
|
|
system.cpu.iq.rate 0.878733 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 19956461 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.196754 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 339280619 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 128148692 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 99657487 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 461 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 120 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 121384498 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 285190 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 4338298 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1479 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1420 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 604069 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 130354 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 827484 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 8008710 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 730406 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 109706046 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 26814209 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 5348913 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 187279 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 360662 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1420 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 436360 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 849241 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 100145631 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 23824107 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1282646 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12666 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 28742996 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 20629033 # Number of branches executed
|
|
system.cpu.iew.exec_stores 4918889 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.867621 # Inst execution rate
|
|
system.cpu.iew.wb_sent 99755826 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 99657607 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 59710820 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 95563157 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.863393 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.624831 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 17390640 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 825698 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 112714742 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.807824 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.745908 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 76462569 67.84% 67.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 18443635 16.36% 84.20% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 7118441 6.32% 90.52% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 3374531 2.99% 93.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1758227 1.56% 95.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 536893 0.48% 95.55% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 726177 0.64% 96.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 179059 0.16% 96.35% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 4115210 3.65% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 112714742 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
|
|
system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 27220755 # Number of memory references committed
|
|
system.cpu.commit.loads 22475911 # Number of loads committed
|
|
system.cpu.commit.membars 3888 # Number of memory barriers committed
|
|
system.cpu.commit.branches 18732304 # Number of branches committed
|
|
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 56148 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 4115210 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 217038076 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 219583064 # The number of ROB writes
|
|
system.cpu.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 16958 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
|
|
system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.274156 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.274156 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.784833 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.784833 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 108123919 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 58738896 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 100 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 369252810 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 58698459 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 28460470 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 5262392 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5262392 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 5407164 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 28368 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 225287 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 225287 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1832 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16380692 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 16382524 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697211456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 697270080 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 28370 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 10923218 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.002597 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.050895 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 10894850 99.74% 99.74% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 28368 0.26% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 10923218 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10854591744 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1387749 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 8230203749 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 456 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 432.039034 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 32315555 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 916 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 35278.990175 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 432.039034 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.843826 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.843826 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 64634074 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 64634074 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 32315555 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 32315555 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 32315555 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 32315555 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 32315555 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 32315555 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1024 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1024 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1024 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1024 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1024 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1024 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21430236 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 21430236 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 21430236 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 21430236 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 21430236 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 21430236 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 32316579 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 32316579 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 32316579 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 32316579 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 32316579 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 32316579 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000032 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000032 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000032 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000032 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000032 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000032 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.964844 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 20927.964844 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 20927.964844 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.964844 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 20927.964844 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 3188 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 170 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.752941 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 916 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 916 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 916 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 916 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17850739 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 17850739 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17850739 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 17850739 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17850739 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 17850739 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19487.706332 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19487.706332 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19487.706332 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 19487.706332 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 8891809 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 13933 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7995771 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 738007 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 118754 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 25344 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 15103327 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.tags.replacements 1672 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 12558.688532 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 10641390 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 17530 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 607.038791 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 10807.797190 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 104.008842 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 299.224972 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1347.657528 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.659656 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006348 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.018263 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082254 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.766522 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1557 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 14301 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 48 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 89 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1370 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 12200 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.095032 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.872864 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 174560305 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 174560305 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 753 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 5260483 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 5261236 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 5407164 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 5407164 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 224791 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 224791 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 753 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 5485274 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 5486027 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 753 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 5485274 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 5486027 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 993 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1156 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 496 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 496 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1489 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1652 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1489 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1652 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12439500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59393247 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 71832747 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31513998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 31513998 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 12439500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 90907245 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 103346745 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 12439500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 90907245 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 103346745 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 916 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 5261476 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5262392 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 5407164 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 5407164 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 225287 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 225287 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 916 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 5486763 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 5487679 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 916 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 5486763 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 5487679 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177948 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000189 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000220 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002202 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002202 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177948 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000271 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.000301 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177948 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000271 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.000301 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76315.950920 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59811.930514 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 62139.054498 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63536.286290 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63536.286290 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 62558.562349 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76315.950920 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61052.548690 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 62558.562349 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 50 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16.400000 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1150 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1150 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 256 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 162 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 162 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 418 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 442 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 418 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 442 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 139 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 737 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 876 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 25344 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 25344 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 334 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 334 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 139 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1071 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1210 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 139 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1071 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 25344 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26554 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10286000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41114499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 51400499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 910618800 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 20873252 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 20873252 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10286000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61987751 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 72273751 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10286000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61987751 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 910618800 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 982892551 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000140 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000166 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001483 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001483 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000220 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151747 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000195 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.004839 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 74000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55786.294437 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58676.368721 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35930.350379 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62494.766467 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62494.766467 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59730.372727 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57878.385621 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35930.350379 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37014.858439 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 5486251 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.841559 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 18271309 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 5486763 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 3.330071 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 27123000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.841559 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999691 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999691 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 61969579 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 61969579 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13905693 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13905693 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 4357334 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 4357334 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 18263027 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 18263027 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 18263549 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 18263549 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 9592430 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 9592430 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 377647 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 377647 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9970077 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9970077 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9970085 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9970085 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87035855746 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 87035855746 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3957576177 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 3957576177 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 283250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 283250 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 90993431923 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 90993431923 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 90993431923 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 90993431923 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23498123 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23498123 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 28233104 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 28233104 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 28233634 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 28233634 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408221 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.408221 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079757 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.079757 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.353134 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.353134 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.353128 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.353128 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9073.389719 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 9073.389719 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10479.564718 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 10479.564718 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20232.142857 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20232.142857 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9126.652876 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 9126.652876 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9126.645552 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 9126.645552 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 301384 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 67125 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 120500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 12183 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.501112 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 5.509727 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 5407164 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 5407164 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328464 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 4328464 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154855 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 154855 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4483319 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4483319 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4483319 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4483319 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263966 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 5263966 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222792 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 222792 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 5486758 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 5486758 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 5486763 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 5486763 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38232328002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 38232328002 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2158774283 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2158774283 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 284500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 284500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40391102285 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 40391102285 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40391386785 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 40391386785 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224016 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194338 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.194338 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194334 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.194334 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7263.027155 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7263.027155 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9689.640036 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9689.640036 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56900 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56900 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7361.560740 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7361.560740 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7361.605884 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7361.605884 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|