c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
1161 lines
132 KiB
Text
1161 lines
132 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.032615 # Number of seconds simulated
|
|
sim_ticks 32615215000 # Number of ticks simulated
|
|
final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 86014 # Simulator instruction rate (inst/s)
|
|
host_op_rate 110001 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 39563517 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 333060 # Number of bytes of host memory used
|
|
host_seconds 824.38 # Real time elapsed on the host
|
|
sim_insts 70907629 # Number of instructions simulated
|
|
sim_ops 90682584 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 155899 # Number of read requests accepted
|
|
system.physmem.writeReqs 98491 # Number of write requests accepted
|
|
system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 10106 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 10077 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 9750 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 10345 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 10619 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 10733 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 9548 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 9567 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 9971 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 9445 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 9639 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 9476 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 8930 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 9084 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 9062 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 9408 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 6017 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 6275 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 6171 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 6231 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 6142 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 6389 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 6054 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 6025 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 6057 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 6227 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 6350 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 5949 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 6129 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 6148 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 6212 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 6088 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 32615126500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 155899 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 98491 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 7435933847 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 3.90 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 126861 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 35985 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 128209.15 # Average gap between requests
|
|
system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 1088880000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.trans_dist::ReadReq 149976 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 149976 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 98491 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 6 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 5923 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 5923 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 254396 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 254396 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 3.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 4.4 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 17209876 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
|
system.cpu.numCycles 65230431 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued
|
|
system.cpu.iq.rate 1.454233 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9866 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 14252629 # Number of branches executed
|
|
system.cpu.iew.exec_stores 20981511 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.440176 # Inst execution rate
|
|
system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 44933898 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
|
|
system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 43422000 # Number of memory references committed
|
|
system.cpu.commit.loads 22866262 # Number of loads committed
|
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
|
system.cpu.commit.branches 13741485 # Number of branches committed
|
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 81528487 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 157213253 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 195483387 # The number of ROB writes
|
|
system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
|
|
system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 102236516 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 56794814 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 36 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 21 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 261186 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 323466 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 22431935 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 331634 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.tags.replacements 140078 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16107.104250 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 874451 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 156393 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 5.591369 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 11482.142430 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 301.953059 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 1690.013125 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 234 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2751 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11585 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 388 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 623 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.053040 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942749 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 17367214 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 17367214 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 320997 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 306363 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 627360 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 256573 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 256573 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 139690 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 139690 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 320997 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 446053 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 767050 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 320997 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 446053 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 767050 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2981 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 30906 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 33887 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 8871 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 8871 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2981 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 39777 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 42758 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2981 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 39777 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 42758 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232061970 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2519217993 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2751279963 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950040000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 950040000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 232061970 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 3469257993 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 3701319963 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 232061970 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 3469257993 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 3701319963 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 323978 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 337269 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 661247 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 256573 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 256573 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 148561 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 148561 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 323978 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 485830 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 809808 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 323978 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 485830 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 809808 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.009201 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.091636 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.051247 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.059713 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.059713 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.009201 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.081874 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.052800 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.009201 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.081874 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.052800 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77847.021134 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81512.262765 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81189.835719 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107095.028745 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107095.028745 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 86564.384747 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 86564.384747 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 3458 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 119 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.058824 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 98491 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 98491 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 910 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 298 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1208 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2953 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 2953 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 910 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 3251 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 4161 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 910 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 3251 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 4161 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2071 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30608 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 32679 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 199121 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 199121 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 5918 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 5918 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2071 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 36526 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 38597 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2071 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 36526 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 199121 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 237718 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159067500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2245450503 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2404518003 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 12215795775 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36006 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36006 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 395713000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 395713000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159067500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 485318 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 40412396 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1633057 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 256573 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|