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Author SHA1 Message Date
Gabe Black 09cc401848 ARM: Implement the ubfx and sbfx instructions. 2010-06-02 12:58:08 -05:00
Gabe Black b1158e4938 ARM: Add a register, immediate, immediate to register base for [su]bfx. 2010-06-02 12:58:08 -05:00
Gabe Black 504ac6518b ARM: Decode the clz instruction. 2010-06-02 12:58:08 -05:00
Gabe Black 2c94bf7f30 ARM: Implement the clz instruction. 2010-06-02 12:58:08 -05:00
Gabe Black 00320a53ab ARM: Decode the rbit instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 5cc1bb6842 ARM: Implement the rbit instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 566b2ff20c ARM: Decode the nop instruction. 2010-06-02 12:58:07 -05:00
Gabe Black b9cfe9a3db ARM: Implement nop. 2010-06-02 12:58:07 -05:00
Gabe Black a2d8dcebba ARM: Decode the ldrex instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 952253483b ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. 2010-06-02 12:58:07 -05:00
Gabe Black f7f75ad053 ARM: Implement the ldrex instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 00baeb742d ARM: Decode the usad8 and usada8 instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 8f566e5ee3 ARM: Implement the usad8 and usada8 instructions. 2010-06-02 12:58:07 -05:00
Gabe Black c643b1c274 ARM: Add a base class to support usada8. 2010-06-02 12:58:07 -05:00
Gabe Black 64ade8316e ARM: Decode the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 7fa6835a0c ARM: Implement the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black 498f9d925e ARM: Add a base class for the sel instruction. 2010-06-02 12:58:07 -05:00
Gabe Black f581fd3f89 ARM: Decode pkh instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 9ffc5e2ae6 ARM: Implement the pkh instruction. 2010-06-02 12:58:07 -05:00
Gabe Black c4d09747a5 ARM: Decode the sign/zero extend instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 69365876d8 ARM: Implement zero/sign extend instructions. 2010-06-02 12:58:07 -05:00
Gabe Black 554fb3774e ARM: Add a base class for extend and add instructions. 2010-06-02 12:58:07 -05:00
Gabe Black cb2e3b0ace ARM: Generalize the saturation instruction bases for use in other instructions. 2010-06-02 12:58:07 -05:00
Gabe Black a1208aa66d ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions. 2010-06-02 12:58:07 -05:00
Gabe Black cabf766a06 ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 82614b6f3a ARM: Fix signed most significant multiply instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 3cff58602a ARM: Fix multiply overflow flag setting. 2010-06-02 12:58:06 -05:00
Gabe Black 90c2284714 ARM: Decode the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 61b8e33225 ARM: Implement the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black c96f03a250 ARM: Implement base classes for the saturation instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 0aff168f1a ARM: Decode the signed add/subtract and subtract/add instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 8ba812f1fb ARM: Implement signed add/subtract and subtract/add. 2010-06-02 12:58:06 -05:00
Gabe Black a895514d35 ARM: Decode the unsigned 8 and 16 bit add and subtract instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 3f12eb02ab ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts. 2010-06-02 12:58:06 -05:00
Gabe Black 29acf9516c ARM: Decode the unsigned saturating instructions. 2010-06-02 12:58:06 -05:00
Gabe Black be888e67e7 ARM: Implement the unsigned saturating instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 5495ebd68d ARM: Decode the ssub instructions. 2010-06-02 12:58:06 -05:00
Gabe Black fd6e9f304e ARM: Implement the ssub instructions. 2010-06-02 12:58:06 -05:00
Gabe Black bcf0454864 ARM: Decode the SADD8 and SADD16 instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 87975aa691 ARM: Implement the SADD8 and SADD16 instructions. 2010-06-02 12:58:06 -05:00
Gabe Black d70c31437a ARM: Support instructions that set the GE bits when they write the condition codes. 2010-06-02 12:58:06 -05:00
Gabe Black e32aaefe8c ARM: Decode 32 bit thumb data processing register instructions. 2010-06-02 12:58:06 -05:00
Gabe Black f19b605aed ARM: Decode the 16 bit thumb versions of the REV* instructions. 2010-06-02 12:58:06 -05:00
Gabe Black 15356af288 ARM: Decode the ARM version of the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 59c726b6f4 ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format. 2010-06-02 12:58:05 -05:00
Gabe Black aa8493d7d1 ARM: Implement the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black c981a4de2b ARM: Add base classes suitable for the REV* instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 57443a2144 ARM: Make LDM that loads the PC perform an interworking branch. 2010-06-02 12:58:05 -05:00
Gabe Black 1344fc2668 ARM: Decode the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black e157b1f52a ARM: Implement the swp and swpb instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 1884ed65bd ARM: Decode MRS and MSR for thumb. 2010-06-02 12:58:05 -05:00
Gabe Black ff3b21bc2b ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. 2010-06-02 12:58:05 -05:00
Gabe Black f0811eb208 ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black f61bb9adb9 ARM: Hook up the push/pop versions of stm/ldm in thumb. 2010-06-02 12:58:05 -05:00
Gabe Black a76ab8e040 ARM: Hook SVC into the thumb decoder. 2010-06-02 12:58:05 -05:00
Gabe Black cbdebf852e ARM: Implement SVC (was SWI) outside of the decoder. 2010-06-02 12:58:05 -05:00
Gabe Black 34032f97d6 ARM: Trigger system calls from the SupervisorCall invoke method. 
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
 2010-06-02 12:58:05 -05:00
Gabe Black 52460938cb ARM: Fix multiply operations. 
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
 2010-06-02 12:58:05 -05:00
Gabe Black 4fb6fcd82d ARM: Decode the scalar saturating add/subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 30dd622622 ARM: Decode the parallel add and subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black 62e8487d57 ARM: Implement signed saturating add and/or subtract instructions. 2010-06-02 12:58:05 -05:00
Gabe Black a1253ec644 ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). 2010-06-02 12:58:05 -05:00
Gabe Black 61b00d3224 ARM: Decode unconditional ARM instructions. 2010-06-02 12:58:04 -05:00
Gabe Black b6e2f5d33f ARM: Make sure ldm exception return writes back its base in the right mode. 
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
 2010-06-02 12:58:04 -05:00
Gabe Black 89060f1fd8 ARM: Rework how unrecognized/unimplemented instructions are handled. 
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
 2010-06-02 12:58:04 -05:00
Gabe Black aa45fafb2e ARM: Add support for "SUBS PC, LR and related instructions". 2010-06-02 12:58:04 -05:00
Gabe Black 2419903dc0 ARM: Make ldrs into the PC and ldm exception return do interworking branches. 2010-06-02 12:58:04 -05:00
Gabe Black 28227440a7 ARM: Align the PC when using it as the base for a load. 2010-06-02 12:58:04 -05:00
Gabe Black d63f748b53 ARM: Implement ADR as separate from ADD. 2010-06-02 12:58:04 -05:00
Gabe Black e92dc21fde ARM: Add support for interworking branch ALU instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 11c3361be4 ARM: Fix when the flag bits are updated for thumb. 2010-06-02 12:58:04 -05:00
Gabe Black 14d25fbad0 ARM: Don't rely on undefined behavior to get arithmetic right shift. 
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
 2010-06-02 12:58:04 -05:00
Gabe Black 05d880f7a1 ARM: Restrict the shift amount from a register to 8 bits. 
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
 2010-06-02 12:58:04 -05:00
Gabe Black 9ebaf8ecd5 ARM: Define the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 3f83094af2 ARM: Decode the VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 647edea970 ARM: Fix the constant describing the number of floating point registers. 2010-06-02 12:58:04 -05:00
Gabe Black 2f3102f1ef ARM: Add templates for VFP load/store multiple instructions. 2010-06-02 12:58:04 -05:00
Gabe Black 739f23c64c ARM: Add base classes for VFP load/store multiple. 2010-06-02 12:58:04 -05:00
Gabe Black cb631d87c3 ARM: Add floating point load/store microops. 2010-06-02 12:58:04 -05:00
Gabe Black 3a11412c99 ARM: Add an fp version of one of the microop indexed registers. 2010-06-02 12:58:04 -05:00
Gabe Black d5aee75efe ARM: Move the mmap region to where Linux actually has it. 2010-06-02 12:58:04 -05:00
Gabe Black a8eb9d521c ARM: Eliminate the unused rhi and rlo operands. 2010-06-02 12:58:03 -05:00
Gabe Black b02c7f1bcd ARM: Move the macro mem constructor out of the isa desc. 
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
 2010-06-02 12:58:03 -05:00
Gabe Black 7b62e9ad71 ARM: Make macroops panic if executed directly. 
The macroop should never be executed, only it's microops will.
 2010-06-02 12:58:03 -05:00
Ali Saidi 8fadf2691d ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs. 2010-06-02 12:58:03 -05:00
Gabe Black f18040a205 ARM: Split out the "basic" templates and format. 
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
 2010-06-02 12:58:03 -05:00
Gabe Black c175f1b993 ARM: Remove unnecessary cruft from includes.isa. 2010-06-02 12:58:03 -05:00
Gabe Black e29ec7d2ed ARM: Move the inst2string function out of the isa_desc. 
Delete the now empty formats/util.isa.
 2010-06-02 12:58:03 -05:00
Gabe Black ae135228fc ARM: Get rid of the unused ArmGenericCodeSubs. 2010-06-02 12:58:03 -05:00
Gabe Black 8c012e9571 ARM: Make the predecoder print out the ExtMachInst it gathered when traced. 2010-06-02 12:58:03 -05:00
Gabe Black 458bd025d4 ARM: Remove special naming for the new version of multiply. 2010-06-02 12:58:03 -05:00
Gabe Black 2196f75a25 ARM: Hook the new multiply instructions into all the decoders. 2010-06-02 12:58:03 -05:00
Gabe Black 33da368e99 ARM: Implement all integer multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 50229be27f ARM: Add templates for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black 3430b34cff ARM: Add base classes for multiply instructions. 2010-06-02 12:58:03 -05:00
Gabe Black c7d2f43641 ARM: Decode plain binary immediate thumb data processing instructions. 2010-06-02 12:58:03 -05:00
Gabe Black dcf218155d ARM: Define a new "movt" data processing instruction. 2010-06-02 12:58:03 -05:00
Gabe Black b615ed1470 ARM: Hook the new branch instructions into the 32 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black 274badd201 ARM: Hook the new branch instructions into the 16 bit thumb decoder. 2010-06-02 12:58:03 -05:00
Gabe Black b6b2f8891a ARM: Eliminate the old style branch instructions. 2010-06-02 12:58:03 -05:00
Gabe Black d082705b01 ARM: Hook the new branch instructions into the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black 9869343636 ARM: Implement branch instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black a6c1c8debb ARM: Add new templates for branch instructions. 2010-06-02 12:58:02 -05:00
Gabe Black ef3972eaae ARM: Implement new base classes for branches. 2010-06-02 12:58:02 -05:00
Gabe Black 769f3406fe ARM: Replace the interworking branch base class with a special operand. 2010-06-02 12:58:02 -05:00
Gabe Black b6e7029dd5 ARM: Fix PC operand handling. 2010-06-02 12:58:02 -05:00
Gabe Black 7eb3ea2798 ARM: Remove the special naming from the new version of data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 4f08b52af2 ARM: Get rid of unnecessary flag calculating functions. 2010-06-02 12:58:02 -05:00
Gabe Black bf903ec9a1 ARM: Get rid of the unused Jump format. 2010-06-02 12:58:02 -05:00
Gabe Black 36ca0658a4 ARM: Get rid of obsoleted predicated inst formats, etc. 2010-06-02 12:58:02 -05:00
Gabe Black 7939b48265 ARM: Implement disassembly for the new data processing classes. 2010-06-02 12:58:02 -05:00
Gabe Black b66e3aec43 ARM: Hook the external data processing instructions into the Thumb decoder. 2010-06-02 12:58:02 -05:00
Gabe Black beb759912b ARM: Move the modified_imm function from all ARM instructions to just data processing ones. 2010-06-02 12:58:02 -05:00
Gabe Black 8136cb3605 ARM: Hook the new external data processing instructions to the ARM decoder. 2010-06-02 12:58:02 -05:00
Gabe Black bf45d44cbe ARM: Implement data processing instructions external to the decoder. 2010-06-02 12:58:02 -05:00
Gabe Black c02f9cdddf ARM: Add new base classes for data processing instructions. 2010-06-02 12:58:02 -05:00
Gabe Black 1e7b317a98 ARM: Hook up 32 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 64d6b6ebfd ARM: Hook up 16 bit thumb load/store multiple. 2010-06-02 12:58:02 -05:00
Gabe Black 51bde086d5 ARM: Reimplement load/store multiple external to the decoder. 
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
 2010-06-02 12:58:02 -05:00
Gabe Black 93a3714816 ARM: Move the templates for predicated instructions into a separate file. 
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 04300e33d4 ARM: Remove the special naming for the new memory instructions. 
These are the only memory instructions now.
 2010-06-02 12:58:01 -05:00
Gabe Black deb6e8f805 ARM: Eliminate the old memory formats which are no longer used. 2010-06-02 12:58:01 -05:00
Gabe Black 1905024766 ARM: Eliminate decoding for the very deprecated FPA instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 55465844dc ARM: Make the addressing mode 3 loads/stores use the externally defined instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 36b6ca2ce3 ARM: Pull double memory instructions out of the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional. 
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
 2010-06-02 12:58:01 -05:00
Gabe Black a86491fbf2 ARM: Decode 16 bit thumb PC relative memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black dc8af1b211 ARM: Decode 16 bit thumb immediate addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 4bbd73649d ARM: Decode 16 bit thumb register addressed memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 462cf6f49b ARM: Make single stores decode to the new external store instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b0f3b1ee2 ARM: Add a .w to the disassembly of 32 bit thumb instructions. 
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
 2010-06-02 12:58:01 -05:00
Gabe Black fde3c8f41d ARM: Make 32 bit thumb use the new, external load instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 3b93015304 ARM: Define the store instructions from outside the decoder. 
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 81fdced83f ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
Gabe Black 321d3a6e8c ARM: Implement a new set of base classes for non macro memory instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 8933857af7 ARM: Create a "decoder" directory for the files implementing the decoder. 
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
 2010-06-02 12:58:01 -05:00
Gabe Black 4ebd44dc4f ARM: Flesh out the 32 bit thumb store single instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 386424ccb5 ARM: Implement the 32 bit thumb load word instructions. 2010-06-02 12:58:01 -05:00
Gabe Black 292b8a3c91 ARM: Add an operand for accessing the current PC. 2010-06-02 12:58:00 -05:00
Gabe Black 003346077f ARM: Flesh out 32 bit thumb load word decoding. 2010-06-02 12:58:00 -05:00
Gabe Black 0d4c4cacab ARM: Implement some 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bd8812cf99 ARM: Replace the "never" condition with the "unconditional" condition. 2010-06-02 12:58:00 -05:00
Gabe Black af91d27271 ARM: Add a base class for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black bfe1a194dd ARM: Add a function to decode 32 bit thumb immediate values. 2010-06-02 12:58:00 -05:00
Gabe Black 0116655674 ARM: Expand the decoding for 32 bit thumb data processing immediate instructions. 2010-06-02 12:58:00 -05:00
Gabe Black cef2e8ecee ARM: Stub out the 32 bit Thumb portion of the decoder. 2010-06-02 12:58:00 -05:00
Gabe Black 659f8d021f ARM: Add bitfields for 32 bit thumb. 2010-06-02 12:58:00 -05:00
Gabe Black bc6ae010c9 ARM: Decode VFP instructions. 2010-06-02 12:58:00 -05:00
Gabe Black 7b8525287d ARM: Stub out the 16 bit thumb decoder. 2010-06-02 12:58:00 -05:00
Gabe Black aaa619ea23 ARM: Add thumb bitfields to the ExtMachInst and the isa definition. 2010-06-02 12:58:00 -05:00
Gabe Black a1838f2c79 ARM: Make the decoder handle thumb instructions separately. 
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
 2010-06-02 12:58:00 -05:00
Gabe Black 0dffd8ce79 ARM: Add a thumb bit bitfield. 2010-06-02 12:58:00 -05:00
Gabe Black 96be7e16c1 ARM: Make the predecoder handle Thumb instructions. 2010-06-02 12:58:00 -05:00
Gabe Black f49cdb4f5d ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. 2010-06-02 12:58:00 -05:00
Gabe Black 330d9d4dbc ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. 2010-06-02 12:58:00 -05:00
Gabe Black a59d219989 ARM: Add a bit to the ExtMachInst to select thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black 4ddeceba96 ARM: Allow ARM processes to start in Thumb mode. 2010-06-02 12:58:00 -05:00
Gabe Black 3951afd2fa ARM: Detect thumb mode elf images. 2010-06-02 12:58:00 -05:00
Gabe Black ebb273bb7b ARM: Add a new base class for instructions that can do an interworking branch. 2010-06-02 12:57:59 -05:00
Gabe Black 9ef82c0bc4 ARM: Track the current ISA mode using the PC. 2010-06-02 12:57:59 -05:00
Gabe Black 1c0d9806e5 ARM: Fix custom writer/reader code for non indexed operands. 2010-06-02 12:57:59 -05:00
Gabe Black 4b87bc887a ARM: Remove IsControl from operands that don't imply control transfers. 
Also remove IsInteger from CondCodes.
 2010-06-02 12:57:59 -05:00
Ali Saidi 322f345b51 ARM: Adjust some copyrights 2010-06-02 12:57:59 -05:00
Nathan Binkert c1aabe8172 style: clean up ruby's Set class 
Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.

There are probably several cases where this class is used, std::bitset
could be used instead.
 2010-06-01 11:38:56 -07:00
Nathan Binkert bb589d463b x86: put back code that I accidentally deleted 2010-05-25 20:15:44 -07:00
Nathan Binkert 13d64906c2 copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
Gabe Black c5c559b6ab SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
Ali Saidi 72071690e7 Automated merge with ssh://m5sim.org//repo/m5 2010-05-13 23:48:06 -04:00
Maximilien Breughe fc746c2268 BPRED: Fixed the treshold-bug in the tournament predictor. 
Suppose the saturating counters of a branch predictor contain n bits.  When the
counter is between 0 and (2^(n-1) - 1), boundaries included, the branch is
predicted as not taken.  When the counter is between 2^(n-1) and (2^n - 1),
boundaries included, the branch is predicted as taken.
 2010-05-13 23:45:57 -04:00
Gabe Black c4497dbf03 X86: Make the cvti2f microop sign extend its integer source correctly. 
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
 2010-05-12 00:51:35 -07:00
Gabe Black cc76842f83 X86: Actual change that fixes div. How did that happen? 2010-05-12 00:49:12 -07:00
Nathan Binkert c4057a13f1 macos: MacOS has deprecated getdirentries, so just disable the code. 
Hopefully it isn't used much
 2010-05-06 08:42:21 -07:00
Nathan Binkert f07ee128cc compile: don't #include unnecessary stuff 
Time from base/time.hh has a name clash with Time from Ruby's
TypeDefines.hh.  Eventually Ruby's Time should go away, so instead of
fixing this properly just try to avoid the clash.
 2010-05-06 08:42:18 -07:00
Gabe Black 2ee7a89209 X86: Update the base aux vector X86 processes install. 2010-05-03 00:44:08 -07:00
Gabe Black 7524fdda6a X86: Sometimes CPUID depends on ecx, so pass that in. 2010-05-02 00:40:17 -07:00
Gabe Black 51a3d65e25 X86: Finally fix a division corner case. 
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
 2010-05-02 00:39:29 -07:00
Nathan Binkert 82fb350f9a stats: make simTicks and simFreq accessible from stats.hh 2010-04-18 13:23:25 -07:00
Nathan Binkert 50bf3895b0 callback: Make helper functions that create callback objects for you 
clean up callback stuff a little bit while we're at it.
 2010-04-18 13:23:25 -07:00
Nathan Binkert 12fc22571c event: Allow EventWrapper to take an object reference 2010-04-18 13:23:24 -07:00
Nathan Binkert 4225a68a95 scons: don't maintain files in sorted order 
This causes builds to happen in sorted order rather than in
declaration order. This gets annoying when you make a global change
and then you notice that the files that are being compiled are jumping
around the directory hierarchy.
 2010-04-15 16:25:14 -07:00
Nathan Binkert e99828b06a tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
Nathan Binkert f7e6f19ada eventq: move EventQueue constructor to cc file 
Also make copy constructor and assignment operator private.
 2010-04-15 16:24:10 -07:00
Korey Sewell b49511ae48 inorder: timing for inst forwarding 
when insts execute, they mark the time they finish to be used for subsequent isnts
they may need forwarding of data. However, the regdepmap was using the wrong
value to index into the destination operands of the instruction to be forwarded.
Thus, in some cases, we are checking to see if the 3rd destination register
for an instruction is executed at a certain time, when there is only 1 dest. register
valid. Thus, we get a bad, uninitialized time value that will stall forwarding
causing performance loss but still the correct execution.
 2010-04-10 23:31:36 -04:00
Nathan Binkert d71f9712b3 eventq: allow an implicit cast from an EventManager to an EventQueue * 2010-04-02 15:28:22 -07:00
Nathan Binkert f32674d9bc eventq: Clean up some flags 
- Make the initialized flag always available, not just in debug mode.
- Make the Initialized flag actually use several bits so it is very
unlikely that something that's uninitialized accidentally looks
initialized.
- Add an initialized() function that tells you if the current event is
indeed  initialized.
- Clear the flags on delete so it can't be accidentally thought of as
initialized.
- Fix getFlags assert statement.  "How did this ever work?"
 2010-04-02 15:28:22 -07:00
Nathan Binkert 2ee3edba8e eventq: Make priorities just an integer instead of an enum. 
Symbolic names should still be used, but this makes it easier to do
things like:
Event::Priority MyObject_Pri = Event::Default_Pri + 1

Remember that higher numbers are lower priority (should we fix this?)
 2010-04-02 15:28:21 -07:00
Nathan Binkert 01dffaa32f refcnt: no default copy contructor or copy operator 
We shouldn't allow these because the default versions will copy
the reference count which is definitely not what we want.
 2010-04-02 11:20:32 -07:00
Nathan Binkert 141f61d83a ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base 2010-04-02 11:20:32 -07:00
Nathan Binkert f1c3f3044b ruby: get "using namespace" out of headers 
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them.  Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
 2010-04-02 11:20:32 -07:00
Nathan Binkert be10204729 style: another ruby style pass 2010-03-31 16:56:45 -07:00
Nathan Binkert 60ae1d2b10 style: cleanup the Ruby Tester 2010-03-29 20:39:02 -04:00
Korey Sewell 1c98bc5a56 m5: merge inorder updates 2010-03-27 02:23:00 -04:00
Korey Sewell ac316d45e8 inorder: write-hints bug fix 
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values
 2010-03-27 01:40:05 -04:00
Timothy M. Jones 6b293c73fd CPU: Added comments to address translation classes. 2010-03-25 12:43:52 +00:00
Nathan Binkert a2652a048a ruby: continue style pass 2010-03-23 22:49:43 -07:00
Steve Reinhardt f066bfc2f5 cpu: get rid of uncached access "events" 
These recordEvent() calls could cause crashes since they
access the req pointer after it's potentially been
deleted during a failed translation call.  (Similar
problem to the traceData bug fixed in the previous cset.)

Moving them above the translation call (as was done
recentlyi in cset 8b2b8e5e7d35) avoids the crash
but doesn't work, since at that point we don't know if
the access is uncached or not.

It's not clear why these calls are there, and no one
seems to use them, so we'll just delete them.  If they
are needed, they should be moved to somewhere that's
guaranteed to be after the translation completes but
before the request is possibly deleted, e.g., in
finishTranslation().
 2010-03-23 08:50:59 -07:00
Steve Reinhardt 4d77ea7a57 cpu: fix exec tracing memory corruption bug 
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.

It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical.  Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.

This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition.  It also moves those calls above
the translation calls to eliminate the crashes.
 2010-03-23 08:50:57 -07:00
Nathan Binkert 5ab13e2deb ruby: style pass 2010-03-22 18:43:53 -07:00
Korey Sewell 2620e08722 inorder: import name for addtl. bpred stats 2010-03-22 17:19:48 -04:00
Maximilien Breughe 0170e851de inorder: fix squash bug in branch predictor 2010-03-22 16:59:12 -04:00