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Author SHA1 Message Date
Korey Sewell 4d749472e3 inorder: enforce stage bandwidth 
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
 2010-01-31 18:28:31 -05:00
Korey Sewell b4e0ef7837 inorder: set thread status' 
set Active/Suspended/Halted status for threads.  useful for system when determining
if/when to exit simulation
 2010-01-31 18:28:12 -05:00
Korey Sewell 5e0b8337ed inorder: add/remove halt/deallocate context respectively 
Halt is called from the exit() system call while
deallocate is unused. So to clear up things, just
use halt and remove deallocate.
 2010-01-31 18:28:05 -05:00
Korey Sewell 069b38c0d5 inorder: track last branch committed 
when threads are switching in/out the CPU, we need to keep
track of special cases like branches. Add appropriate
variables in ThreadState t track this and then use
these variables when updating pc after context switch
 2010-01-31 18:27:58 -05:00
Korey Sewell aacc5cb205 inorder: add updatePC event to resPool 
this will be used for when a thread comes back from a cache miss, it needs to update the PCs
because the inst might of been a branch or delayslot in which the next PC isnt always
a straight addition
 2010-01-31 18:27:49 -05:00
Korey Sewell 90d3b45a56 inorder: ready thread wakeup 
allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
 2010-01-31 18:27:38 -05:00
Korey Sewell 3eb04b4ad7 inorder: add threadmodel flag 
this prints out messages relative to what
threading model is being used (smt, switch-on-miss, single, etc.)
 2010-01-31 18:27:25 -05:00
Korey Sewell 611a8642c2 inorder: mem. mgmt. update 
update address List and address Map to take
into account multiple threads
 2010-01-31 18:27:12 -05:00
Korey Sewell 4dbc2f1718 inorder: suspend in respool 
give resources their own specific
activity to do for a "suspend" event
instead of defaulting to deactivating the thread for a
suspend thread event. This really matters
for the fetch sequence unit which wants to remove the
thread from fetching while other units want to
ignore a thread suspension. If you deactivate a thread
in a resource then you may lose some of the allotted
bandwidth that the thread is taking up...
 2010-01-31 18:27:02 -05:00
Korey Sewell 4ea296e296 inorder: fetch thread bug 
dont check total # of threads but instead all
active threads
 2010-01-31 18:26:54 -05:00
Korey Sewell 96b493d315 inorder: ready/suspend status fns 
update/add in the use of isThreadReady & isThreadSuspended
functions.Check in activateThread what list a thread is
on so it can be managed accordingly.
 2010-01-31 18:26:47 -05:00
Korey Sewell d9eaa2fe21 inorder-cleanup: remove unused thread functions 2010-01-31 18:26:40 -05:00
Korey Sewell e1fcc64980 inorder: activate thread on cache miss 
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
 2010-01-31 18:26:32 -05:00
Korey Sewell 4a945aab19 inorder: add event priority offset 
allow for events to schedule themselves later if desired. this is important
because of cases like where you need to activate a thread only after the previous
thread has been deactivated. The ordering there has to be enforced
 2010-01-31 18:26:26 -05:00
Korey Sewell eac5eac67a inorder: squash on memory stall 
add code to recognize memory stalls in resources and the pipeline as well
as squash a thread if there is a stall and we are in the switch on cache miss
model
 2010-01-31 18:26:13 -05:00
Korey Sewell d8e0935af2 inorder: add insts to cpu event 
some events are going to need instruction data when they process, so just
include the instruction in the event construction
 2010-01-31 18:26:03 -05:00
Korey Sewell e8312ab6f7 inorder: switch out buffer 
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
 2010-01-31 18:25:48 -05:00
Korey Sewell a892af7b26 inorder: dont allow early loads 
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
 2010-01-31 18:25:27 -05:00
Korey Sewell 0e96798fe0 configs/inorder: add options for switch-on-miss to inorder cpu 2010-01-31 18:25:13 -05:00
Korey Sewell 7b3b362ba5 inorder: init internal debug cpu counters 
- cpuEventNum
- resReqCount
 2010-01-31 17:18:15 -05:00
Brad Beckmann 45230a4f6b ruby: added the GEMS ruby tester 2010-01-29 20:29:23 -08:00
Lisa Hsu 9f63548478 since totalInstructions() is impl'ed by all the cpus, make it an abstract base class. 2010-01-12 10:22:46 -08:00
Brad Beckmann b5d2052fa0 m5: Fixed bug in atomic cpu destructor 2009-11-18 13:55:58 -08:00
Gabe Black b8120f6c38 Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
Nathan Binkert 2c5fe6f95e build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
Steve Reinhardt fbfe92b5b8 o3: get rid of unused physmem pointer 2009-11-04 14:23:25 -08:00
Timothy M. Jones 835a55e7f3 POWER: Add support for the Power ISA 
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
 2009-10-27 09:24:39 -07:00
Gabe Black 010b13c937 ISA: Fix compilation. 2009-10-17 01:13:41 -07:00
Brad Beckmann 28204b2a96 fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread 2009-10-15 15:15:24 -07:00
Korey Sewell f09f84da6e inorder-debug: print out workload 2009-10-01 09:35:06 -04:00
Lisa Hsu 1290a5f340 commit Soumyaroop's bug catch about max_insts_all_threads 2009-09-29 18:03:10 -04:00
Steve Reinhardt 4bec4702e9 O3: Add flag to control whether faulting instructions are traced. 
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
 2009-09-26 10:50:50 -07:00
Steve Reinhardt f28ea7a6c9 O3: Mark fetch stage as active if it faults. 
Otherwise if the rest of the pipeline is idle then
fault will never propagate to commit to be handled,
causing CPU to deadlock.
 2009-09-26 10:50:50 -07:00
Korey Sewell 25d1f2728a inorder-debug: fix cpu tick debug message 2009-09-25 11:18:55 -04:00
Nathan Binkert d9f39c8ce7 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
Nathan Binkert 9a8cb7db7e python: Move more code into m5.util allow SCons to use that code. 
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.

--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
 2009-09-22 15:24:16 -07:00
Korey Sewell 6f7e196113 inorder-mdu: multiplier latency fix 
mdu was workign incorrectly for 4+ latency due to incorrectly assuming
multiply was finished the next stage
 2009-09-17 15:45:27 -04:00
Soumyaroop Roy 83eebe0464 inorder-smt: remove hardcoded values 
allows for the 2T hello world example to work in inorder model
 2009-09-16 09:47:38 -04:00
Korey Sewell badb2382a8 inorder-alpha-fs: edit inorder model to compile FS mode 2009-09-15 01:44:48 -04:00
Polina Dudnik ca0e0c3683 SCons fix to always make MemTest object 2009-09-01 10:38:25 -05:00
Gabe Black ce63e50364 Atomic CPU: Respect the NO_ACCESS request flag. 2009-08-23 14:15:15 -07:00
Steve Reinhardt a13a706a20 Fix setting of INST_FETCH flag for O3 CPU. 
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
 2009-08-01 22:50:14 -07:00
Gabe Black 2871a13ab3 Simple CPU: Make the simple CPU handle the IntRegs trace flag. 2009-07-29 00:15:26 -07:00
Gabe Black 8ec235c7b1 ARM: Make native trace print out what instruction caused an error. 2009-07-27 00:54:09 -07:00
Korey Sewell 44f80e7ca5 o3-smt: enforce numThreads parameter for SMT SE mode 2009-07-25 00:50:27 -04:00
Gabe Black 3e8e813218 CPU: Separate out native trace into ISA (in)dependent code and SimObjects. 
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
 2009-07-19 23:54:56 -07:00
Gabe Black c9a27d85b9 Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
Gabe Black b398b8ff1b Registers: Add a registers.hh file as an ISA switched header. 
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
 2009-07-08 23:02:21 -07:00
Gabe Black 5c37d10624 Registers: Eliminate the ISA defined RegFile class. 2009-07-08 23:02:21 -07:00
Gabe Black 43345bff6c Registers: Move the PCs out of the ISAs and into the CPUs. 2009-07-08 23:02:21 -07:00
Gabe Black 1b29f1621d ARM, Simple CPU: Fix an index and add assert checks. 2009-07-08 23:02:21 -07:00
Gabe Black a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black 0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black 25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black 32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile. 
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
 2009-07-08 23:02:20 -07:00
Nathan Binkert 6faf377b53 types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
Nathan Binkert 4e34266245 move: put predictor includes and cc files into the same place 
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
 2009-06-04 21:50:20 -07:00
Nathan Binkert 47877cf2db types: add a type for thread IDs and try to use it everywhere 2009-05-26 09:23:13 -07:00
Nathan Binkert 8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert eef3a2e142 types: Move stuff for global types into src/base/types.hh 
--HG--
rename : src/sim/host.hh => src/base/types.hh
 2009-05-17 14:34:50 -07:00
Korey Sewell a032d91016 cpus: add InOrderCPU to default build 
regressions need this so they build the model
 2009-05-12 20:55:21 -04:00
Korey Sewell 6c88730540 inorder-resources: delete events 
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
 2009-05-12 15:01:16 -04:00
Korey Sewell db2b721380 inorder-tlb-cunit: merge the TLB as implicit to any memory access 
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
 2009-05-12 15:01:16 -04:00
Korey Sewell 3a057bdbb1 inorder-tlb: squash insts in TLB correctly 
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
 2009-05-12 15:01:16 -04:00
Korey Sewell f1c97e830b inorder-faults: ignore unalign translation faults for prefetches 2009-05-12 15:01:16 -04:00
Korey Sewell fe4cd9847d inorder-stc: update interface to handle store conditionals 2009-05-12 15:01:15 -04:00
Korey Sewell 6211fe5d2e inorder-float: Fix storage of FP results 
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
 2009-05-12 15:01:15 -04:00
Korey Sewell 3603dd25ef inorder-fetch: update model to use predecoder 2009-05-12 15:01:15 -04:00
Korey Sewell c9a03f549b inorder-mem: clean up allocation/deletion of requests/packets 
* * *
 2009-05-12 15:01:15 -04:00
Korey Sewell 1c7e988272 inorder-mem: skeleton support for prefetch/writehints 2009-05-12 15:01:15 -04:00
Korey Sewell f41df0ee08 inorder-o3: allow both to compile together 
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
 2009-05-12 15:01:14 -04:00
Korey Sewell 5127ea226a inorder-unified-tlb: use unified TLB instead of old TLB model 2009-05-12 15:01:14 -04:00
Korey Sewell 98b1452058 inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values 2009-05-12 15:01:14 -04:00
Korey Sewell 2012202b06 inorder/alpha-isa: create eaComp object visible to StaticInst through ISA 
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
 2009-05-12 15:01:14 -04:00
Korey Sewell b569f8f0ed inorder-bpred: edits to handle non-delay-slot ISAs 
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
 2009-05-12 15:01:14 -04:00
Korey Sewell 1c8dfd9254 inorder-alpha-port: initial inorder support of ALPHA 
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
 2009-05-12 15:01:13 -04:00
Korey Sewell 9f90291c54 cpus: fix cpu progress event 
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
 2009-05-05 02:39:05 -04:00
Nathan Binkert 50f1570352 arm: Unify the ARM tlb. We forgot about this when we did the rest. 
This code compiles, but there are no tests still
 2009-04-21 15:40:25 -07:00
Steve Reinhardt 3083268d60 request: rename INST_READ to INST_FETCH. 2009-04-20 18:54:02 -07:00
Gabe Black bd6f2bb538 Mem: Change isLlsc to isLLSC. 2009-04-19 21:44:15 -07:00
Gabe Black 1a8a765a5c CPUs: Make the atomic CPU support locked memory accesses. 2009-04-19 04:50:07 -07:00
Gabe Black 3e5f487663 Memory: Rename LOCKED for load locked store conditional to LLSC. 2009-04-19 04:25:01 -07:00
Gabe Black d10195b1a4 CPU: If the simple CPU is already idle, just return from suspendContext, don't assert. 2009-04-19 02:23:29 -07:00
Korey Sewell 5c1742b822 o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly 2009-04-18 10:42:29 -04:00
Steve Reinhardt 14808ecac9 o3, inorder: fix FS bug due to initializing ThreadState to Halted. 
For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case.  There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
 2009-04-17 16:54:58 -07:00
Steve Reinhardt b146131d18 o3: handle fetch with no active threads correctly. 
This situation can arise now on the first fetch cycle after
the last active thread is halted.  It seems easy enough to
deal with when it happens rather than trying to avoid it.
 2009-04-15 23:12:00 -07:00
Steve Reinhardt bb974d5a47 o3: fix {read,set}ArchFloatReg* functions. 
Register indices were not being calculated properly.
 2009-04-15 23:10:43 -07:00
Steve Reinhardt 7617dcf736 ThreadState: initialize status to Halted in constructor. 
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
 2009-04-15 13:18:24 -07:00
Steve Reinhardt 8882dc1283 Get rid of the Unallocated thread context state. 
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
 - InOrderCPU's setThreadRescheduleCondition.
 - ThreadContext::exit().  This function was there to avoid terminating
   simulation when one thread out of a multi-thread workload exits, but we
   need to find a better (non-cpu-centric) way.
 2009-04-15 13:13:47 -07:00
Nathan Binkert e0de2c3443 tlb: More fixing of unified TLB 2009-04-08 22:21:27 -07:00
Gabe Black 7b5a96f06b tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
Steve Reinhardt 61ff48a1f8 cpu: fix minor endian issue with trace output 
(no functional change)
 2009-03-11 23:05:24 -07:00
Nathan Binkert ac7bda0212 stats: fix duplicate statistics names. 
This generally requires providing a more meaningful name() function for a
class.
 2009-03-07 14:30:54 -08:00
Nathan Binkert cc95b57390 stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
Steve Reinhardt e3d6e8882e Get rid of 'using namespace' declarations in headers. 2009-03-05 17:15:31 -08:00
Korey Sewell 9e1dc7f205 InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in a way for the compiler to play *nice*) 2009-03-04 22:37:45 -05:00
Korey Sewell 7c8d544216 Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag 2009-03-04 13:17:09 -05:00
Korey Sewell 30cd2d21fa Remove unused functions/comments cluttering up the code. 2009-03-04 13:17:08 -05:00
Korey Sewell f69b018571 make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads 2009-03-04 13:17:07 -05:00
Korey Sewell f98e9161a8 InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use. 2009-03-04 13:17:05 -05:00
Korey Sewell 846f953c2b Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic stages so w/o an ID there is no way to differentiate buffers when debugging 2009-03-04 13:16:49 -05:00
Korey Sewell e4aa4ca40c use numCycles instead of simTicks to determine CPI stat in InOrder 2009-03-04 13:16:48 -05:00
Steve Reinhardt 9ee8e685a4 O3: Make numThreads error message more helpful. 2009-03-04 09:25:53 -05:00
Gabe Black 9a000c5173 Processes: Make getting and setting system call arguments part of a process object. 2009-02-27 09:22:14 -08:00
Ali Saidi d447ccb2c6 CPA: Add code to automatically record function symbols as CPU executes. 2009-02-26 19:29:17 -05:00
Gabe Black 5c546e3504 CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code. 2009-02-25 10:22:36 -08:00
Gabe Black 9940e21fa9 CPU: Add a flag to identify a read barrier to the static inst class. 2009-02-25 10:19:33 -08:00
Gabe Black da61c4b3ee CPU: Don't fetch when executing a macroop. 
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
 2009-02-25 10:18:36 -08:00
Gabe Black 6ed47e9464 CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. 2009-02-25 10:16:15 -08:00
Gabe Black 5605079b1f ISA: Replace the translate functions in the TLBs with translateAtomic. 2009-02-25 10:15:44 -08:00
Gabe Black a1aba01a02 CPU: Get rid of translate... functions from various interface classes. 2009-02-25 10:15:34 -08:00
Nathan Binkert 3fa9812e1d debug: Move debug_break into src/base 2009-02-23 11:48:40 -08:00
Korey Sewell 6c5afe6346 Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context 2009-02-20 11:02:48 -05:00
Steve Reinhardt 89a7fb0393 Fixes to get prefetching working again. 
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
 2009-02-16 08:56:40 -08:00
Nathan Binkert f255957b90 style 2009-02-10 22:19:27 -08:00
Korey Sewell cf4a00ca41 Configs: Add support for the InOrder CPU model 2009-02-10 15:49:29 -08:00
Korey Sewell 973d8b8b13 InOrder: Import new inorder CPU model from MIPS. 
This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
 2009-02-10 15:49:29 -08:00
Korey Sewell 34a5cd8870 ExeTrace: Allow subclasses of the tracer to define their own prefix to dump 2009-02-10 15:49:29 -08:00
Korey Sewell 2d0a66cbc1 CPU: Prepare CPU models for the new in-order CPU model. 
Some new functions and forward declarations are necessary to make things work
 2009-02-10 15:49:29 -08:00
Gabe Black 7b58511470 CPU: Don't always reset the micro pc on faults. Let the faults handle it. 2009-02-01 00:30:54 -08:00
Gabe Black 7720968949 X86: Make sure the predecoder is cleared out for interrupts. 2009-02-01 00:04:34 -08:00
Ali Saidi 35a85a4e86 Config: Cause a fatal() when a parameter without a default value isn't set(FS #315). 2009-01-30 19:08:13 -05:00
Gabe Black d9794784ba CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00
Nathan Binkert f0fb3ac060 cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. 
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were.  Maybe we'll try again some day.
 2009-01-24 07:27:21 -08:00
Nathan Binkert 10fc45da27 o3cpu: give a name to the activity recorder for better tracing 2009-01-21 14:56:18 -08:00
Nathan Binkert dbac448b08 thread_context: move getSystemPtr so SE mode can get to it. 
There was really no reason that it should be FS only.
 2009-01-19 20:36:49 -08:00
Nathan Binkert 8153790d00 SCons: centralize the Dir() workaround for newer versions of scons. 
Scons bug id: 2006 M5 Bug id: 308
 2009-01-13 14:17:50 -08:00
Richard Strong 81180a3bf0 This fix addresses an ill formed if statement that fails 
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condition resolution.
 2009-01-11 22:45:03 -08:00
Gabe Black b0ab5c894d Tracing: Make tracing aware of macro and micro ops. 2009-01-06 22:34:18 -08:00
Steve Reinhardt 1704ba2273 Make Alpha pseudo-insts available from SE mode. 2008-12-17 09:51:18 -08:00
Gabe Black 02cd18f536 SPARC: Truncate syscall args and return values appropriately. 2008-12-16 23:06:37 -08:00
Nathan Binkert 489e3e7381 eventq: use the flags data structure 2008-12-06 14:18:18 -08:00
Gabe Black 7a4d75bae3 CPU: Refactor read/write in the simple timing CPU. 2008-11-13 23:30:37 -08:00
Clint Smullen 1adfe5c7f3 O3CPU: Make the instcount debugging stuff per-cpu. 
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
 2008-11-10 11:51:18 -08:00
Nathan Binkert 9c49bc7b00 mem: update stuff for changes to Packet and Request 2008-11-10 11:51:17 -08:00
Gabe Black 846cb450f9 CPU: Make unaligned accesses work in the timing simple CPU. 2008-11-09 21:56:28 -08:00
Gabe Black 909380f3ee X86: Make the timing simple CPU handle variable length instructions. 2008-11-09 21:55:01 -08:00
Lisa Hsu 07969dbbf1 Right now a single thread cpu 1 could get assigned context Id != 1, depending 
on the order in which it's registered with the system.  To make them match,
here is a little change.
 2008-11-05 15:30:49 -05:00
Lisa Hsu dd99ff23c6 get rid of all instances of readTid() and getThreadNum(). Unify and eliminate 
redundancies with threadId() as their replacement.
 2008-11-04 11:35:42 -05:00
Lisa Hsu d857faf073 Add in Context IDs to the simulator. From now on, cpuId is almost never used, 
the primary identifier for a hardware context should be contextId().  The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
 2008-11-02 21:57:07 -05:00
Lisa Hsu 67fda02dda Make it so that all thread contexts are registered with the System, even in 
SE.  Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
 2008-11-02 21:57:06 -05:00
Lisa Hsu c55a467a06 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered 
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
 2008-11-02 21:56:57 -05:00
Clint Smullen 95af120e60 CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU. 
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
 2008-10-27 18:18:04 -04:00
Lisa Hsu 8788d703f8 s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in 
comments.
 2008-10-23 16:49:17 -04:00
Nathan Binkert 9836d81c2b style: Use the correct m5 style for things relating to interrupts. 2008-10-21 07:12:53 -07:00
Ali Saidi b760b99f4d O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes 
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
 2008-10-20 16:22:59 -04:00
Gabe Black 809f6cb6d1 CPU: Explain why some code is commented out. 2008-10-12 23:52:02 -07:00
Gabe Black 989fa4fc0f X86: Make the MicroPC type 16 bit. 2008-10-12 20:48:24 -07:00
Gabe Black 0756dbb37a X86: Don't fetch in the simple CPU if you're in the ROM. 2008-10-12 19:32:06 -07:00
Gabe Black f245358343 Get rid of old RegContext code. 2008-10-12 17:57:46 -07:00
Gabe Black c9ea0b7349 CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM. 2008-10-12 16:59:55 -07:00
Gabe Black 2736086d7c CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
Gabe Black d0a43ce2b2 X86: Fix the ordering of special physical address ranges. 2008-10-12 14:01:06 -07:00
Gabe Black 557bde43c3 X86: Make APICs communicate through the memory system. 2008-10-12 13:28:54 -07:00
Gabe Black 42ebebf99a X86: Make the local APIC accessible through the memory system directly, and make the timer work. 2008-10-12 11:08:00 -07:00
Gabe Black d9f9c967fb Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
Gabe Black c4f1cc3b48 CPU: Eliminate the get_vec function. 2008-10-12 08:24:09 -07:00
Gabe Black 0c3848732e CPU: Add a getInterruptController function 2008-10-11 16:13:58 -07:00
Gabe Black f621b7b81f CPU: Eliminate the simPalCheck funciton. 2008-10-11 12:17:24 -07:00
Gabe Black da7209ec93 CPU: Eliminate the hwrei function. 2008-10-11 02:27:21 -07:00
Nathan Binkert 94b08bed07 SimObjects: Clean up handling of C++ namespaces. 
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
 2008-10-09 22:19:39 -07:00
Nathan Binkert e06321091d eventq: convert all usage of events to use the new API. 
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
 2008-10-09 04:58:24 -07:00
Gabe Black b66eb3b8d1 O3: Generaize the O3 IMPL class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
 2008-10-09 00:10:02 -07:00
Gabe Black f57c286d2c O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. 
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
 2008-10-09 00:09:26 -07:00
Gabe Black e09c403d32 O3: Generalize the O3 CPU object so it isn't split out by ISA. 2008-10-09 00:08:50 -07:00
Gabe Black c5c6ad7ed6 CPU: Fix where setMicroPC was being called instead of setNextMicroPC. 2008-10-09 00:06:05 -07:00
Nathan Binkert 80d9be86e6 gcc: Add extra parens to quell warnings. 
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off.  Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
 2008-09-27 21:03:49 -07:00
Kevin Lim b784903207 O3CPU: Fix thread writeback logic. 
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
 2008-09-26 07:44:07 -07:00
Kevin Lim 712a8ee700 O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls. 
Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
 2008-09-26 07:44:06 -07:00
Nathan Binkert 6efb930e19 gcc: Version 4.3 is pretty anal about shadowing types, placate it. 
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
 2008-09-22 08:25:57 -07:00
Ali Saidi 3a3e356f4e style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
Gabe Black 3633a916c2 CPU: Get rid of two more duplicated CPU params. 2008-08-19 21:59:09 -07:00
Richard Strong 8d018aef0f Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its 
python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
 2008-08-18 10:50:58 -07:00
Nathan Binkert ee62a0fec8 params: Convert the CPU objects to use the auto generated param structs. 
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them.  While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
 2008-08-11 12:22:16 -07:00
Nathan Binkert 50ef39af82 sockets: Add a function to disable all listening sockets. 
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb.  Expose a function to disable those ports, and have the
regression scripts disable them.  There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
 2008-08-03 18:19:55 -07:00
Steve Reinhardt 8e7ddce284 Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. 2008-07-15 14:38:51 -04:00
Ali Saidi a4a7a09e96 Remove delVirtPort() and make getVirtPort() only return cached version. 2008-07-01 10:25:07 -04:00
Ali Saidi 50e3e50e1a Make the cached virtPort have a thread context so it can do everything that a newly created one can. 2008-07-01 10:24:16 -04:00
Ali Saidi 9bd0bfe559 After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong. 
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
 2008-07-01 10:24:09 -04:00
Steve Reinhardt caaac16803 Backed out changeset 94a7bb476fca: caused memory leak. 2008-06-28 13:19:38 -04:00
Steve Reinhardt 6b45238316 Generate more useful error messages for unconnected ports. 
Force all non-default ports to provide a name and an
owner in the constructor.
 2008-06-21 01:04:43 -04:00
Nathan Binkert 67a33eed40 AtomicSimpleCPU: Separate data stalls from instruction stalls. 
Separate simulation of icache stalls and dat stalls.
 2008-06-18 10:15:21 -07:00
Nathan Binkert 163465ac08 ThreadState: Ensure that kernelStats is properly initialized 2008-06-17 21:11:20 -07:00
Nathan Binkert e3c267a3db port: Clean up default port setup and port switchover code. 2008-06-15 21:34:32 -07:00
Gabe Black d093fcb079 CPU: Make the simple cpu trace data for loads/stores. 2008-06-12 00:35:50 -04:00
Ali Saidi 8af6dc118c SCons: add comments to SConscript documenting bug workaround 
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
 2008-04-10 15:38:10 -04:00
Ali Saidi ed27c4c521 SCons: Manually specifying header only directories with Dir() works around the problem 
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
 2008-04-08 11:08:26 -04:00
Steve Reinhardt 93ab43288a Don't FastAlloc MSHRs since we don't allocate them on the fly. 
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
 2008-03-24 01:08:02 -04:00
Vilas Sridharan 21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined 
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
 2008-03-06 00:27:09 -05:00
Korey Sewell 8fb74c238c Add comments in code to describe bug conditions. 
This should help if somebody gets to the bug
fix before me (or someone else)...

--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
 2008-02-27 17:50:29 -05:00
Korey Sewell b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
 2008-02-27 16:53:08 -05:00
Korey Sewell 34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Gabe Black 8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Ali Saidi 9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Steve Reinhardt 9d7a69c582 Fix #include lines for renamed cache files. 
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Stephen Hines 6cc1573923 Make the Event::description() a const function 
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Stephen Hines 0ccf9a2c37 Add base ARM code to M5 
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
 2008-02-05 23:44:13 -05:00
Ke Meng 0b6876a0c0 The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. 
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>

--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
 2008-01-14 11:47:32 -05:00
Steve Reinhardt 6c5a3ab8b2 Add ReadRespWithInvalidate to handle multi-level coherence situation 
where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us.  We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A.  This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.

--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
 2008-01-02 15:22:38 -08:00
Steve Reinhardt cde5a79eab Additional comments and helper functions for PrintReq. 
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
 2008-01-02 13:46:22 -08:00
Steve Reinhardt 3952e41ab1 Add functional PrintReq command for memory-system debugging. 
--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
 2008-01-02 12:20:15 -08:00
Ali Saidi 45ea1549c9 Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 
--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
 2007-12-18 01:52:57 -05:00
Ali Saidi 71909a50de CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. 
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
 2007-12-16 03:48:13 -05:00
Gabe Black ab598eadbf imported patch pagewalker.patch 
--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
 2007-11-21 00:04:15 -08:00
Gabe Black a12d5975cc Simple CPU fix simple mistake in translateDataWriteAddr. 
--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
 2007-11-20 15:37:56 -08:00
Korey Sewell d09ab2bd22 add thread id to misc. reg functions 
--HG--
extra : convert_revision : 35d073d1279947d943a0290832e09a5268dd0b76
 2007-11-15 20:35:49 -05:00
Korey Sewell 7c076479e4 add MicroPC functions back to thread context 
--HG--
extra : convert_revision : a9cfd2829c4aec191f5f9ec6ce7b5d1dccc92af1
 2007-11-15 20:35:31 -05:00
Korey Sewell cf9dc4b151 add microPC stuff back in. got deleted on changeset propragation somehow. 
--HG--
extra : convert_revision : 5e89484b2ef21457ffba35ef959df999a28c5676
 2007-11-15 19:48:53 -05:00
Korey Sewell 8f8e7fe08e put the flattenIndex stuff back in O3 AND put fatal() back in faults 
--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
 2007-11-15 16:38:09 -05:00
Korey Sewell 641ee83e40 add core specific parameter to BaseCPU params 
--HG--
extra : convert_revision : 15c5995e3acf23a45c712891fd06ef273584f7e8
 2007-11-15 14:18:56 -05:00
Korey Sewell 789153dff6 Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp" 
--HG--
extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
 2007-11-15 03:10:41 -05:00
Korey Sewell 375ddf8d25 branch merge 
--HG--
extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
 2007-11-15 00:14:20 -05:00
Korey Sewell 2692590049 Add in files from merge-bare-iron, get them compiling in FS and SE mode 
--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
 2007-11-13 16:58:16 -05:00
Gabe Black 1048b548fa X86: Separate out the page table walker into it's own cc and hh. 
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
 2007-11-12 18:06:57 -08:00
Gabe Black fce45baf17 X86: Work on the page table walker, TLB, and related faults. 
--HG--
extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
 2007-11-12 14:38:31 -08:00
Gabe Black f17f3d20be X86: Implement a page table walker. 
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
 2007-11-12 14:38:24 -08:00
Gabe Black 7a39457d7f X86: Make the micropc available through the thread context objects. 
This is necssary for fault handlers that branch to non-zero micro PCs.

--HG--
extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
 2007-11-12 14:38:17 -08:00
Ali Saidi 422ab8bec0 TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes. 
--HG--
extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
 2007-11-08 10:46:41 -05:00
Ali Saidi cf1c25dbcc AtomicSimpleCPU: Refactor resume() code to have a cleaner control path. 
--HG--
extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
 2007-11-08 10:46:41 -05:00
Ali Saidi 11b931df6a Interrupts: Inline some code and remove duplication. 
--HG--
extra : convert_revision : 0631c601f281bdd2a12ff0d0ae94576780115c2a
 2007-11-08 10:46:41 -05:00
Ali Saidi e41197a3f8 CPU: Add function to explictly compare thread contexts after copying. 
--HG--
extra : convert_revision : 9b7af59a11202a91409aad7c427b7749cd1d2f12
 2007-11-08 10:46:41 -05:00
Gabe Black 19292d3f06 O3: Remove unneeded variable. 
--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
 2007-11-06 12:51:08 -08:00
Steve Reinhardt 4b49bd47f4 String constant const-ness changes to placate g++ 4.2. 
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).

--HG--
extra : convert_revision : b347cc0108f23890e9b73b3ee96059f0cea96cf6
 2007-10-31 18:04:22 -07:00
Ali Saidi 538fae951b Traceflags: Add SCons function to created a traceflag instead of having one file with them all. 
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
 2007-10-31 01:21:54 -04:00
Gabe Black 93da9eb7f6 CPU: Add functions to the "ExecContext"s that translate a given address. 
--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
 2007-10-22 14:30:45 -07:00
Ali Saidi 8351660273 CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases. 
--HG--
extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
 2007-10-18 13:15:08 -04:00
Gabe Black 50e2d20cb8 Merge with head. 
--HG--
extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
 2007-10-02 23:03:38 -07:00
Gabe Black a56c651980 Predecoder: Clear out predecoder state on an ITLB fault. 
--HG--
extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
 2007-10-02 22:21:38 -07:00
Gabe Black 7571e8346d CPU: Make the cpuid parameter get set in SE mode as well. 
--HG--
extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
 2007-10-02 18:33:57 -07:00
Gabe Black 988cdb49f2 CPU: Make the cpus check the pc event queues in SE mode. 
--HG--
extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
 2007-10-02 18:25:37 -07:00
Gabe Black 3eeda8008d CPU: Make sure the system parameter gets set in the cpu builders. Other parameters need to be fixed as well. 
--HG--
extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
 2007-10-02 18:22:36 -07:00
Ali Saidi 0acf891c32 CPU: fix sparc_fs booting with SimpleTimingCPU. 
--HG--
extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
 2007-10-01 02:55:27 -04:00
Ali Saidi d2a4f595d6 Update stats for quiesced cycles 
--HG--
extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
 2007-09-28 13:22:14 -04:00
Ali Saidi d325f49b70 Rename cycles() function to ticks() 
--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
 2007-09-28 13:21:52 -04:00
Ali Saidi 887cd6a273 Update statistics to use cycles properly instead of ticks 
--HG--
extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
 2007-09-28 13:21:30 -04:00
Gabe Black 2dd65dc254 Merge with head. 
--HG--
extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225
 2007-09-25 20:11:41 -07:00
Gabe Black 032a30f345 SPARC: Fix a stupid mistake which was breaking the SPARC regressions. 
--HG--
extra : convert_revision : 34a11df0d467ea249211dd3aba86bc8d2aea45de
 2007-09-25 20:00:46 -07:00
Gabe Black 418ddf43e6 X86: Get X86_FS to compile. 
--HG--
extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
 2007-09-24 17:39:56 -07:00
Gabe Black f3f3747431 X86: Put in the foundation for x87 stack based fp registers. 
--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
 2007-09-19 18:26:42 -07:00
Gabe Black 26044dca33 X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm. 
--HG--
extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77
 2007-09-04 23:39:57 -07:00
Gabe Black 941675690c X86: Get x86 to compile again after the simobject constructor change. 
--HG--
extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
 2007-08-31 13:02:58 -07:00
Miles Kaufmann e4eea9ee04 Fix miscellaneous small typos. 
--HG--
extra : convert_revision : bfc0ac8e1c8a5d01d9fa5203184bbf99c8361da3
 2007-08-30 15:16:59 -04:00
Miles Kaufmann 54cc0053f0 params: Deprecate old-style constructors; update most SimObject constructors. 
SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed.  Subclasses
that still rely on that behavior must call the parent initializer as
  : SimObject(makeParams(name))

--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
 2007-08-30 15:16:59 -04:00
Gabe Black 7227ab5f22 Merge with head 
--HG--
extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
 2007-08-26 21:45:40 -07:00
Gabe Black 80d51650c8 O3 CPU: Remove alignment check from dynamic instruction read/write functions. 
--HG--
extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
 2007-08-26 20:31:30 -07:00
Gabe Black 24bfda0fdf Simple CPU: Don't trace instructions that fault. Otherwise they show up twice. 
--HG--
extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
 2007-08-26 20:29:09 -07:00
Gabe Black e7e2d5ce90 Simple CPU: Added code that will split requests that cross block boundaries into multiple memory access. 
--HG--
extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
 2007-08-26 20:27:11 -07:00
Gabe Black e056e49c45 Simple CPU: Make sure only instructions which complete without faulting are counted. 
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
 2007-08-26 20:25:42 -07:00
Gabe Black 537239b278 Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
 2007-08-26 20:24:18 -07:00
Gabe Black 20e0a3792a Merge with head. 
--HG--
extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
 2007-08-21 16:19:46 -07:00