Commit graph

7320 commits

Author SHA1 Message Date
David Guillen Fandos
c0c3316e31 sim: Add voltage() function to clocked_object
Adding voltage function which returns the current voltage
for a given clocked object. It's handy for power models and
similar stuff that need to retrieve voltage. Function
frequency() is already there, so I see no reason for not having
this one too.
2015-06-17 16:49:40 +01:00
Rekai Gonzalez Alberquilla
21f8242430 cpu: Change literal integer constants to meaningful labels
fu_pool and inst_queue were using -1 for "no such FU" and -2 for "all those
FUs are busy at the moment" when requesting for a FU and replying. This
patch introduces new constants NoCapableFU and NoFreeFU respectively.

In addition, the condition (idx == -2 || idx != -1) is equivalent to
(idx != -1), so this patch also simplifies that.

--HG--
extra : rebase_source : 4833717b9d1e09d7594d1f34f882e13fc4b86846
2015-05-05 16:47:24 +01:00
Andreas Hansson
8faeec44a6 base: Fix gpu-compute output stream creation
Match changes in output stream.
2016-03-04 20:14:10 -05:00
Andreas Sandberg
4f303785dc kvm: Shutdown KVM and disconnect performance counters on fork
We can't/shouldn't use KVM after a fork since the child and parent
probably point to the same VM. Knowing the exact effects of this is
hard, but they are likely to be messy. We also disconnect the
performance counters attached to the guest. This works around what
seems to be a kernel bug where spurious SIGIOs get delivered to the
forked child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Fatal if entering KVM in child process ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-27 14:52:10 +00:00
Andreas Sandberg
a91c1e69a8 sim: Add support for forking
This changeset adds forking capabilities to the gem5 python scripts. A fork
method is added to simulate.py. This method is responsible for forking the
simulator itself, and will direct all output files to a new output directory
based on the fork sequence number. The default name of the output directory is
the same as the parent with the suffix ".fN" added where N is the fork sequence
number. The fork method provides the option to specify if the system should be
drained prior to forking, or not. By default the system is drained to ensure
that there are no in-flight transactions.

When forking the simulator, the fork method returns the PID of the child
process, or returns 0 if running in the child. This is in line with the standard
Python forking interface.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Updated to comply with modern draining semantics ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:11:57 +00:00
Andreas Sandberg
6de52699bb dev: Add post-fork handling for disk images
This changeset adds support for notifying the disk images that the simulator has
been forked. We need to disable the saving of the CoW disk image from the child
process, and we need to make sure that systems which use a raw disk image are
not allowed to fork to avoid two or more gem5 processes writing to the same disk
image.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:11:52 +00:00
Andreas Sandberg
738d71f6a9 sim: Add support for notifying Drainable objects of a fork
When forking a gem5 process, some objects need to clean up resources
(mainly file descriptions) shared between the child and the parent of
the fork. This changeset adds the notifyFork() method to Drainable,
which is called in the child process.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-26 10:03:43 +00:00
Andreas Sandberg
5383e1ada4 base: Add support for changing output directories
This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.

This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2015-11-27 14:41:59 +00:00
Stephan Diestelhorst
f703160e5a mem, cpu: Add assertions to snoop invalidation logic
This patch adds assertions that enforce that only invalidating snoops
will ever reach into the logic that tracks in-order load completion and
also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds
some comments to MSHR::replaceUpgrades().
2015-08-10 11:25:52 +01:00
Krishnendra Nathella
cabd4768c7 cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
2015-07-19 15:03:30 -05:00
Mitch Hayenga
c0d19391d4 arm: Squash after returning from exceptions in v7
Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
2016-02-29 19:13:13 -06:00
Curtis Dunham
aa674268e9 base: support gzip-compressed object files 2016-02-29 19:13:13 -06:00
Andreas Hansson
7958f34797 mem: Ensure that InvalidateReq is not forwarded as ReadExReq
This patch fixes an issue where an InvalidationReq only traversed one
level of the cache hierarchy, and was subsequently turned into a
ReadExReq due to it needing writable, and the command not being
checked for explicitly.
2016-02-24 04:16:57 -05:00
Matteo Andreozzi
496a8c6c92 cpu: TraceGen fix for tick frequency check
Bug fix for check on protobuf file frequency being different than
global frequency.

The ASCII encoder script is also fixed, and the example trace used in
the regressions is updated.
2016-02-24 04:16:55 -05:00
Andreas Sandberg
e2cea54deb dev, arm: Implement the NoMali reset callback
Add a callback handler for the NoMali reset callback. This callback is
called whenever the GPU is reset using the register interface or the
NoMali API. The callback can be used to override ID registers using
the raw register API.
2016-02-23 11:49:35 +00:00
Andreas Sandberg
81a8ce3564 dev, arm: Refactor the NoMali GPU
Refactor and cleanup the NoMaliGpu class:

  * Use a std::map instead of a switch block to map the parameter enum
    describing the GPU type to a NoMali type.

  * Remove redundant NoMali handle from the interrupt callback.

  * Make callbacks and API wrappers protected instead of private to
    enable future extensions.

  * Wrap remaining NoMali API calls.
2016-02-23 11:49:34 +00:00
Andreas Hansson
4619f0ee8b scons: Add missing override to appease clang
Make clang happy...again.
2016-02-23 03:27:20 -05:00
Tony Gutierrez
5a88f0931f ruby: move range change send from RubyPort to derived classes. 2016-02-18 10:50:16 -05:00
John Kalamatianos
a28a234069 gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
Both Memory Fence is now flagged as Global Memory only to avoid resource
oversubscribing.
Flat instructions now check for Shared Memory resource busy to avoid
oversubscribing resources.
All WaitClass resources now use cycles (not ticks) to register the number
of pipe stages between Scoreboard and Execute to be consistent with
instruction scheduling logic which always used clock cycles.
2016-02-18 10:42:03 -05:00
Tony Gutierrez
9a0f1be21f gpu-compute: remove brig_object.hh from hsa_object.cc
brig_object.hh is specific to the HSAIL ISA, and hence should not be
included in ISA-agnostic code.
2016-02-17 11:46:02 -05:00
Tony Gutierrez
969babd26f ruby: send address ranges from RubyPort 2016-02-17 11:31:54 -05:00
Andreas Hansson
a34ff350da scons: Enable building with the gcc/clang Address Sanitizer
Allow the user to easily build gem5 with the Address Sanitizer, part
of both gcc and clang these days.
2016-02-17 03:56:20 -05:00
Andreas Hansson
0d50979888 misc: Add missing overrides to appease clang
Since the last round of fixes a few new issues have snuck in. We
should consider switching the regression runs to clang.
2016-02-15 03:40:32 -05:00
Andreas Hansson
407233f5d8 mem: Avoid using invalid iterator in cache lock list traversal
Fix up issue highlighted by Valgrind and the clang Address Sanitizer.
2016-02-15 03:40:04 -05:00
Michael LeBeane
b181cea364 ruby: make DMASequencer inherit from RubyPort
This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the
parent class of DMASequencer.  It removes redundant code and restores some
features which were lost when directly inheriting from MemObject.  For
example,
DMASequencer can now communicate to other devices using PIO, which is useful
for memmory-mapped communication between multiple DMADevices.
2016-02-14 20:28:48 -05:00
Michael LeBeane
2ae4cce393 configs: add command-line option to stop debug output
This patch adds a --debug-end flag to main.py so that debug output can be
stoped at a specified tick, while allowing the simulation to continue. It is
useful in situations where you would like to produce a trace for a region of
interest while still collecting stats for the entire run. This is in contrast
to the currently existing --debug-break flag, which terminates the simulation
at the tick.
2016-02-13 12:36:43 -05:00
Michael LeBeane
8d923c7380 syscall_emul: Implement clock_getres() system call
This patch implements the clock_getres() system call for arm and x86 in linux
SE mode.
2016-02-13 12:33:07 -05:00
Andreas Hansson
83a5977481 mem: Be less conservative in clearing load locks in the cache
Avoid being overly conservative in clearing load locks in the cache,
and allow writes to the line if they are from the same context. This
is in line with ALPHA and ARM.
2016-02-10 04:08:25 -05:00
Andreas Hansson
92f021cbbe mem: Move the point of coherency to the coherent crossbar
This patch introduces the ability of making the coherent crossbar the
point of coherency. If so, the crossbar does not forward packets where
a cache with ownership has already committed to responding, and also
does not forward any coherency-related packets that are not intended
for a downstream memory controller. Thus, invalidations and upgrades
are turned around in the crossbar, and the memory controller only sees
normal reads and writes.

In addition this patch moves the express snoop promotion of a packet
to the crossbar, thus allowing the downstream cache to check the
express snoop flag (as it should) for bypassing any blocking, rather
than relying on whether a cache is responding or not.
2016-02-10 04:08:25 -05:00
Andreas Hansson
f84ee031cc mem: Align cache behaviour in atomic when upstream is responding
Adopt the same flow as in timing mode, where the caches on the path to
memory get to keep the line (if present), and we use the
responderHadWritable flag to determine if we need to forward the
(invalidating) packet or not.
2016-02-10 04:08:24 -05:00
Andreas Hansson
986214f181 mem: Align how snoops are handled when hitting writebacks
This patch unifies the snoop handling in case of hitting writebacks
with how we handle snoops hitting in the tags. As a result, we end up
using the same optimisation as the normal snoops, where we inform the
downstream cache if we encounter a line in Modified (writable and
dirty) state, which enables us to avoid sending out express snoops to
invalidate any Shared copies of the line. A few regressions
consequently change, as some transactions are sunk higher up in the
cache hierarchy.
2016-02-10 04:08:24 -05:00
Andreas Hansson
fbdeb60316 mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.

The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
2016-02-10 04:08:24 -05:00
Curtis Dunham
bead7f249a scons: always generate sim/tags.cc
Due to insufficient build deps, the checkpoint tags might not get
updated; this commit solves this. Due to the uncommon nature of the
build target, regenerating tags.cc is a fairly clean solution. Since
SCons hashes file contents, it won't recompile anything unless a new
checkpoint upgrader is actually added.

--HG--
extra : amend_source : ed3879da7668554693f697076deaf5029cc9b954
2016-02-08 13:39:45 -06:00
Alexandru Dutu
0f27d70e90 x86: revamp cmpxchg8b/cmpxchg16b implementation
The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models.  It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops.  It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.

This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg.  This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
5200e04e92 arch, x86: add support for arrays as memory operands
Although the cache models support wider accesses, the ISA descriptions
assume that (for the most part) memory operands are integer types,
which makes it difficult to define instructions that do memory accesses
larger than 64 bits.

This patch adds some generic support for memory operands that are arrays
of uint64_t, and specifically a 'u2qw' operand type for x86 that is an
array of 2 uint64_ts (128 bits).  This support is unused at this point,
but will be needed shortly for cmpxchg16b.  Ideally the 128-bit SSE
memory accesses will also be rewritten to use this support.

Support for 128-bit accesses could also have been added using the gcc
__int128_t extension, which would have been less disruptive.  However,
although clang also supports __int128_t, it's still non-standard.
Also, more importantly, this approach creates a path to defining
256- and 512-byte operands as well, which will be useful for eventual
AVX support.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
f5343df1e1 arch: get rid of dummy var init
MemOperand variables were being initialized to 0
"to avoid 'uninitialized variable' errors" but these
no longer seem to be a problem (with the exception of
one use case in POWER that is arguably broken and
easily fixed here).

Getting rid of the initialization is necessary to
set up a subsequent patch which extends memory
operands to possibly not be scalars, making the
'= 0' initialization no longer feasible.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
92b750d5ef syscall_emul: fix bug in aux vector initialization
Writing 16 bytes from an 8-byte source value is a bad idea.
This doesn't appear to have broken anything, but showed up
as spurious differences when tracediffing runs.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
f6b828d068 style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.

Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>>        DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>>            "EXPECT_FALSE(" #expr ")", (expr) == false)<<
2016-02-06 17:21:20 -08:00
Steve Reinhardt
2d91e741e8 x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison,
it became apparent that a slightly more involved solution was
needed.  Split this out into its own changeset since it's not
a totally trivial local change like the others.
2016-02-06 17:21:20 -08:00
Steve Reinhardt
5592798865 style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
2016-02-06 17:21:19 -08:00
Steve Reinhardt
dc8018a5c3 style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
2016-02-06 17:21:18 -08:00
Mohammad Alian
24da47cf96 dist, dev: add an ethernet switch model 2016-02-06 13:33:34 -05:00
Brad Beckmann
dcd8eeec3b ruby: removed Write_Only AccessPermission 2016-01-22 10:42:12 -05:00
David Hashe
698866d461 ruby: split CPU and GPU latency stats 2015-07-20 09:15:18 -05:00
Tony Gutierrez
1a7d3f9fcb gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
Tony Gutierrez
28e353e040 mem: write combining for ruby protocols
This patch adds support for write-combining in ruby.
2016-01-19 14:05:03 -05:00
Tony Gutierrez
d658b6e1cc * * *
mem: support for gpu-style RMWs in ruby

This patch adds support for GPU-style read-modify-write (RMW) operations in
ruby. Such atomic operations are traditionally executed at the memory controller
(instead of through an L1 cache using cache-line locking).

Currently, this patch works by propogating operation functors through the memory
system.
2016-01-19 13:57:50 -05:00
Blake Hechtman
34fb6b5e35 mem: misc flags for AMD gpu model
This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.
2015-07-20 09:15:18 -05:00
Steve Reinhardt
b7ea2bc705 sim: fix redundant --debug-start help string
Just changes the metavar for --debug-start from TIME
to TICK in cset 72046b9b3323 and didn't notice that the
comment "must be in ticks" is now redundant.
2016-01-17 19:18:49 -08:00
Steve Reinhardt
1b6355c895 cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.

This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.

This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().

For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level.  For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.
2016-01-17 18:27:46 -08:00
Steve Reinhardt
707275265f cpu: remove unnecessary data ptr from O3 internal read() funcs
The read() function merely initiates a memory read operation; the
data doesn't arrive until the access completes and a response packet
is received from the memory system.  Thus there's no need to provide
a data pointer; its existence is historical.

Getting this pointer out of this internal o3 interface sets the
stage for similar cleanup in the ExecContext interface.  Also
found that we were pointlessly setting the contents at this pointer
on a store forward (the useful memcpy happens just a few lines
below the deleted one).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
e595d9cccb arch: don't call *Timing functions from *Atomic versions
The readMemAtomic/writeMemAtomic helper functions were calling
readMemTiming/writeMemTiming respectively.  This is functionally
correct, since the *Timing functions are doing the same access
initiation operation as the *Atomic functions (just that the
*Atomic versions also complete the access in line).  It also
provides for some (very minimal) code reuse.  Unfortunately,
it's potentially pretty confusing, since it makes it look like
the atomic accesses are somehow being converted to timing
accesses.  It also gets in the way of specializing the timing
interface (as will be done in a future patch).
2016-01-17 18:27:46 -08:00
Steve Reinhardt
fb0383bc72 arch: get rid of unused LargestRead typedef 2016-01-17 18:27:46 -08:00
Steve Reinhardt
28a0e5a165 sim: don't ignore SIG_TRAP
By ignoring SIG_TRAP, using --debug-break <N> when not connected to
a debugger becomes a no-op.  Apparently this was intended to be a
feature, though the rationale is not clear.

If we don't ignore SIG_TRAP, then using --debug-break <N> when not
connected to a debugger causes the simulation process to terminate
at tick N.  This is occasionally useful, e.g., if you just want to
collect a trace for a specific window of execution then you can combine
this with --debug-start to do exactly that.

In addition to not ignoring the signal, this patch also updates
the --debug-break help message and deletes a handful of unprotected
calls to Debug::breakpoint() that relied on the prior behavior.
2016-01-17 18:27:46 -08:00
Andreas Sandberg
745f8229f6 dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:

  * Automatic PCI interrupt assignment
  * PCI interrupts allocated in a contiguous range.
  * Automatic boot loader selection (32-bit / 64-bit)
  * Cleaner memory map where gem5-specific devices live in CS5 which
    isn't used by current Versatile Express platforms.
  * No fake devices. Devices that were previously faked will be
    removed from the device tree instead.
  * Support for 510 GiB contiguous memory
2016-01-15 11:30:13 +00:00
Andreas Sandberg
6d058a63b0 dev, arm: Add support for automatic PCI interrupt routing
Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.

Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:

  * ARM_PCI_INT_STATIC: Use the old static routing policy using the
    interrupt line from a device's configurtion space.

  * ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
    interrupt in the GIC. The interrupt is computed as:

    gic_int = int_base + (pci_dev % int_count)

  * ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
    an interrupt in the GIC. The PCI specification reserves pin ID 0
    for devices without interrupts, the interrupt therefore computed
    as:

    gic_int = int_base + ((pin - 1) % int_count)
2016-01-15 11:30:06 +00:00
Steve Reinhardt
8406a54907 mem: fix bug in packet access endianness changes
The new Packet::setRaw() method incorrectly still contained
an htog() conversion.  As a result, calls to the old set()
method (now defined as setRaw(htog(v))) underwent two htog
conversions, which breaks things when htog() is not a no-op.

Interestingly the only test that caught this was a SPARC
boot test, where an IsaFake device with a non-zero return
value was getting swapped twice resulting in a register
getting loaded with 0x100000000000000 instead of 1.
(Good reason for keeping SPARC around, perhaps?)
2016-01-11 16:20:38 -05:00
Andreas Hansson
12eb034378 scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
2016-01-11 05:52:20 -05:00
Andreas Hansson
7661f1c2bf ext: Replace gzstream with iostream3 from zlib to avoid LGPL
This patch replaces the gzstream zlib wrapper with the iostream3
wrapper provided as part of zlib contributions. The main reason for
the switch is to avoid including LGPL in the default gem5
build. iostream3 is provided under a more permissive license:

The code is provided "as is", with the permission to use, copy,
modify, distribute and sell it for any purpose without fee.
2016-01-11 05:52:18 -05:00
Gabor Dozsa
5dec4e07b8 dev: Distributed Ethernet link for distributed gem5 simulations
Distributed gem5 (abbreviated dist-gem5) is the result of the
convergence effort between multi-gem5 and pd-gem5 (from Univ. of
Wisconsin). It relies on the base multi-gem5 infrastructure for packet
forwarding, synchronisation and checkpointing but combines those with
the elaborated network switch model from pd-gem5.

--HG--
rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc
rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh
rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc
rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh
rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
2016-01-07 16:33:47 -06:00
Gabor Dozsa
e677494260 pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from
within the simulated software.
2016-01-07 16:33:47 -06:00
Steve Reinhardt
6caa2c9b4e mem: add CacheVerbose debug flag, filter noisy DPRINTFs
Some of the DPRINTFs added to the classic cache in cset 45df88079f04,
while useful to those unfamiliar with the cache code, end up being
noise when you're familiar with the code but are trying to debug tricky
protocol issues.  (Particularly getting two messages from each cache
as it receives a snoop request then declares that there was no match.)

This patch introduces a CacheVerbose debug flag, and moves a subset of
the added DPRINTFs into that category, so that Cache by itself returns
to being a more succinct summary of cache activity.

Also added a CacheAll compound flag to turn on all the cache-related
debug flags (other than CacheTags, which you *really* have to want badly
to turn it on, IMO).
2015-12-31 09:32:09 -08:00
Andreas Hansson
c153b669fd mem: Do not rely on the NeedsWritable flag for responses
This patch removes the NeedsWritable flag for all responses, as it is
really only the request that needs a writable response. The response,
on the other hand, should in these cases always provide the line in a
writable state, as indicated by the hasSharers flag not being set.

When we send requests that has NeedsWritable set, the response will
always have the hasSharers flag not set. Additionally, there are cases
where the request did not have NeedsWritable set, and we still get a
writable response with the hasSharers flag not set. This never happens
on snoops, but is used by downstream caches to pass ownership
upstream.

As part of this patch, the affected response types are updated, and
the snoop filter is similarly modified to check only the hasSharers
flag (as it should). A sanity check is also added to the packet class,
asserting that we never look at the NeedsWritable flag for responses.

No regressions are affected.
2015-12-31 09:34:18 -05:00
Andreas Hansson
7fca994d04 mem: Do not allocate space for packet data if not needed
This patch looks at the request and response command to determine if
either actually has any data payload, and if not, we do not allocate
any space for packet data.

The only tricky case is where the command type is changed as part of
the MSHR functionality. In these cases where the original packet had
no data, but the new packet does, we need to explicitly call
allocate().
2015-12-31 09:33:39 -05:00
Andreas Hansson
f1ec326be5 mem: Do not alter cache block state on uncacheable snoops
This patch ensures we do not respond with a Modified (dirty and
writable) line if the request is uncacheable, and that the cache
responding retains the line without modifying the state (even if
responding).
2015-12-31 09:33:25 -05:00
Andreas Hansson
0fcb376e5f mem: Make cache terminology easier to understand
This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
2015-12-31 09:32:58 -05:00
Tony Gutierrez
a317764577 ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one.  The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.

The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier.  This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
2015-07-20 09:15:18 -05:00
Tony Gutierrez
3f68884c0e ruby: slicc: remove support for single machine, multiple types
This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.
2015-07-20 09:15:18 -05:00
Andreas Hansson
f5c4a45889 mem: Explicitly check MSHR snoops for cases not dealt with
Add a sanity check to make it explicit that we currently do not allow
an I/O coherent agent to directly issue writes into the coherent part
of the memory system (it has to go via a cache, and get transformed
into a read ex, upgrade or invalidation).
2015-12-28 11:14:18 -05:00
Andreas Hansson
f6525ff221 mem: Remove unused cache squash functionality
This patch removes the unused squash function from the MSHR queue, and
the associated (and also unused) threadNum member from the MSHR.
2015-12-28 11:14:16 -05:00
Andreas Hansson
fbf3987c7b mem: Avoid unecessary checks when creating HardPFReq in cache
The checks made before sending out a HardPFReq were unecessarily
complex, and checked for cases that never occur. This patch
tidies it up.
2015-12-28 11:14:15 -05:00
Andreas Hansson
b93a9d0d51 mem: Do not use sender state to track forwarded snoops in cache
This patch changes how the cache tracks which snoops are forwarded,
and which ones are created locally. Previously the identification was
based on an empty sender state of a specific class, but this method
fails to distinguish which cache actually attached the sender
state. Instead we use the same mechanism as the crossbar, and keep
track of the requests that have outstanding snoops.
2015-12-28 11:14:14 -05:00
Andreas Hansson
036263e280 mem: Fix cache sender state handling and add clarification
This patch addresses a bug in how the cache attached the MSHR as a
sender state. Rather than overwriting any existing sender state it now
pushes a new one. The handling of upward snoops is also clarified.
2015-12-28 11:14:10 -05:00
Boris Shingarov
d765dbf22c arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays.  The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question.  This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).

With this patch I propose a simpler mechanism for expressing the
register set structure.  In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation.  The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.

This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.

Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
2015-12-18 15:12:07 -06:00
Andreas Sandberg
b5a54eb64e sim: Use the old work item behavior by default
When adding an option to forward work items to the Python environment,
the new behavior was accidentally enabled by default. Set the value of
exit_on_work_items to False by default to revert to the old behavior
unless the simulation scripts explicitly requests work item
forwarding.
2015-12-18 10:14:17 +00:00
Andreas Hansson
97887eb6dc mem: Fix memory allocation bug in deferred snoop handling
This patch fixes a corner case in the deferred snoop handling, where
requests ended up being used by multiple packets with different
lifetimes, and inadvertently got deleted while they were still in use.
2015-12-17 17:07:11 -05:00
Andreas Sandberg
08754488a3 sim: Add an option to forward work items to Python
There are cases where we want the Python world to handle work items
instead of the C++ world. However, that's currently not possible. This
changeset adds the forward_work_items option to the System class. Then
it is set to True, work items will generate workbegin/workend
simulation exists with the work item ID as the exit code and the old
C++ handling is completely bypassed.

--HG--
extra : rebase_source : 8de637a744fc4b6ff2bc763f00cdf8ddf2bff885
2015-12-14 17:10:36 +00:00
David Hashe
f5f04c3120 mem: add request types for acquire and release
Add support for acquire and release requests.  These synchronization operations
are commonly supported by several modern instruction sets.
2015-07-20 09:15:18 -05:00
Brad Beckmann
173a786921 ruby: more flexible ruby tester support
This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests.  This patch is similar to a previous changeset
(8932:1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code.  Finally, the patch also includes better DPRINTFs for
debugging the tester.
2015-07-20 09:15:18 -05:00
Andreas Sandberg
4e6241007c dev: Add missing SConscript in src/dev/i2c 2015-12-10 18:46:02 +00:00
Andreas Sandberg
8ec5fc6632 dev: Move storage devices to src/dev/storage/
Move the IDE controller and the disk implementations to
src/dev/storage.

--HG--
rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py
rename : src/dev/Ide.py => src/dev/storage/Ide.py
rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py
rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc
rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh
rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h
rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc
rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh
rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc
rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh
rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h
rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc
rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh
2015-12-10 10:35:23 +00:00
Andreas Sandberg
23c961a0fd dev: Move network devices to src/dev/net/
--HG--
rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py
rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc
rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh
rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc
rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh
rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc
rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh
rename : src/dev/etherint.cc => src/dev/net/etherint.cc
rename : src/dev/etherint.hh => src/dev/net/etherint.hh
rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc
rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh
rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh
rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc
rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh
rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc
rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh
rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc
rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh
rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh
rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc
rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh
rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc
rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh
rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc
rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh
rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc
rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh
rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h
rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc
rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh
rename : src/dev/sinic.cc => src/dev/net/sinic.cc
rename : src/dev/sinic.hh => src/dev/net/sinic.hh
rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh
rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc
rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
2015-12-10 10:35:18 +00:00
Andreas Sandberg
ef097ac438 dev: Move i2c functionality to src/dev/i2c/
--HG--
rename : src/dev/I2C.py => src/dev/i2c/I2C.py
rename : src/dev/i2cbus.cc => src/dev/i2c/bus.cc
rename : src/dev/i2cbus.hh => src/dev/i2c/bus.hh
rename : src/dev/i2cdev.hh => src/dev/i2c/device.hh
2015-12-10 10:35:18 +00:00
Andreas Sandberg
38e2860c36 dev: Move the CopyEngine class to src/dev/pci
--HG--
rename : src/dev/CopyEngine.py => src/dev/pci/CopyEngine.py
rename : src/dev/copy_engine.cc => src/dev/pci/copy_engine.cc
rename : src/dev/copy_engine.hh => src/dev/pci/copy_engine.hh
rename : src/dev/copy_engine_defs.hh => src/dev/pci/copy_engine_defs.hh
2015-12-10 10:35:16 +00:00
Andreas Sandberg
139c97c977 dev: Move existing PCI device functionality to src/dev/pci
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.

--HG--
rename : src/dev/Pci.py => src/dev/pci/PciDevice.py
rename : src/dev/pcidev.cc => src/dev/pci/device.cc
rename : src/dev/pcidev.hh => src/dev/pci/device.hh
rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
2015-12-10 10:35:15 +00:00
Sascha Bischoff
2d79bf3d4d sim: Disable gzip compression for writefile pseudo instruction
The writefile pseudo instruction uses OutputDirectory::create and
OutputDirectory::openFile to create the output files. However, by
default these will check the file extention for .gz, and create a gzip
compressed stream if the file ending matches. When writing out files,
we want to write them out exactly as they are in the guest simulation,
and never want to compress them with gzio. Additionally, this causes
m5 writefile to fail when checking the error flags for the output
steam.

With this patch we add an additional no_gz argument to
OutputDirectory::create and OutputDirectory::openFile which allows us
to override the gzip compression.  Therefore, for m5 writefile we
disable the filename check, and always create a standard ostream.
2015-11-05 18:26:23 +00:00
Karthik Sangaiah
6fa936b021 dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.

When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.

This changeset is based on previous work by Matt Evans.
2015-09-18 16:49:28 +01:00
Tony Gutierrez
413f3088ea mem: remove acq/rel cmds from packet and add mem fence req 2015-12-09 22:56:31 -05:00
Steve Reinhardt
28d7e261ed syscall_emul: don't check host fd when allocating target fd
There's a well-meaning check in Process::allocFD() to return an invalid
target fd (-1) if the incoming host fd is -1.  However, this means that
emulated drivers, which want to allocate a target fd that doesn't
correspond to a host fd, can't use -1 to indicate an intentionally
invalid host fd.

It turns out the allocFD() check is redundant, as callers always test
the host fd for validity before calling.  Also, callers never test the
return value of allocFD() for validity, so even if the test failed,
it would likely have the undesirable result of returning -1 to the
target app as a file descriptor without setting errno.

Thus the check is pointless and is now getting in the way, so it seems
we should just get rid of it.
2015-12-09 14:47:43 -05:00
Radhika Jagtap
54519fd51f cpu: Support virtual addr in elastic traces
This patch adds support to optionally capture the virtual address and asid
for load/store instructions in the elastic traces. If they are present in
the traces, Trace CPU will set those fields of the request during replay.
2015-12-07 16:42:16 -06:00
Radhika Jagtap
3080bbcc36 cpu: Create record type enum for elastic traces
This patch replaces the booleans that specified the elastic trace record
type with an enum type. The source of change is the proto message for
elastic trace where the enum is introduced. The struct definitions in the
elastic trace probe listener as well as the Trace CPU replace the boleans
with the proto message enum.

The patch does not impact functionality, but traces are not compatible with
previous version. This is preparation for adding new types of records in
subsequent patches.
2015-12-07 16:42:16 -06:00
Radhika Jagtap
7d3600c309 cpu: Add TraceCPU to playback elastic traces
This patch defines a TraceCPU that replays trace generated using the elastic
trace probe attached to the O3 CPU model. The elastic trace is an execution
trace with data dependencies and ordering dependencies annoted to it. It also
replays fixed timestamp instruction fetch trace that is also generated by the
elastic trace probe.

The TraceCPU inherits from BaseCPU as a result of which some methods need
to be defined. It has two port subclasses inherited from MasterPort for
instruction and data ports. It issues the memory requests deducing the
timing from the trace and without performing real execution of micro-ops.
As soon as the last dependency for an instruction is complete,
its computational delay, also provided in the input trace is added. The
dependency-free nodes are maintained in a list, called 'ReadyList',
ordered by ready time. Instructions which depend on load stall until the
responses for read requests are received thus achieving elastic replay. If
the dependency is not found when adding a new node, it is assumed complete.
Thus, if this node is found to be completely dependency-free its issue time is
calculated and it is added to the ready list immediately. This is encapsulated
in the subclass ElasticDataGen.

If ready nodes are issued in an unconstrained way there can be more nodes
outstanding which results in divergence in timing compared to the O3CPU.
Therefore, the Trace CPU also models hardware resources. A sub-class to model
hardware resources is added which contains the maximum sizes of load buffer,
store buffer and ROB. If resources are not available, the node is not issued.
The 'depFreeQueue' structure holds nodes that are pending issue.

Modeling the ROB size in the Trace CPU as a resource limitation is arguably the
most important parameter of all resources. The ROB occupancy is estimated using
the newly added field 'robNum'. We need to use ROB number as sequence number is
at times much higher due to squashing and trace replay is focused on correct
path modeling.

A map called 'inFlightNodes' is added to track nodes that are not only in
the readyList but also load nodes that are executed (and thus removed from
readyList) but are not complete. ReadyList handles what and when to execute
next node while the inFlightNodes is used for resource modelling. The oldest
ROB number is updated when any node occupies the ROB or when an entry in the
ROB is released. The ROB occupancy is equal to the difference in the ROB number
of the newly dependency-free node and the oldest ROB number in flight.

If no node dependends on a non load/store node then there is no reason to track
it in the dependency graph. We filter out such nodes but count them and add a
weight field to the subsequent node that we do include in the trace. The weight
field is used to model ROB occupancy during replay.

The depFreeQueue is chosen to be FIFO so that child nodes which are in
program order get pushed into it in that order and thus issued in the in
program order, like in the O3CPU. This is also why the dependents is made a
sequential container, std::set to std::vector. We only check head of the
depFreeQueue as nodes are issued in order and blocking on head models that
better than looping the entire queue. An alternative choice would be to inspect
top N pending nodes where N is the issue-width. This is left for future as the
timing correlation looks good as it is.

At the start of an execution event, first we attempt to issue such pending
nodes by checking if appropriate resources have become available. If yes, we
compute the execute tick with respect to the time then. Then we proceed to
complete nodes from the readyList.

When a read response is received, sometimes a dependency on it that was
supposed to be released when it was issued is still not released. This occurs
because the dependent gets added to the graph after the read was sent. So the
check is made less strict and the dependency is marked complete on read
response instead of insisting that it should have been removed on read sent.

There is a check for requests spanning two cache lines as this condition
triggers an assert fail in the L1 cache. If it does then truncate the size
to access only until the end of that line and ignore the remainder.
Strictly-ordered requests are skipped and the dependencies on such requests
are handled by simply marking them complete immediately.

The simulated seconds can be calculated as the difference between the
final_tick stat and the tickOffset stat. A CountedExitEvent that contains
a static int belonging to the Trace CPU class as a down counter is used to
implement multi Trace CPU simulation exit.
2015-12-07 16:42:15 -06:00
Radhika Jagtap
36bb848104 mem: Add instruction sequence number to request
This patch adds the instruction sequence number to the request and provides a
request constructor that accepts a sequence number for initialization.
2015-12-07 16:42:15 -06:00
Radhika Jagtap
de4dc50e95 proto, probe: Add elastic trace probe to o3 cpu
The elastic trace is a type of probe listener and listens to probe points
in multiple stages of the O3CPU. The notify method is called on a probe
point typically when an instruction successfully progresses through that
stage.

As different listener methods mapped to the different probe points execute,
relevant information about the instruction, e.g. timestamps and register
accesses, are captured and stored in temporary InstExecInfo class objects.
When the instruction progresses through the commit stage, the timing and the
dependency information about the instruction is finalised and encapsulated in
a struct called TraceInfo. TraceInfo objects are collected in a list instead
of writing them out to the trace file one a time. This is required as the
trace is processed in chunks to evaluate order dependencies and computational
delay in case an instruction does not have any register dependencies. By this
we achieve a simpler algorithm during replay because every record in the
trace can be hooked onto a record in its past. The instruction dependency
trace is written out as a protobuf format file. A second trace containing
fetch requests at absolute timestamps is written to a separate protobuf
format file.

If the instruction is not executed then it is not added to the trace.
The code checks if the instruction had a fault, if it predicated
false and thus previous register values were restored or if it was a
load/store that did not have a request (e.g. when the size of the
request is zero). In all these cases the instruction is set as
executed by the Execute stage and is picked up by the commit probe
listener. But a request is not issued and registers are not written.
So practically, skipping these should not hurt the dependency modelling.

If squashing results in squashing younger instructions, it may happen that
the squash probe discards the inst and removes it from the temporary
store but execute stage deals with the instruction in the next cycle which
results in the execute probe seeing this inst as 'new' inst. A sequence
number of the last processed trace record is used to trap these cases and
not add to the temporary store.

The elastic instruction trace and fetch request trace can be read in and
played back by the TraceCPU.
2015-12-07 16:42:15 -06:00
Radhika Jagtap
eb19fc2976 probe: Add probe in Fetch, IEW, Rename and Commit
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows.

A probe point is added in the Fetch stage for probing when a fetch request is
sent. Notify is fired on the probe point when a request is sent succesfully in
the first attempt as well as on a retry attempt.

Probe points are added in the IEW stage when an instruction begins to execute
and when execution is complete. This points can be used for monitoring the
execution time of an instruction.

Probe points are added in the Rename stage to probe renaming of source and
destination registers and when there is squashing. These probe points can be
used to track register dependencies and remove when there is squashing.

A probe point for squashing is added in Commit to probe squashed instructions.
2015-12-07 16:42:15 -06:00
Andreas Sandberg
78275c9d2f dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.
2015-12-05 00:11:24 +00:00
Pau Cabre
abfb997800 cpu: fix unitialized variable which may cause assertion failure
The assert in lsq_unit_impl.hh line 963 needs pktPending to be initialized to
NULL (I got the assertion failure several times without the fix).

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-12-04 17:54:03 -06:00
Andreas Sandberg
1a34e23603 sim: Get rid of the non-const serialize() method
The last SimObject using the legacy serialize API with non-const
methods has now been transitioned to the new API. This changeset
removes the serializeOld() methods from the serialization base class
as they are no longer used.
2015-12-04 09:48:48 +00:00
Andreas Sandberg
6a05179e13 arm, config: Automatically discover available platforms
Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
b3f7a62876 dev, arm: Disable R/B swap in HDLCD by default
The HDLCD model implements a workaround that swaps the red and blue
channels. This works around an issue in certain old kernels. The new
driver doesn't seem to have this behavior, so disable the workaround
by default and enable it in the affected platforms.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
4aeaaf7985 dev, arm: Split MCC and DCC subsystems
Devices behind the Versatile Express configuration controllers are
currently all lumped into one SimObject. This will make DTB generation
challenging since the DTB assumes them to be in different parts of the
hierarchy. It also makes it hard to model other CoreTiles without also
replicating devices from the motherboard.

This changeset splits the VExpressCoreTileCtrl into two subsystems:
VExpressMCC for all motherboard-related devices and CoreTile2A15DCC
for Core Tile specific devices.
2015-12-04 00:19:05 +00:00
Andreas Sandberg
daa53da594 sim: Add support for generating back traces on errors
Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
2015-12-04 00:12:58 +00:00
Andreas Sandberg
a1aeff27ce arm: Add support for automatic boot loader selection
Add support for automatically selecting a boot loader that matches the
guest system's kernel. Instead of accepting a single boot loader, the
ArmSystem class now accepts a vector of boot loaders. When
initializing a system, the we now look for the first boot loader with
an architecture that matches the kernel.

This changeset makes it possible to use the same system for both
64-bit and 32-bit kernels.
2015-12-03 23:53:37 +00:00
Andreas Sandberg
146dfd0356 dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the
class name) to the TsunamiPChip. If someone decides to implement PCI
for Malta, they should make sure to share code with the Tsunami
implementation if they are similar.
2015-12-03 23:09:34 +00:00
Andreas Sandberg
c84745e2cb config: Fix broken SimObject listing
The gem5 option '--list-sim-objects' is supposed to list all available
SimObjects and their parameters. It currently chokes on SimObjects
with parameters that have an object instance as their default
value. This is caused by __str__ in SimObject trying to resolve its
complete path. When the path resolution method reaches the parent
object (a MetaSimObject since it hasn't been instantiated), it dies
with a Python exception.

This changeset adds a guard to stop path resolution if the parent
object is a MetaSimObject.
2015-12-01 13:01:05 +00:00
Andreas Sandberg
d7e3d94c14 dev: Remove unnecessary header include
--HG--
extra : rebase_source : 64046371962e98413757bc3ab0c0d48dfb11ff1e
2015-11-24 10:13:04 +00:00
Andreas Hansson
72b14f7ef6 mem: Fix search-replace issues in DRAMPower wrapper license
Fix a number of unintentional insertions of 'const'.
2015-11-25 13:52:56 -05:00
Andrew Bardsley
4375678a0d config: Added missing types to JSON/INI Python reader
Added the missing types EthernetAddr and Current to the JSON/INI file
reader example configs/example/read_config.py.

Also added __str__ to EthernetAddr to make values appear in the same form
in JSON an INI files.
2015-11-22 05:10:21 -05:00
Geoffrey Blake
1e1cd2dc01 arm, dev: Fix flash model serialization code typos
The flash model has typos in its serialization code for
unknownPages, locationTable, blockValidEntries, and blockEmptyEntries
arrays where it would save each entry in the array under the same
name in the checkpoint.  This patch fixes these typos.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
488128dab2 cpu: Fix base FP and CC register index in o3 insertThread()
Note that the method is not used, and could possibly be deleted.
2015-11-22 05:10:19 -05:00
Nathanael Premillieu
bbdd7cecb9 arm: Fix fplib 128-bit shift operators
Appease clang.
2015-11-22 05:10:18 -05:00
Andreas Hansson
949437d559 cpu: Fix memory leak in traffic generator
In cases where we discard the packet, make sure to also delete it and
the associated request.
2015-11-22 05:10:16 -05:00
Andreas Sandberg
d57a855e40 cpu: Enforce 1 interrupt controller per thread
Consider it a fatal configuration error if the number of interrupt
controllers doesn't match the number of threads in an SMT
configuration.
2015-11-20 14:50:17 -06:00
Nilay Vaish
90d430d5b3 Merged changesets: 47e2adf7fb1a and b65d4e878ed2
--HG--
extra : amend_source : c51de9ae5387aba6fae8403677054678beceb2ab
2015-11-16 05:10:45 -06:00
Swapnil Haria
08cec03f8e x86: Invalidating TLB entry on page fault
As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel.  This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11
2015-11-16 05:08:54 -06:00
Bjoern A. Zeeb
f50e92d2c7 x86: cpuid: add family to warn() message
doCpuid() has to identical warn messages about unimplemented functions.  Add
the family to the log message to make them distinguishable.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Bjoern A. Zeeb
5c49635f20 x86: pagetable walker: fix typo in comment 2015-11-16 04:58:39 -06:00
Palle Lyckegaard
a95e8ab887 sparc: Make remote debugging with gdb work
Remove sparc V8 TBR register from list of registers since it is not part of
sparc V9. This brings the number of registers in sync with what gdb expects

Without this patch gdb complains about receoved packet too long.

with this patch gdb is able to work properly with gem5 for remote debugging.

Note: gdb is version 7.8
Note: gdb is configured with --target=sparc64-sun-solaris2.8

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-16 04:58:39 -06:00
Nilay Vaish
1d268a1f2d o3: drop unused statistic wbPenalized and wbPenalizedRate 2015-11-16 04:57:52 -06:00
Andreas Sandberg
2a6fe97092 arm: Add missing explicit overrides for classic caches
Make clang when compiling on OSX.
2015-11-15 21:28:00 +00:00
Brad Beckmann
95f20a2905 ruby: added stl vector of ints to be used by SLICC 2015-07-20 09:15:20 -05:00
Tony Gutierrez
d10fac27bc slicc: fixes for the Address to Addr changeset (11025)
misc changes now that Address has become Addr including int to address util
function
2015-11-13 17:30:58 -05:00
Joe Gross
5143d480f3 ruby: add BoolVec
The BoolVec typedef and insertion operator overload function simplify usage of
vectors of type bool
2015-11-13 17:30:56 -05:00
Brad Beckmann
aef8d851bd mem: add boolean to disable PacketQueue's size sanity check
the sanity check, while generally useful for exposing memory system bugs,
may be spurious with respect to GPU workloads, which may generate many more
requests than typical CPU workloads. the large number of requests generated
by the GPU may cause the req/resp queues to back up, thus queueing more than
100 packets.
2015-07-20 09:15:18 -05:00
Andreas Sandberg
0ee18f5b66 dev, arm: Initialized the iccrpr register in the GIC
The IICRPR register in the GIC is currently not being initialized when
the GIC is instantiated. Initialize to the value mandated by the
architecture specification.
2015-11-11 10:18:38 +00:00
Sascha Bischoff
9d23e6d323 dev: Add basic checkpoint support to VirtIO9PProxy device
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
2015-11-05 09:40:12 +00:00
Andreas Sandberg
9719b261a1 dev: Remove unused header includes
Devices should never need to include dev/pciconfall.hh.

--HG--
extra : amend_source : 3a6e56485d432b49e2af22407982fa785c0ccb68
2015-11-09 13:44:15 +00:00
Andreas Sandberg
c62fe43ba9 dev: Don't access the platform directly in PCI devices
Cleanup PCI devices to avoid using the PciDevice::platform pointer
directly. The PCI-specific functionality provided by the Platform
should be accessed through the wrappers in PciDevice.
2015-11-09 13:44:04 +00:00
Andreas Hansson
7433d77fcf mem: Add an option to perform clean writebacks from caches
This patch adds the necessary commands and cache functionality to
allow clean writebacks. This functionality is crucial, especially when
having exclusive (victim) caches. For example, if read-only L1
instruction caches are not sending clean writebacks, there will never
be any spills from the L1 to the L2. At the moment the cache model
defaults to not sending clean writebacks, and this should possibly be
re-evaluated.

The implementation of clean writebacks relies on a new packet command
WritebackClean, which acts much like a Writeback (renamed
WritebackDirty), and also much like a CleanEvict. On eviction of a
clean block the cache either sends a clean evict, or a clean
writeback, and if any copies are still cached upstream the clean
evict/writeback is dropped. Similarly, if a clean evict/writeback
reaches a cache where there are outstanding MSHRs for the block, the
packet is dropped. In the typical case though, the clean writeback
allocates a block in the downstream cache, and marks it writable if
the evicted block was writable.

The patch changes the O3_ARM_v7a L1 cache configuration and the
default L1 caches in config/common/Caches.py
2015-11-06 03:26:43 -05:00
Andreas Hansson
654266f39c mem: Add cache clusivity
This patch adds a parameter to control the cache clusivity, that is if
the cache is mostly inclusive or exclusive. At the moment there is no
intention to support strict policies, and thus the options are: 1)
mostly inclusive, or 2) mostly exclusive.

The choice of policy guides the behaviuor on a cache fill, and a new
helper function, allocOnFill, is created to encapsulate the decision
making process. For the timing mode, the decision is annotated on the
MSHR on sending out the downstream packet, and in atomic we directly
pass the decision to handleFill. We (ab)use the tempBlock in cases
where we are not allocating on fill, leaving the rest of the cache
unaffected. Simple and effective.

This patch also makes it more explicit that multiple caches are
allowed to consider a block writable (this is the case
also before this patch). That is, for a mostly inclusive cache,
multiple caches upstream may also consider the block exclusive. The
caches considering the block writable/exclusive all appear along the
same path to memory, and from a coherency protocol point of view it
works due to the fact that we always snoop upwards in zero time before
querying any downstream cache.

Note that this patch does not introduce clean writebacks. Thus, for
clean lines we are essentially removing a cache level if it is made
mostly exclusive. For example, lines from the read-only L1 instruction
cache or table-walker cache are always clean, and simply get dropped
rather than being passed to the L2. If the L2 is mostly exclusive and
does not allocate on fill it will thus never hold the line. A follow
on patch adds the clean writebacks.

The patch changes the L2 of the O3_ARM_v7a CPU configuration to be
mostly exclusive (and stats are affected accordingly).
2015-11-06 03:26:41 -05:00
Ali Jafri
f02a9338c1 mem: Avoid unnecessary snoops on writebacks and clean evictions
This patch optimises the handling of writebacks and clean evictions
when using a snoop filter. Instead of snooping into the caches to
determine if the block is cached or not, simply set the status based
on the snoop-filter result.
2015-11-06 03:26:40 -05:00
Andreas Hansson
c086c20bd2 mem: Order packet queue only on matching addresses
Instead of conservatively enforcing order for all packets, which may
negatively impact the simulated-system performance, this patch updates
the packet queue such that it only applies the restriction if there
are already packets with the same address in the queue.

The basic need for the order enforcement is due to coherency
interactions where requests/responses to the same cache line must not
over-take each other. We rely on the fact that any packet that needs
order enforcement will have a block-aligned address. Thus, there is no
need for the queue to know about the cacheline size.
2015-11-06 03:26:38 -05:00
Ali Jafri
52c8ae5187 mem: Enforce insertion order on the cache response path
This patch enforces insertion order transmission of packets on the
response path in the cache. Note that the logic to enforce order is
already present in the packet queue, this patch simply turns it on for
queues in the response path.

Without this patch, there are corner cases where a request-response is
faster than a response-response forwarded through the cache. This
violation of queuing order causes problems in the snoop filter leaving
it with inaccurate information. This causes assert failures in the
snoop filter later on.

A follow on patch relaxes the order enforcement in the packet queue to
limit the performance impact.
2015-11-06 03:26:37 -05:00
Andreas Hansson
6b70afd0d4 mem: Use the packet delays and do not just zero them out
This patch updates the I/O devices, bridge and simple memory to take
the packet header and payload delay into account in their latency
calculations. In all cases we add the header delay, i.e. the
accumulated pipeline delay of any crossbars, and the payload delay
needed for deserialisation of any payload.

Due to the additional unknown latency contribution, the packet queue
of the simple memory is changed to use insertion sorting based on the
time stamp. Moreover, since the memory hands out exclusive (non
shared) responses, we also need to ensure ordering for reads to the
same address.
2015-11-06 03:26:36 -05:00
Andreas Hansson
8bc925e36d mem: Align rules for sinking inhibited packets at the slave
This patch aligns how the memory-system slaves, i.e. the various
memory controllers and the bridge, identify and deal with sinking of
inhibited packets that are only useful within the coherent part of the
memory system.

In the future we could shift the onus to the crossbar, and add a
parameter "is_point_of_coherence" that would allow it to sink the
aforementioned packets.
2015-11-06 03:26:35 -05:00
Andreas Hansson
8e55d51aaa mem: Do not treat CleanEvict as a write operation
This patch changes the CleanEvict command type to not be considered a
write. Initially it was made a zero-sized write to match the writeback
command, but as things developed it became clear that it causes more
problems than it solves. For example, the memory modules (and bridge)
should not consider the CleanEvict as a write, but instead discard
it. With this patch it will be neither a read, nor write, and as it
does not need a response the slave will simply sink it.
2015-11-06 03:26:33 -05:00
Andreas Hansson
ac1368df50 mem: Unify delayed packet deletion
This patch unifies how we deal with delayed packet deletion, where the
receiving slave is responsible for deleting the packet, but the
sending agent (e.g. a cache) is still relying on the pointer until the
call to sendTimingReq completes. Previously we used a mix of a
deletion vector and a construct using unique_ptr. With this patch we
ensure all slaves use the latter approach.
2015-11-06 03:26:21 -05:00
Andreas Hansson
2cb5467e85 misc: Appease clang static analyzer
A few minor fixes to issues identified by the clang static analyzer.
2015-11-06 03:26:16 -05:00
Andreas Sandberg
3747e178ed mem: Check the XBar's port queues on functional snoops
The CoherentXBar currently doesn't check its queued slave ports when
receiving a functional snoop. This caused data corruption in cases
when a modified cache lines is forwarded between two caches.

Add the required functional calls into the queued slave ports.
2015-11-06 03:26:09 -05:00
Erfan Azarkhish
845a10e330 mem: hmc: minor fixes
This patch performs two minor fixes to DRAMCtrl.py and xbar.hh in favor of the
HMC patch series.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-03 12:17:58 -06:00
Erfan Azarkhish
7e3f670457 mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube (HMC).
SerialLink is a simple variation of the Bridge class, with the ability to
account for the latency of packet serialization. Also trySendTiming has been
modified to correctly model bandwidth.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-03 12:17:57 -06:00
Erfan Azarkhish
1530e1a690 mem: hmc: adds controller
This patch models a simple HMC Controller. It simply schedules the incoming
packets to HMC Serial Links using a round robin mechanism.  This patch should
be applied in series with other patches modeling a complete HMC device.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-11-03 12:17:56 -06:00
Nathanael Premillieu
e6a6d6445b arm: Add secure flag to TableWalker request when needed 2015-10-29 08:48:26 -04:00
Sascha Bischoff
84c697807f dev: Fix segfault in flash device
Fix a bug in which the flash device would write out of bounds and
could either trigger a segfault and corrupt the memory of other
objects. This was caused by using pageSize in the place of
pagesPerBlock when running the garbage collector.

Also, added an assert to flag this condition in the future.
2015-10-29 08:48:25 -04:00
Sascha Bischoff
84b3452f67 dev: Fix draining for UFSHostDevice and FlashDevice
This patch fixes the drain logic for the UFSHostDevice and the
FlashDevice. In the case of the FlashDevice, the logic for CheckDrain
needed to be reversed, whilst in the case of the UFSHostDevice check
drain was never being called. In both cases the system would never
complete draining if the initial attampt to drain failed.
2015-10-29 08:48:24 -04:00
Victor Garcia
8427d05daa kvm, arm: Fix compilation errors due to API changes
The checkpoint changes, along with the SMT patches have changed a
number of APIs. Adapt the ArmKvmCPU accordingly.
2015-10-29 08:48:23 -04:00
Andreas Hansson
d8b7a652e1 mem: Clarify cache MSHR handling on fill
This patch addresses the upgrading of deferred targets in the MSHR,
and makes it clearer by explicitly calling out what is happening
(deferred targets are promoted if we get exclusivity without asking
for it).
2015-10-29 08:48:20 -04:00
Boris Shingarov
58cb57bacc power: Implement Remote GDB 2015-10-25 16:01:52 -07:00
Andreas Hansson
b48ed9b6c2 x86: Add missing explicit overrides for X86 devices
Make clang >= 3.5 happy when compiling build/X86/gem5.opt on OSX.
2015-10-23 09:51:12 -04:00
Andreas Hansson
fa32ad4941 arm: Add missing explicit overrides for ARM devices
Make clang >= 3.5 happy when compiling build/ARM/gem5.opt on OSX.
2015-10-23 09:51:11 -04:00
Andreas Hansson
2a1f49fae6 mem: Pass snoop retries through the CommMonitor
Allow the monitor to be placed after a snooping port, and do not fail
on snoop retries, but instead pass them on to the slave port.
2015-10-14 13:32:28 -04:00
Nilay Vaish
4453537ead ruby: profiler: provide the number of vnets through ruby system
The aim is to ultimately do away with the static function
Network::getNumberOfVirtualNetworks().
2015-10-14 00:29:43 -05:00
Nilay Vaish
f1b6d1913c ruby: remove unused functionalRead() function.
Not required since functional reads cannot rely on messages that are inflight.
2015-10-14 00:29:39 -05:00
Nilay Vaish
7defb594b3 ruby: garnet: flexible: refactor flit 2015-10-14 00:29:38 -05:00
Andreas Hansson
2ac04c11ac misc: Add explicit overrides and fix other clang >= 3.5 issues
This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
2015-10-12 04:08:01 -04:00
Andreas Hansson
22c04190c6 misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
2015-10-12 04:07:59 -04:00
Joel Hestness
1f2e7c1aaa sim: Don't quiesce UDelayEvents with 0 latency
ARM uses UDelayEvents to emulate kernel __*udelay functions and speed up
simulation. UDelayEvents call Pseudoinst::quiesceNs to quiesce the system for
a specified delay. Changeset 10341:0b4d10f53c2d introduced the requirement
that any quiesce process that is started must also be completed by scheduling
an EndQuiesceEvent. This change causes the CPU to hang if an IsQuiesce
instruction is executed, but the corresponding EndQuiesceEvent is not
scheduled.

Changeset 11058:d0934b57735a introduces a fix for uses of PseudoInst::quiesce*
that would conditionally execute the EndQuiesceEvent. ARM UDelayEvents specify
quiesce period of 0 ns (src/arch/arm/linux/system.cc), so changeset 11058
causes these events to now execute full quiesce processes, greatly increasing
the total instructions executed in kernel delay loops and slowing simulation.

This patch updates the UDelayEvent to conditionally execute
PseudoInst::quiesceNs (**a quiesce operation**) only if the specified
delay is >0 ns. The result is ARM delay loops no longer execute instructions
for quiesce handling, and regression time returns to normal.
2015-10-10 16:45:38 -05:00
Rekai Gonzalez Alberquilla
d3d159749a isa: Add parameter to pick different decoder inside ISA
The decoder is responsible for splitting instructions in micro
operations (uops). Given that different micro architectures may split
operations differently, this patch allows to specify which micro
architecture each isa implements, so different cores in the system can
split instructions differently, also decoupling uop splitting
(microArch) from ISA (Arch). This is done making the decodification
calls templates that receive a type 'DecoderFlavour' that maps the
name of the operation to the class that implements it. This way there
is only one selection point (converting the command line enum to the
appropriate DecodeFeatures object). In addition, there is no explicit
code replication: template instantiation hides that, and the compiler
should be able to resolve a number of things at compile-time.
2015-10-09 14:50:54 -05:00
Dylan Johnson
7624fc1fb4 sim: Add relative break scheduling
Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
2015-10-09 14:27:09 -05:00
Steve Reinhardt
90c279e4b1 arch: clean up isa_parser error handling
Although some decent error messages were getting generated inside
isa_parser.py, they weren't always getting printed because of the
screwy way we were handling exceptions.  (Basically an inner
exception would get hidden by an outer exception, and the more
informative inner error message would not get printed.)

Also line numbers were messed up, since they were taken from the
lexer, which is typically a token (or more) ahead of the grammar
rule that's being matched.  Using the 'lineno' attribute that
PLY associates with the grammar production is more accurate.
The new LineTracker class extends lineno to track filenames as
well as line numbers.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
2511490c9c sim: add ExecMacro to Exec* compound debug flags
Really should have been there in the first place, IMO.
Makes debugging x86 execution a lot easier.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
4b7c1fe610 sim: print pid in output header
This information is useful if you have a bunch of simulations running
and want to know which one to kill, but you've neglected to take
advantage of the previous patch and embed the pid in your output path.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
a2c875c746 x86: implement rcpps and rcpss SSE insts
These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.

This code was basically developed by copying the code for
sqrtps and sqrtss.  The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.
2015-10-06 17:26:50 -07:00
Steve Reinhardt
57b9f53afa x86: implement fild, fucomi, and fucomip x87 insts
fild loads an integer value into the x87 top of stack register.
fucomi/fucomip compare two x87 register values (the latter
also doing a stack pop).
These instructions are used by some versions of GNU libstdc++.
2015-10-06 17:26:50 -07:00
Dylan Johnson
71b1c6ce76 sim: Add ability to break at specific kernel function
Adds a GDB callable function that sets a breakpoint at
the beginning of a kernel function.
2015-09-02 13:34:19 -05:00
Curtis Dunham
02881a7bf3 base: remove Trace::enabled flag
The DTRACE() macro tests both Trace::enabled and the specific flag. This
change uses the same administrative interface for enabling/disabling
tracing, but masks the SimpleFlags settings directly. This eliminates a
load for every DTRACE() test, e.g. DPRINTF.
2015-09-30 15:21:55 -05:00
Mitch Hayenga
ccf4f6c3d7 arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is
detected.  Having 2 SMT threads share a TLB resulted in these not being
updated as required.  This patch adds a thread context identifer to
assist in the invalidation of these variables.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
9e07a7504c cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
a5c4eb3de9 isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
e255fa053f arm: SMT MPIDR Setting
Changes assignment of the MPIDR for multi-threaded systems only.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
fafa83ed32 cpu: Add per-thread monitors
Adds per-thread address monitors to support FullSystem SMT.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
582a0148b4 config,cpu: Add SMT support to Atomic and Timing CPUs
Adds SMT support to the "simple" CPU models so that they can be
used with other SMT-supported CPUs. Example usage: this enables
the TimingSimpleCPU to be used to warmup caches before swapping to
detailed mode with the in-order or out-of-order based CPU models.
2015-09-30 11:14:19 -05:00
Mitch Hayenga
52d521e433 cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
cores) caused failures due to the CPU id assignment logic.  The comment
about thread assignment (worrying about core 0 not having tid 0) seems
not to be valid given that our configuration scripts initialize them in
order.

This removes that constraint so a heterogenously threaded sytem can work.
2015-09-30 11:14:19 -05:00
Joel Hestness
c05d268cfa ruby: Fix CacheMemory allocate leak
If a cache entry permission was previously set to NotPresent, but the entry was
not deleted, a following cache allocation can cause the entry to be leaked by
setting the entry pointer to a newly allocated entry. To eliminate this
possibility, check if the new entry is different from the old one, and if so,
delete the old one.
2015-09-29 09:28:26 -05:00
Joel Hestness
0ecaab4ea8 arch, x86: Delete packet in IntDevice::recvResponse
IntDevice::recvResponse is called from two places in current mainline: (1) the
short circuit path of X86ISA::IntDevice::IntMasterPort::sendMessage for atomic
mode, and (2) the full request->response path to and from the x86 interrupts
device (finally called from MessageMasterPort::recvTimingResp). In the former
case, the packet was deleted correctly, but in the latter case, the packet and
request leak. To fix the leak, move request and packet deletion into IntDevice
inherited class implementations of recvResponse.
2015-09-29 09:28:26 -05:00
Joel Hestness
b80024ee7d ruby: RubyPort delete snoop requests
In RubyPort::ruby_eviction_callback, prior changes fixed a memory leak caused
by instantiating separate packets for each port that the eviction was forwarded
to. That change, however, left the instantiated request to also leak. Allocate
it on the stack to avoid the leak.
2015-09-29 09:28:25 -05:00
Joel Hestness
7b70fa02ae ruby: Fix memory leak in AbstractController
Recent changes to memory access queuing allocate requests for packets sent to
memory controllers, but did not free the requests. Delete them to avoid leaks.
2015-09-29 09:28:25 -05:00
Joel Hestness
501705eaf0 ruby: RubyMemoryControl delete requests
Changes to the RubyMemoryControl removed the dequeue function, which deleted
MemoryNode instances. This results in leaked MemoryNode instances. Correctly
delete these instances.
2015-09-29 09:25:29 -05:00
Joel Hestness
395b31f518 syscall_emul: Bandage readlink /proc/self/exe
The recent changeset to readlink() to handle reading the /proc/self/exe link
introduces a number of problems. This patch fixes two:

1) Because readlink() called on /proc/self/exe now uses LiveProcess::progName()
to find the binary path, it will only get the zeroth parameter of the simulated
system command line. However, if a config script also specifies the process'
executable, the executable parameter is used to create the LiveProcess rather
than the zeroth command line parameter. Thus, the zeroth command line parameter
is not necessarily the correct path to the binary executing in the simulated
system. To fix this, add a LiveProcess data member, 'executable', which is
correctly set during instantiation and returned from progName().

2) If a config script allows a user to pass a relative path as the zeroth
simulated system command line parameter or process executable, readlink() will
incorrecly return a relative path when called on '/proc/self/exe'.
/proc/self/exe is always set to a full path, so running benchmarks can fail if
a relative path is returned. To fix this, clean up the handling of
LiveProcess::progName() within readlink() to get the full binary path.

NOTE: This patch still leaves the potential problem that host full path to the
binary bleeds into the simulated system, potentially causing the appearance of
non-deterministic simulated system execution.
2015-09-29 09:25:20 -05:00
Andreas Hansson
9a0129dcbf mem: Add PacketInfo to be used for packet probe points
This patch fixes a use-after-delete issue in the packet probe points
by adding a PacketInfo struct to retain the key fields before passing
the packet onwards. We want to probe the packet after it is
successfully sent, but by that time the fields may be modified, and
the packet may even be deleted.

Amazingly enough the issue has gone undetected for months, and only
recently popped up in our regressions.
2015-09-25 13:25:34 -04:00
Andreas Hansson
a9a7002a3b mem: Add check for block status on WriteLineReq fill
More checks to help with understanding of functionality.
2015-09-25 07:26:58 -04:00
Andreas Hansson
012dd52dc2 mem: Fix WriteLineReq fill behaviour
This patch fixes issues in the interactions between deferred snoops
and WriteLineReq. More specifically, the patch addresses an issue
where deferred snoops caused assertion failures when being serviced on
the arrival of an InvalidateResp. The response packet was perceived to
be invalidating, when actually it is not for the cache that sent out
the original invalidation request.
2015-09-25 07:26:58 -04:00
Andreas Hansson
5570aa9e9a mem: Comment clean-up for the snoop filter
Merely fixing up some style issues and adding more comments.
2015-09-25 07:26:57 -04:00
Andreas Hansson
7d4e89d4e0 mem: Avoid adding and then removing empty snoop-filter items
This patch tidies up how we access the snoop filter for snoops, and
avoids adding items only to later remove them.
2015-09-25 07:26:57 -04:00
Andreas Hansson
ca163a80e2 mem: Only track snooping ports in the snoop filter
This patch changes the tracking of ports in the snoop filter to use
local dense port IDs so that we can have 64 snooping ports (rather
than crossbar slave ports). This is achieved by adding a simple
remapping vector that translates the actal port IDs into the local
slave IDs used in the SnoopMask.

Ultimately this patch allows us to scale to much larger systems
without introducing a hierarchy of crossbars.
2015-09-25 07:26:57 -04:00
Ali Jafri
3aa87251d7 mem: Add snoop filters to L2 crossbars, and check size
This patch adds a snoop filter to the L2XBar. For now we refrain from
globally adding a snoop filter to the SystemXBar, since the latter is
also used in systems without caches. In scenarios without caches the
snoop filter will not see any writeback/clean evicts from the CPU
ports, despite the fact that they are snooping. To avoid inadvertent
use of the snoop filter in these cases we leave it out for now.

A size check is added to the snoop filter, merely to ensure it does
not grow beyond the total capacity of the caches above it. The size
has to be set manually, and a value of 8 MByte is choosen as suitably
high default.
2015-09-25 07:26:57 -04:00
Andreas Hansson
0c5a98f9d1 mem: Store snoop filter lookup result to avoid second lookup
This patch introduces a private member storing the iterator from the
lookupRequest call, such that it can be re-used when the request
eventually finishes. The method previously called updateRequest is
renamed finishRequest to make it more clear that the two functions
must be called together.
2015-09-25 07:26:57 -04:00
Ali Jafri
ceec2bb02c mem: Add snoops for CleanEvicts and Writebacks in atomic mode
This patch mirrors the logic in timing mode which sends up snoops to
check for cached copies before sending CleanEvicts and Writebacks down
the memory hierarchy. In case there is a copy in a cache above,
discard CleanEvicts and set the BLOCK_CACHED flag in Writebacks so
that writebacks do not reset the cache residency bit in the snoop
filter below.
2015-09-25 07:26:57 -04:00
Ali Jafri
6ac356f93b mem: Add CleanEvict and Writeback support to snoop filters
This patch adds the functionality to properly track CleanEvicts and
Writebacks in the snoop filter. Previously there were no CleanEvicts, and
Writebacks did not send up snoops to ensure there were no copies in
caches above. Hence a writeback could never erase an entry from the
snoop filter.

When a CleanEvict message reaches a snoop filter, it confirms that the
BLOCK_CACHED flag is not set and resets the bits corresponding to the
CleanEvict address and port it arrived on. If none of the other peer
caches have (or have requested) the block, the snoop filter forwards
the CleanEvict to lower levels of memory. In case of a Writeback
message, the snoop filter checks if the BLOCK_CACHED flag is not set
and only then resets the bits corresponding to the Writeback
address. If any of the other peer caches have (or has requested) the
same block, the snoop filter sets the BLOCK_CACHED flag in the
Writeback before forwarding it to lower levels of memory heirarachy.
2015-09-25 07:26:57 -04:00
Ali Jafri
79d3dbcea8 mem: Add check for snooping ports in the snoop filter
This patch prevents the snoop filter from creating items for requests
originating from non-snooping ports. The allocation decision is thus
based both on the cacheability of the line, and the snooping status of
the source port. Ultimately we should check if the source of the
packet is caching, since also the CPU ports are snooping (but not
allocating). Thus, at the moment we rely on the snoop filter being
used together with caches.

The patch also transitions to use the Packet::getBlockAddr in
determining the line address.
2015-09-25 07:26:57 -04:00
Andreas Hansson
462c288a75 mem: Make the coherent crossbar account for timing snoops
This patch introduces the concept of a snoop latency. Given the
requirement to snoop and forward packets in zero time (due to the
coherency mechanism), the latency is accounted for later.

On a snoop, we establish the latency, and later add it to the header
delay of the packet. To allow multiple caches to contribute to the
snoop latency, we use a separate variable in the packet, and then take
the maximum before adding it to the header delay.
2015-09-25 07:13:54 -04:00
Andreas Hansson
3bd78a141e mem: Do not include snoop-filter latency in crossbar occupancy
This patch ensures that the snoop-filter latency only contributes to
the packet latency, and not to the crossbar throughput/occupancy. In
essence we treat the snoop-filter lookup as pipelined.
2015-09-25 06:45:52 -04:00
Nilay Vaish
4647e4e961 ruby: simple network: refactor code
Drops an unused variable and marks three variables as const.
2015-09-24 08:41:24 -05:00
Nilay Vaish
b3a3b0b6cf ruby: garnet: refactor code in network links 2015-09-23 11:23:11 -05:00
Nilay Vaish
6bd7aa1f20 ruby: bloom filters: refactor code 2015-09-23 11:23:10 -05:00
Nilay Vaish
c2376918a5 ruby: abstract controller: mark some variables as const 2015-09-23 11:23:10 -05:00
Wendy Elsasser
61c38524ce mem: Add initial HBM configurations
Created the following HBM configurations:
1) HBM gen1 (x128/CH), 2Gb die, 4H stack, 1Gbps, 8 channels
2) HBM gen2 (x64/PC), 8Gb die, 4H stack, 1Gbps, 16 pseudo-channels

The configuration values are based on:
- The HBM gen1 public JEDEC spec
- Publically released data from MemCon presentations
- Timing extrapolated from existing LPDDR configurations

Will adjust once specs become available.
2015-09-22 13:17:53 -05:00
Nilay Vaish
8975053864 ruby: garnet: mark some variables as const 2015-09-18 13:27:48 -05:00
Nilay Vaish
96c999fe88 ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements.  So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals.  This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address.  This function has been put to use in some of the
places.  At other places, change has been made to print just the address in
hex.
2015-09-18 13:27:47 -05:00
Nilay Vaish
216529bf18 ruby: slicc: derive DataMember class from Var instead of PairContainer
The DataMember class in Type.py was being derived from PairContainer.  A
separate Var object was also created for the DataMember.  This meant some
duplication of across the members of these two classes (Var and DataMember).
This patch changes DataMember from Var instead.  There is no obvious reason to
derive from PairContainer which can only hold pairs, something that Var class
already supports.  The only thing that DataMember has over Var is init_code,
which is being retained.  This change would later on help in having pointers
in DataMembers.
2015-09-18 13:27:47 -05:00
Tony Gutierrez
b3eb0d1423 ruby: update WireBuffer API to match that of MessageBuffer
this patch updates the WireBuffer API to mirror the changes in revision 11111
2015-09-17 14:00:33 -04:00
Lena Olson
3225379cc0 ruby: Add missing block deallocations in MOESI_hammer
Some blocks in MOESI hammer were not getting deallocated when they were set to
an idle state (e.g. by invalidate or other_getx/s messages).  While
functionally correct, this caused some bad effects on performance, such as
blocks in I in the L1s getting sent to the L2 upon eviction, in turn evicting
valid blocks.  Also, if a valid block was in LRU, that block could be evicted
rather than a block in I.  This patch adds in the missing deallocations.

Committed by: Nilay Vaish<nilay@cs.wisc.edu>
2015-09-16 20:18:40 -05:00
Joe Gross
950e431d87 ruby: fix message buffer init order
The recent changes to make MessageBuffers SimObjects required them to be
initialized in a particular order, which could break some protocols. Fix this
by calling initNetQueues on the external nodes of each external link in the
constructor of Network.

This patch also refactors the duplicated code for checking network allocation
and setting net queues (which are called by initNetQueues) from the simple and
garnet networks to be in Network.
2015-09-16 13:10:42 -04:00
Nilay Vaish
cd9e445813 ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for
buffering messages by components in ruby.  These structures would no longer
maintain pointers to clock objects.  Functions in these structures have been
changed to take as input current time in Tick.  Similarly, these structures
will not operate on Cycle valued latencies for different operations.  The
corresponding functions would need to be provided with these latencies by
components invoking the relevant functions.  These latencies should also be
in Ticks.

I felt the need for these changes while trying to speed up ruby.  The ultimate
aim is to eliminate Consumer class and replace it with an EventManager object in
the MessageBuffer and TimerTable classes.  This object would be used for
scheduling events.  The event itself would contain information on the object and
function to be invoked.

In hindsight, it seems I should have done this while I was moving away from use
of a single global clock in the memory system.  That change led to introduction
of clock objects that replaced the global clock object.  It never crossed my
mind that having clock object pointers is not a good design.  And now I really
don't like the fact that we have separate consumer, receiver and sender
pointers in message buffers.
2015-09-16 11:59:56 -05:00
Nilay Vaish
78a1245b41 ruby: remove unused function removeRequest() 2015-09-16 11:59:55 -05:00
Nilay Vaish
4b19e06644 ruby: sequencer: remove commented out function printProgress() 2015-09-16 11:59:55 -05:00
David Hashe
b6b972da99 ruby: rename System.{hh,cc} to RubySystem.{hh,cc}
The eventual aim of this change is to pass RubySystem pointers through to
objects generated from the SLICC protocol code.

Because some of these objects need to dereference their RubySystem pointers,
they need access to the System.hh header file.

In src/mem/ruby/SConscript, the MakeInclude function creates single-line header
files in the build directory that do nothing except include the corresponding
header file from the source tree.

However, SLICC also generates a list of header files from its symbol table, and
writes it to mem/protocol/Types.hh in the build directory. This code assumes
that the header file name is the same as the class name.

The end result of this is the many of the generated slicc files try to include
RubySystem.hh, when the file they really need is System.hh. The path of least
resistence is just to rename System.hh to RubySystem.hh.

--HG--
rename : src/mem/ruby/system/System.cc => src/mem/ruby/system/RubySystem.cc
rename : src/mem/ruby/system/System.hh => src/mem/ruby/system/RubySystem.hh
2015-09-16 12:03:03 -04:00
Anthony Gutierrez
3edadb0bd3 slicc: export uint64_t instead of uint64 2015-09-16 12:01:39 -04:00
Palle Lyckegaard
3de9def6c1 sparc: writing to tick_cmpr should not cause a panic
This register is writable according to UA2005

Tried to boot NetBSD which starts the kernel by writing to the tick_cmpr
register.  Without the patch gem5 crashes with a panic.  With the patch NetBSD
starts to boot normally (although sun4v support in NetBSD is not complete yet)

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-15 08:14:07 -05:00
Dongxue Zhang
58ec70444d dev: IDE Disk: Handle bad IDE image size
Handle bad IDE disk image size 0. When image size is 0, gem5 will cause an
exception with log "Floating point exception (core dumped)".

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-15 08:14:07 -05:00
Andrew Lukefahr
543efd5ca6 cpu: pred: Local Predictor Reset in Tournament Predictor
When a branch gets squashed, it's speculative branch predictor state should get
rolled back in squash().  However, only the globalHistory state was being
rolled back.  This patch adds (at least some) support for rolling back the
local predictor state also.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-15 08:14:07 -05:00
Hongil Yoon
fb0f9884e2 cpu, o3: consider split requests for LSQ checksnoop operations
This patch enables instructions in LSQ to track two physical addresses for
corresponding two split requests. Later, the information is used in
checksnoop() to search for/invalidate the corresponding LD instructions.

The current implementation has kept track of only the physical address that is
referenced by the first split request. Thus, for checksnoop(), the line
accessed by the second request has not been considered, causing potential
correctness issues.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-09-15 08:14:06 -05:00
Nilay Vaish
6bee1d9124 ruby: topology: refactor code. 2015-09-14 10:14:50 -05:00
Nilay Vaish
4e898be762 ruby: slicc: remove member buffer_expr from Var class
This was added by changeset 51f40b101a56.  Instead, buffer_expr would now be
associated with the InPort class.
2015-09-14 10:04:55 -05:00
Nilay Vaish
78bf2dfeac merged with 62e1504b9c64 2015-09-12 16:23:47 -05:00
Nilay Vaish
8b199b775e ruby: perfect switch: refactor code
Refactored the code in operateVnet(), moved partly to a new function
operateMessageBuffer().  This is required since a later patch moves to having a
wakeup event per MessageBuffer instead of one event for the entire Switch.
2015-09-12 16:16:17 -05:00
Nilay Vaish
25cd13dbf1 ruby: simple network: store Switch* in PerfectSwitch and Throttle
There are two reasons for doing so:

a. provide a source of clock to PerfectSwitch. A follow on patch removes sender
and receiver pointers from MessageBuffer means that the object owning the
buffer should have some way of providing timing info.

b. schedule events.  A follow on patch removes the consumer class.  So the
PerfectSwitch needs some EventManager object to schedule events on its own.
2015-09-12 16:16:03 -05:00
Andreas Sandberg
a151786741 dev: Add an underrun statistic to the HDLCD controller
Add a stat that counts buffer underruns in the HDLCD controller. The
stat counts at most one underrun per frame since the controller aborts
the current frame if it underruns.
2015-09-11 15:56:09 +01:00
Andreas Sandberg
f7055e9215 dev, arm: Rewrite the HDLCD controller
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:

   * Broken/missing interrupt support (VSync, underrun, DMA end)
   * Fragile resolution changes (changing resolutions used
     to cause assertion errors).
   * Support for resolutions with a width that isn't divisible by 32.
   * The pixel clock can now be set dynamically.

This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
2015-09-11 15:55:46 +01:00
Nilay Vaish
f611d4f22e ruby: slicc: remove nextLineHack from Type.py 2015-09-08 19:32:04 -05:00
Nilay Vaish
740984b30b ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches.  While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function.  This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.

The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
2015-09-05 09:35:39 -05:00
Nilay Vaish
8f29298bc7 ruby: adds set and way indices to AbstractCacheEntry 2015-09-05 09:35:31 -05:00
Nilay Vaish
abcc67010e ruby: set: reimplement using std::bitset
The current Set data structure is slow and therefore is being reimplemented
using std::bitset. A maximum limit of 64 is being set on the number of
controllers of each type.  This means that for simulating a system with more
controllers of a given type, one would need to change the value of the variable
NUMBER_BITS_PER_SET
2015-09-05 09:34:25 -05:00
Nilay Vaish
7962a81148 ruby: declare all protocol message buffers as parameters
MessageBuffer is a SimObject now.  There were protocols that still declared
some of the message buffers are variables of the controller, but not as input
parameters.  Special handling was required for these variables in the SLICC
compiler.  This patch changes this.  Now all message buffers are declared as
input parameters.
2015-09-05 09:34:24 -05:00
Andreas Hansson
419d437385 mem: Avoid setting markPending if not needed
In cases where a newly added target does not have any upstream MSHR to
mark as downstreamPending, remember that nothing is marked. This
allows us to avoid attempting to find the MSHR as part of the clearing
of downstreamPending.
2015-09-04 13:14:03 -04:00
Andreas Hansson
2c50a83ba2 mem: Tidy up CacheSet
Minor tweaks and house keeping.
2015-09-04 13:14:01 -04:00
Andreas Hansson
76088fb9ca mem: Tidy up the snoop state-transition logic
Remove broken and unused option to pass dirty data on non-exclusive
snoops. Also beef up the comments a bit.
2015-09-04 13:13:58 -04:00
Andreas Hansson
8e74d5484f sim: Fix time unit in abort message 2015-09-04 13:13:55 -04:00
Curtis Dunham
87b9da2df4 sim: tag-based checkpoint versioning
This commit addresses gem5 checkpoints' linear versioning bottleneck.
Since development is distributed across many private trees, there exists
a sort of 'race' for checkpoint version numbers: internally a checkpoint
version may be used but then resynchronizing with the external tree causes
a conflict on that version.  This change replaces the linear version number
with a set of unique strings called tags.  Now the only conflicts that can
arise are of tag names, where collisions are much easier to avoid.

The checkpoint upgrader (util/cpt_upgrader.py) upgrades the version
representation, as one would expect. Each tag version implements its
upgrader code in a python file in the util/cpt_upgraders directory
rather than adding a function to the upgrader script itself.

The version tags are stored in the 'Globals' section rather than 'root'
(as the version was previously) because 'Globals' gets unserialized
first and can provide a warning before any other unserialization errors
can occur.
2015-09-02 15:23:30 -05:00
Curtis Dunham
62e0344aef sim: support checkpointing std::set<std::string>'s
This is in support of tag-based checkpoint versioning; the version tags
are stored in string sets. This commit adds such support.
2015-09-02 15:19:44 -05:00
Curtis Dunham
1ad5b77229 sim: make warning for absent optional parameters optional
This is in support of tag-based checkpoint versioning. It should be
possible to examine an optional parameter in a checkpoint during
unserialization and not have it throw a warning.
2015-09-02 15:19:43 -05:00
Nilay Vaish
fe47f0a72f ruby: remove random seed
We no longer use the C library based random number generator: random().
Instead we use the C++ library provided rng.  So setting the random seed for
the RubySystem class has no effect.  Hence the variable and the corresponding
option are being dropped.
2015-09-01 15:50:33 -05:00
Nilay Vaish
5d555df359 ruby: directory memory: drop unused variable. 2015-09-01 15:50:32 -05:00
Andreas Sandberg
05852e698a sim: Remove broken AutoSerialize support from the event queue
Event auto-serialization no longer in use and has been broken ever
since the introduction of PDES support almost two years
ago. Additionally, serializing the individual event queues is
undesirable since it exposes the thread structure of the
simulator. What this means in practice is that the number of threads
in the simulator must be the same when taking a checkpoint and when
loading the checkpoint.

This changeset removes support for the AutoSerialize event flag and
the associated serialization code.
2015-09-01 15:28:45 +01:00
Andreas Sandberg
53001e6e09 dev: Remove auto-serialization dependency in EtherLink
EtherLink currently uses a fire-and-forget link delay event that
delays sending of packets by a fixed number of ticks. In order to
serialize this event, it relies on the event queue's auto
serialization support. However, support for event auto serialization
has been broken for more than two years, which means that checkpoints
of multi-system setups are likely to drop in-flight packets.

This changeset the replaces rewrites this part of the EtherLink to use
a packet queue instead. The queue contains a (tick, packet) tuple. The
tick indicates when the packet will be ready. Instead of relying on
event autoserialization, we now explicitly serialize the packet queue
in the EhterLink::Link class.

Note that this changeset changes the way in-flight packages are
serialized. Old checkpoints will still load, but in-flight packets
will be dropped (just as before). There has been no attempt to upgrade
checkpoints since this would actually change the behavior of existing
checkpoints.
2015-09-01 15:28:44 +01:00
Andreas Sandberg
0572dc3c6e sim: Remove autoserialize support for exit events
This changeset removes the support for the autoserialize parameter in
GlobalSimLoopExitEvent (including exitSimLoop()) and
LocalSimLoopExitEvent.

Auto-serialization of the LocalSimLoopExitEvent was never used, so
this is not expected to affect anything. However, it was sometimes
used for GlobalSimLoopExitEvent. Unfortunately, serialization of
global events has never been supported, so checkpoints with such
events will currently cause simulation panics.

The serialize parameter to exitSimLoop() has been left in-place to
maintain API compatibility (removing it would affect m5ops). Instead
of just dropping it, we now print a warning if the parameter is set
and the exit event is scheduled in the future (i.e., not at the
current tick).
2015-09-01 13:41:45 +01:00
Andreas Sandberg
1fa7a4394c sim: Remove unused SerializeBuilder interface 2015-09-01 13:40:28 +01:00
Andreas Sandberg
4411c97ee1 sim: Replace fromInt/fromSimObject with decltype 2015-09-01 13:40:25 +01:00
Andreas Sandberg
db465fd788 sim: Move SimObject resolver to sim_object.hh
The object resolver isn't serialization specific and shouldn't live in
serialize.hh. Move it to sim_object.hh since it queries to the
SimObject hierarchy.
2015-09-01 13:40:05 +01:00
Nilay Vaish
a60a93eb05 ruby: specify number of vnets for each protocol
The default value for number of virtual networks is being removed.  Each protocol
should now specify the value it needs.
2015-08-30 12:24:18 -05:00
Nilay Vaish
bf8ae288fa ruby: network: drop member m_in_use
This member indicates whether or not a particular virtual network is in use.
Instead of having a default big value for the number of virtual networks and
then checking whether a virtual network is in use, the next patch removes the
default value and the protocol configuration file would now specify the
number of virtual networks it requires.

Additionally, the patch also refactors some of the code used for computing the
virtual channel next in the round robin order.
2015-08-30 12:24:18 -05:00
Nilay Vaish
7175db4a3f ruby: garnet: mark few functions const in BaseGarnetNetwork.hh 2015-08-30 12:24:18 -05:00
Nilay Vaish
426e38af8b ruby: slicc: avoid duplicate code for function argument check
Both FuncCallExprAST and MethodCallExprAST had code for checking the arguments
with which a function is being called.  The patch does away with this
duplication.  Now the code for checking function call arguments resides in the
Func class.
2015-08-30 10:52:58 -05:00
Nilay Vaish
4727fc26f8 ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
2015-08-29 10:19:23 -05:00
Andreas Sandberg
e9d6bf5e35 ruby: Use the const serialize interface in RubySystem
The new serialization code (kudos to Tim Jones) moves all of the state
mangling in RubySystem to memWriteback. This makes it possible to use
the new const serialization interface.

This changeset moves the cache recorder cleanup from the checkpoint()
method to drainResume() to make checkpointing truly constant and
updates the checkpointing code to use the new interface.
2015-08-28 10:58:44 +01:00
Nilay Vaish
fc3d34a488 ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory.  This is unnecessary once the required CacheEntry object
is available.  Thus some of the calls to findTagInSet() are avoided.
2015-08-27 12:51:40 -05:00
Emilio Castillo
88b1fd82a6 cpu: quiesce pseudoinsts: Always do full quiesce
The O3CPU blocks the Fetch when it sees a quiesce instruction (IsQuiesce flag).
When the inst. is executed, a quiesce event is created to reactivate the
context and unblock the Fetch.

If the quiesceNs or quiesceCycles are called with a value of 0, the
QuiesceEvent will not be created and the Fetch stage will remain blocked.


Committed by Joel Hestness <jthestness@gmail.com>
2015-08-26 14:20:30 -05:00
Andreas Hansson
ce4f6a9020 mem: Revert requirement on packet addr/size always valid
This patch reverts part of (842f56345a42), as apparently there are
use-cases outside the main repository relying on the late setting of
the physical address.
2015-08-24 05:03:45 -04:00
Andreas Hansson
daaae3744d mem: Reflect that packet address and size are always valid
This patch simplifies the packet, and removes the possibility of
creating a packet without a valid address and/or size. Under no
circumstances are these fields set at a later point, and thus they
really have to be provided at construction time.

The patch also fixes a case there the MinorCPU creates a packet
without a valid address and size, only to later delete it.
2015-08-21 07:03:27 -04:00
Andreas Hansson
6eb434c8a2 arm, mem: Remove unused CLEAR_LL request flag
Cleaning up dead code. The CLREX stores zero directly to
MISCREG_LOCKFLAG and so the request flag is no longer needed. The
corresponding functionality in the cache tags is also removed.
2015-08-21 07:03:25 -04:00