Andreas Sandberg daa53da594 sim: Add support for generating back traces on errors ... Add functionality to generate a back trace if gem5 crashes (SIGABRT or SIGSEGV). The current implementation uses glibc's stack traversal support if available and stubs out the call to print_backtrace() otherwise.		2015-12-04 00:12:58 +00:00
..
arch	arm: Add support for automatic boot loader selection	2015-12-03 23:53:37 +00:00
base	sim: Add support for generating back traces on errors	2015-12-04 00:12:58 +00:00
cpu	cpu: Fix base FP and CC register index in o3 insertThread()	2015-11-22 05:10:19 -05:00
dev	dev, mips: Remove the unused MaltaPChip class	2015-12-03 23:09:34 +00:00
doc	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	misc: Remove redundant compiler-specific defines	2015-10-12 04:07:59 -04:00
mem	mem: Fix search-replace issues in DRAMPower wrapper license	2015-11-25 13:52:56 -05:00
proto	cpu: add support for outputing a protobuf formatted CPU trace	2015-02-16 03:32:38 -05:00
python	config: Fix broken SimObject listing	2015-12-01 13:01:05 +00:00
sim	sim: Add support for generating back traces on errors	2015-12-04 00:12:58 +00:00
unittest	base: Rewrite the CircleBuf to fix bugs and add serialization	2015-08-07 09:59:19 +01:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	sim: tag-based checkpoint versioning	2015-09-02 15:23:30 -05:00