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misc: Remove redundant compiler-specific defines

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This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
This commit is contained in:
Andreas Hansson 2015-10-12 04:07:59 -04:00
parent 735c4a8766
commit 22c04190c6
168 changed files with 512 additions and 628 deletions
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4
src/arch/alpha/isa.hh
View file

@ -92,8 +92,8 @@ namespace AlphaISA
memset(ipr, 0, sizeof(ipr));
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
int
flattenIntIndex(int reg) const

4
src/arch/alpha/kernel_stats.hh
View file

@ -86,8 +86,8 @@ class Statistics : public ::Kernel::Statistics
void setIdleProcess(Addr idle, ThreadContext *tc);
public:
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
} // namespace Kernel

4
src/arch/alpha/pagetable.hh
View file

@ -142,8 +142,8 @@ struct TlbEntry : public Serializable
return ppn << PageShift;
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
} // namespace AlphaISA

2
src/arch/alpha/process.hh
View file

@ -42,7 +42,7 @@ class AlphaLiveProcess : public LiveProcess
protected:
AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void loadState(CheckpointIn &cp) override;
void initState();
void argsInit(int intSize, int pageSize);

4
src/arch/alpha/system.hh
View file

@ -60,8 +60,8 @@ class AlphaSystem : public System
/**
* Serialization stuff
*/
void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serializeSymtab(CheckpointOut &cp) const override;
void unserializeSymtab(CheckpointIn &cp) override;
/** Override startup() to provide a path to call setupFuncEvents()
*/

4
src/arch/alpha/tlb.hh
View file

@ -117,8 +117,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req, bool itb = false);
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
// Most recently used page table entries
TlbEntry *EntryCache[3];

4
src/arch/arm/isa_device.hh
View file

@ -97,8 +97,8 @@ class DummyISADevice : public BaseISADevice
: BaseISADevice() {}
~DummyISADevice() {}
void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
void setMiscReg(int misc_reg, MiscReg val) override;
MiscReg readMiscReg(int misc_reg) override;
};
}

6
src/arch/arm/kvm/armv8_cpu.hh
View file

@ -83,11 +83,11 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
void dump() M5_ATTR_OVERRIDE;
void dump() override;
protected:
void updateKvmState() M5_ATTR_OVERRIDE;
void updateThreadContext() M5_ATTR_OVERRIDE;
void updateKvmState() override;
void updateThreadContext() override;
protected:
/** Mapping between integer registers in gem5 and KVM */

4
src/arch/arm/kvm/base_cpu.hh
View file

@ -52,10 +52,10 @@ class BaseArmKvmCPU : public BaseKvmCPU
BaseArmKvmCPU(BaseArmKvmCPUParams *params);
virtual ~BaseArmKvmCPU();
void startup() M5_ATTR_OVERRIDE;
void startup() override;
protected:
Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE;
Tick kvmRun(Tick ticks) override;
/** Cached state of the IRQ line */

20
src/arch/arm/kvm/gic.hh
View file

@ -76,23 +76,23 @@ class KvmGic : public BaseGic
KvmGic(const KvmGicParams *p);
~KvmGic();
void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
void startup() override { verifyMemoryMode(); }
void drainResume() override { verifyMemoryMode(); }
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(Checkpoint *cp, const std::string &sec) override;
public: // PioDevice
AddrRangeList getAddrRanges() const { return addrRanges; }
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
public: // BaseGic
void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
void sendInt(uint32_t num) override;
void clearInt(uint32_t num) override;
void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
void sendPPInt(uint32_t num, uint32_t cpu) override;
void clearPPInt(uint32_t num, uint32_t cpu) override;
protected:
/**

4
src/arch/arm/pagetable.hh
View file

@ -284,7 +284,7 @@ struct TlbEntry : public Serializable
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(longDescFormat);
SERIALIZE_SCALAR(pfn);
@ -314,7 +314,7 @@ struct TlbEntry : public Serializable
paramOut(cp, "domain", domain_);
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(longDescFormat);
UNSERIALIZE_SCALAR(pfn);

16
src/arch/arm/pmu.hh
View file

@ -96,10 +96,10 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
public: // SimObject and related interfaces
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void drainResume() M5_ATTR_OVERRIDE;
void drainResume() override;
public: // ISA Device interface
@ -109,14 +109,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
* @param misc_reg Register number (see miscregs.hh)
* @param val Value to store
*/
void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
void setMiscReg(int misc_reg, MiscReg val) override;
/**
* Read a register within the PMU.
*
* @param misc_reg Register number (see miscregs.hh)
* @return Register value.
*/
MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
MiscReg readMiscReg(int misc_reg) override;
protected: // PMU register types and constants
BitUnion32(PMCR_t)
@ -269,7 +269,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
: ProbeListenerArgBase(pm, name),
pmu(_pmu), id(_id) {}
void notify(const uint64_t &val) M5_ATTR_OVERRIDE
void notify(const uint64_t &val) override
{
pmu.handleEvent(id, val);
}
@ -329,8 +329,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
listeners.reserve(4);
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Add an event count to the counter and check for overflow.

4
src/arch/arm/table_walker.hh
View file

@ -891,8 +891,8 @@ class TableWalker : public MemObject
bool haveLargeAsid64() const { return _haveLargeAsid64; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
DrainState drain() M5_ATTR_OVERRIDE;
virtual void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
virtual void drainResume() override;
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);

8
src/arch/arm/tlb.hh
View file

@ -284,15 +284,15 @@ class TLB : public BaseTLB
bool callFromS2);
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
void drainResume() M5_ATTR_OVERRIDE;
void drainResume() override;
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void regStats();
void regProbePoints() M5_ATTR_OVERRIDE;
void regProbePoints() override;
/**
* Get the table walker master port. This is used for migrating

9
src/arch/arm/types.hh
View file

@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
@ -483,7 +482,7 @@ namespace ArmISA
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
@ -494,7 +493,7 @@ namespace ArmISA
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
@ -740,7 +739,7 @@ namespace ArmISA
} // namespace ArmISA
__hash_namespace_begin
namespace std {
template<>
struct hash<ArmISA::ExtMachInst> :
@ -752,6 +751,6 @@ struct hash<ArmISA::ExtMachInst> :
};
__hash_namespace_end
}
#endif

16
src/arch/generic/types.hh
View file

@ -105,14 +105,14 @@ class PCStateBase : public Serializable
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(_pc);
SERIALIZE_SCALAR(_npc);
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(_pc);
UNSERIALIZE_SCALAR(_npc);
@ -248,7 +248,7 @@ class UPCState : public SimplePCState<MachInst>
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
@ -256,7 +256,7 @@ class UPCState : public SimplePCState<MachInst>
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);
@ -329,14 +329,14 @@ class DelaySlotPCState : public SimplePCState<MachInst>
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_nnpc);
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_nnpc);
@ -426,7 +426,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_upc);
@ -434,7 +434,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst>
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_upc);

4
src/arch/mips/interrupts.hh
View file

@ -116,13 +116,13 @@ class Interrupts : public SimObject
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
fatal("Serialization of Interrupts Unimplemented for MIPS");
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
fatal("Unserialization of Interrupts Unimplemented for MIPS");
}

4
src/arch/mips/tlb.hh
View file

@ -107,8 +107,8 @@ class TLB : public BaseTLB
static Fault checkCacheability(RequestPtr &req);
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void regStats();

4
src/arch/power/tlb.hh
View file

@ -172,8 +172,8 @@ class TLB : public BaseTLB
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void regStats();
};

5
src/arch/power/types.hh
View file

@ -33,7 +33,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
namespace PowerISA
@ -89,7 +88,7 @@ typedef GenericISA::SimplePCState<MachInst> PCState;
} // PowerISA namespace
__hash_namespace_begin
namespace std {
template<>
struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
@ -98,6 +97,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> {
};
};
__hash_namespace_end
}
#endif // __ARCH_POWER_TYPES_HH__

4
src/arch/sparc/interrupts.hh
View file

@ -191,14 +191,14 @@ class Interrupts : public SimObject
}
void
serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
serialize(CheckpointOut &cp) const override
{
SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
SERIALIZE_SCALAR(intStatus);
}
void
unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
UNSERIALIZE_SCALAR(intStatus);

4
src/arch/sparc/isa.hh
View file

@ -167,8 +167,8 @@ class ISA : public SimObject
void clear();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc) {}

4
src/arch/sparc/system.hh
View file

@ -54,8 +54,8 @@ class SparcSystem : public System
* Serialization stuff
*/
public:
void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serializeSymtab(CheckpointOut &cp) const override;
void unserializeSymtab(CheckpointIn &cp) override;
/** reset binary symbol table */
SymbolTable *resetSymtab;

4
src/arch/sparc/tlb.hh
View file

@ -176,8 +176,8 @@ class TLB : public BaseTLB
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/** Give an entry id, read that tlb entries' tte */
uint64_t TteRead(int entry);

5
src/arch/x86/decoder.hh
View file

@ -32,6 +32,7 @@
#define __ARCH_X86_DECODER_HH__
#include <cassert>
#include <unordered_map>
#include <vector>
#include "arch/x86/regs/misc.hh"
@ -223,11 +224,11 @@ class Decoder
typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages;
DecodePages *decodePages;
typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap;
typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
AddrCacheMap addrCacheMap;
DecodeCache::InstMap *instMap;
typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
static InstCacheMap instCacheMap;
public:

4
src/arch/x86/interrupts.hh
View file

@ -293,8 +293,8 @@ class Interrupts : public BasicPioDevice, IntDevice
/*
* Serialization.
*/
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/*
* Old functions needed for compatability but which will be phased out

4
src/arch/x86/isa.hh
View file

@ -97,8 +97,8 @@ namespace X86ISA
return reg;
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void startup(ThreadContext *tc);

4
src/arch/x86/pagetable.hh
View file

@ -149,8 +149,8 @@ namespace X86ISA
return (1 << logBytes);
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
/** The size of each level of the page table expressed in base 2

5
src/arch/x86/regs/msr.hh
View file

@ -31,14 +31,15 @@
#ifndef __ARCH_X86_REG_MSR_HH__
#define __ARCH_X86_REG_MSR_HH__
#include <unordered_map>
#include "arch/x86/regs/misc.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
namespace X86ISA
{
typedef m5::hash_map<Addr, MiscRegIndex> MsrMap;
typedef std::unordered_map<Addr, MiscRegIndex> MsrMap;
/**
* Map between MSR addresses and their corresponding misc registers.

4
src/arch/x86/tlb.hh
View file

@ -148,8 +148,8 @@ namespace X86ISA
TlbEntry * insert(Addr vpn, TlbEntry &entry);
// Checkpointing
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Get the table walker master port. This is used for

5
src/arch/x86/types.hh
View file

@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/cprintf.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
@ -346,7 +345,7 @@ namespace X86ISA
}
__hash_namespace_begin
namespace std {
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
@ -362,7 +361,7 @@ __hash_namespace_begin
emi.stackSize ^ emi.dispSize;
};
};
__hash_namespace_end
}
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
// and UNSERIALIZE_SCALAR.

1
src/arch/x86/utility.hh
View file

@ -42,7 +42,6 @@
#include "arch/x86/regs/misc.hh"
#include "arch/x86/types.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"

29
src/base/compiler.hh
View file

@ -43,37 +43,8 @@
#ifndef __BASE_COMPILER_HH__
#define __BASE_COMPILER_HH__
// gcc C++11 status: http://gcc.gnu.org/projects/cxx0x.html
// clang C++11 status: http://clang.llvm.org/cxx_status.html
// http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html
/* Support for override control (final/override) */
#undef M5_COMP_HAS_OVERRIDE_CONTROL
#if defined(__GNUC__) && !defined(__clang__) /* Check for gcc */
# define M5_GCC_VERSION(maj, min) \
(__GNUC__ > (maj) || (__GNUC__ == (maj) && __GNUC_MINOR__ >= (min)))
# define M5_COMP_HAS_OVERRIDE_CONTROL M5_GCC_VERSION(4, 7)
#elif defined(__clang__) /* Check for clang */
# define M5_COMP_HAS_OVERRIDE_CONTROL __has_feature(cxx_override_control)
#else
# error "Need to define compiler options in base/compiler.hh"
#endif
#if M5_COMP_HAS_OVERRIDE_CONTROL
# define M5_ATTR_FINAL final
# define M5_ATTR_OVERRIDE override
#else
# define M5_ATTR_FINAL
# define M5_ATTR_OVERRIDE
#endif
#if defined(__GNUC__) // clang or gcc
# define M5_ATTR_NORETURN __attribute__((noreturn))
# define M5_DUMMY_RETURN

20
src/base/cp_annotate.hh
View file

@ -47,10 +47,10 @@
#include <map>
#include <memory>
#include <string>
#include <unordered_map>
#include <vector>
#include "base/loader/symtab.hh"
#include "base/hashmap.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/AnnotateQ.hh"
@ -127,7 +127,7 @@ class CPA
/**
* Provide a hash function for the CPI Id type
*/
__hash_namespace_begin
namespace std {
template <>
struct hash<std::pair<std::string, uint64_t> >
{
@ -139,7 +139,7 @@ struct hash<std::pair<std::string, uint64_t> >
}
};
__hash_namespace_end
}
class CPA : SimObject
{
@ -202,8 +202,8 @@ class CPA : SimObject
uint8_t cpu;
bool dump;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
typedef std::shared_ptr<AnnotateData> AnnDataPtr;
@ -236,12 +236,12 @@ class CPA : SimObject
uint64_t conId;
// Convert state strings into state ids
typedef m5::hash_map<std::string, int> SCache;
typedef std::unordered_map<std::string, int> SCache;
typedef std::vector<SCache> StCache;
// Convert sm and queue name,id into queue id
typedef std::pair<std::string, uint64_t> Id;
typedef m5::hash_map<Id, int> IdHCache;
typedef std::unordered_map<Id, int> IdHCache;
typedef std::vector<IdHCache> IdCache;
// Hold mapping of sm and queues to output python
@ -266,7 +266,7 @@ class CPA : SimObject
typedef std::map<int, int> LinkMap;
// SC Links
typedef m5::hash_map<Id, AnnDataPtr> ScHCache;
typedef std::unordered_map<Id, AnnDataPtr> ScHCache;
typedef std::vector<ScHCache> ScCache;
@ -540,8 +540,8 @@ class CPA : SimObject
void dump(bool all);
void dumpKey();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // !CP_ANNOTATE

4
src/base/framebuffer.hh
View file

@ -256,8 +256,8 @@ class FrameBuffer : public Serializable
virtual ~FrameBuffer();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Resize the frame buffer.

71
src/base/hashmap.hh
View file

@ -1,71 +0,0 @@
/*
* Copyright (c) 2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Andreas Hansson
*/
#ifndef __HASHMAP_HH__
#define __HASHMAP_HH__
// we stick with defines here until gcc >= 4.7 and clang >= 3.2 is
// adopted as these are the minimum versions to support variadic
// templates and template aliasing
#define hash_map unordered_map
#define hash_multimap unordered_multimap
#define hash_set unordered_set
#define hash_multiset unordered_multiset
// gcc >= 4.4 or clang with libc++ no longer rely on the transitional
// tr1 namespace
#include <unordered_map>
#include <unordered_set>
#define __hash_namespace std
#define __hash_namespace_begin namespace std {
#define __hash_namespace_end }
namespace m5 {
using ::__hash_namespace::hash_multimap;
using ::__hash_namespace::hash_multiset;
using ::__hash_namespace::hash_map;
using ::__hash_namespace::hash_set;
using ::__hash_namespace::hash;
}
#endif // __HASHMAP_HH__

7
src/base/inifile.hh
View file

@ -35,10 +35,9 @@
#include <fstream>
#include <list>
#include <string>
#include <unordered_map>
#include <vector>
#include "base/hashmap.hh"
/**
* @file
* Declaration of IniFile object.
@ -94,7 +93,7 @@ class IniFile
class Section
{
/// EntryTable type. Map of strings to Entry object pointers.
typedef m5::hash_map<std::string, Entry *> EntryTable;
typedef std::unordered_map<std::string, Entry *> EntryTable;
EntryTable table; ///< Table of entries.
mutable bool referenced; ///< Has this section been used?
@ -139,7 +138,7 @@ class IniFile
};
/// SectionTable type. Map of strings to Section object pointers.
typedef m5::hash_map<std::string, Section *> SectionTable;
typedef std::unordered_map<std::string, Section *> SectionTable;
protected:
/// Hash of section names to Section object pointers.

4
src/base/pollevent.hh
View file

@ -60,8 +60,8 @@ class PollEvent : public Serializable
bool queued() { return queue != 0; }
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
class PollQueue

4
src/base/random.hh
View file

@ -104,8 +104,8 @@ class Random : public Serializable
return dist(gen);
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
extern Random random_mt;

4
src/base/trace.hh
View file

@ -101,9 +101,9 @@ class OstreamLogger : public Logger
{ }
void logMessage(Tick when, const std::string &name,
const std::string &message) M5_ATTR_OVERRIDE;
const std::string &message) override;
std::ostream &getOstream() M5_ATTR_OVERRIDE { return stream; }
std::ostream &getOstream() override { return stream; }
};
/** Get the current global debug logger. This takes ownership of the given

4
src/base/vnc/vncserver.hh
View file

@ -307,8 +307,8 @@ class VncServer : public VncInput
static const PixelConverter pixelConverter;
public:
void setDirty() M5_ATTR_OVERRIDE;
void frameBufferResized() M5_ATTR_OVERRIDE;
void setDirty() override;
void frameBufferResized() override;
};
#endif

6
src/cpu/base.hh
View file

@ -307,7 +307,7 @@ class BaseCPU : public MemObject
virtual void startup();
virtual void regStats();
void regProbePoints() M5_ATTR_OVERRIDE;
void regProbePoints() override;
void registerThreadContexts();
@ -399,7 +399,7 @@ class BaseCPU : public MemObject
*
* @param os The stream to serialize to.
*/
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
/**
* Reconstruct the state of this object from a checkpoint.
@ -412,7 +412,7 @@ class BaseCPU : public MemObject
* @param cp The checkpoint use.
* @param section The section name of this object.
*/
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) override;
/**
* Serialize a single thread.

6
src/cpu/checker/cpu.hh
View file

@ -189,8 +189,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
Counter numLoad;
Counter startNumLoad;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
@ -380,7 +380,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
void wakeup(ThreadID tid) override { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum) { }

9
src/cpu/decode_cache.hh
View file

@ -31,9 +31,10 @@
#ifndef __CPU_DECODE_CACHE_HH__
#define __CPU_DECODE_CACHE_HH__
#include <unordered_map>
#include "arch/isa_traits.hh"
#include "arch/types.hh"
#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/static_inst_fwd.hh"
@ -46,7 +47,7 @@ namespace DecodeCache
{
/// Hash for decoded instructions.
typedef m5::hash_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
typedef std::unordered_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
/// A sparse map from an Addr to a Value, stored in page chunks.
template<class Value>
@ -58,7 +59,7 @@ class AddrMap
Value items[TheISA::PageBytes];
};
// A map of cache pages which allows a sparse mapping.
typedef typename m5::hash_map<Addr, CachePage *> PageMap;
typedef typename std::unordered_map<Addr, CachePage *> PageMap;
typedef typename PageMap::iterator PageIt;
// Mini cache of recent lookups.
PageIt recent[2];
@ -75,7 +76,7 @@ class AddrMap
/// Attempt to find the CacheePage which goes with a particular
/// address. First check the small cache of recent results, then
/// actually look in the hash_map.
/// actually look in the hash map.
/// @param addr The address to look up.
CachePage *
getPage(Addr addr)

4
src/cpu/inst_pb_trace.hh
View file

@ -75,7 +75,7 @@ class InstPBTraceRecord : public InstRecord
* This implementation of dump calls InstPBTrace to output the contents to a
* protobuf file
*/
void dump() M5_ATTR_OVERRIDE;
void dump() override;
protected:
InstPBTrace& tracer;
@ -90,7 +90,7 @@ class InstPBTrace : public InstTracer
InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
StaticInstPtr si, TheISA::PCState pc, const
StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE;
StaticInstPtr mi = NULL) override;
protected:
/** One output stream for the entire simulation.

12
src/cpu/kvm/base.hh
View file

@ -84,13 +84,11 @@ class BaseKvmCPU : public BaseCPU
void startup();
void regStats();
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
void unserializeThread(CheckpointIn &cp,
ThreadID tid) M5_ATTR_OVERRIDE;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *cpu);
@ -100,7 +98,7 @@ class BaseKvmCPU : public BaseCPU
MasterPort &getDataPort() { return dataPort; }
MasterPort &getInstPort() { return instPort; }
void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE;
void wakeup(ThreadID tid = 0) override;
void activateContext(ThreadID thread_num);
void suspendContext(ThreadID thread_num);
void deallocateContext(ThreadID thread_num);

2
src/cpu/kvm/x86_cpu.hh
View file

@ -47,7 +47,7 @@ class X86KvmCPU : public BaseKvmCPU
void startup();
/** @{ */
void dump() const M5_ATTR_OVERRIDE;
void dump() const override;
void dumpFpuRegs() const;
void dumpIntRegs() const;
void dumpSpecRegs() const;

11
src/cpu/minor/cpu.hh
View file

@ -128,7 +128,7 @@ class MinorCPU : public BaseCPU
/** Starting, waking and initialisation */
void init();
void startup();
void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
void wakeup(ThreadID tid) override;
Addr dbg_vtophys(Addr addr);
@ -142,17 +142,16 @@ class MinorCPU : public BaseCPU
Counter totalInsts() const;
Counter totalOps() const;
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/** Serialize pipeline data */
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
/** Drain interface */
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
/** Signal from Pipeline that MinorCPU should signal that a drain
* is complete and set its drainState */
void signalDrainDone();

2
src/cpu/minor/pipeline.hh
View file

@ -126,7 +126,7 @@ class Pipeline : public Ticked
* stages and pipeline advance) */
void evaluate();
void countCycles(Cycles delta) M5_ATTR_OVERRIDE
void countCycles(Cycles delta) override
{
cpu.ppCycles->notify(delta);
}

11
src/cpu/o3/cpu.hh
View file

@ -338,9 +338,8 @@ class FullO3CPU : public BaseO3CPU
/** Is the CPU draining? */
bool isDraining() const { return drainState() == DrainState::Draining; }
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
public:
/** Executes a syscall.
@ -350,10 +349,10 @@ class FullO3CPU : public BaseO3CPU
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
/** Resumes execution after a drain. */
void drainResume() M5_ATTR_OVERRIDE;
void drainResume() override;
/**
* Commit has reached a safe point to drain a thread.
@ -640,7 +639,7 @@ class FullO3CPU : public BaseO3CPU
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();

1
src/cpu/o3/lsq_unit.hh
View file

@ -54,7 +54,6 @@
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"

4
src/cpu/o3/mem_dep_unit.hh
View file

@ -46,8 +46,8 @@
#include <list>
#include <memory>
#include <set>
#include <unordered_map>
#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "debug/MemDepUnit.hh"
@ -237,7 +237,7 @@ class MemDepUnit
/** Moves an entry to the ready list. */
inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
typedef typename MemDepHash::iterator MemDepHashIt;

4
src/cpu/o3/thread_state.hh
View file

@ -112,7 +112,7 @@ struct O3ThreadState : public ThreadState {
profilePC = 3;
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
void serialize(CheckpointOut &cp) const override
{
ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
@ -120,7 +120,7 @@ struct O3ThreadState : public ThreadState {
::serialize(*tc, cp);
}
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
void unserialize(CheckpointIn &cp) override
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a

2
src/cpu/pred/bpred_unit.hh
View file

@ -77,7 +77,7 @@ class BPredUnit : public SimObject
*/
void regStats();
void regProbePoints() M5_ATTR_OVERRIDE;
void regProbePoints() override;
/** Perform sanity checks after a drain. */
void drainSanityCheck() const;

4
src/cpu/simple/atomic.hh
View file

@ -191,8 +191,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);

7
src/cpu/simple/base.hh
View file

@ -93,7 +93,7 @@ class BaseSimpleCPU : public BaseCPU
public:
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
void wakeup(ThreadID tid) override;
virtual void init();
public:
Trace::InstRecord *traceData;
@ -152,9 +152,8 @@ class BaseSimpleCPU : public BaseCPU
virtual Counter totalInsts() const;
virtual Counter totalOps() const;
void serializeThread(CheckpointOut &cp,
ThreadID tid) const M5_ATTR_OVERRIDE;
void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
};

74
src/cpu/simple/exec_context.hh
View file

@ -160,23 +160,21 @@ class SimpleExecContext : public ExecContext {
{ }
/** Reads an integer register. */
IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
return thread->readIntReg(si->srcRegIdx(idx));
}
/** Sets an integer register to a value. */
void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
M5_ATTR_OVERRIDE
void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
{
numIntRegWrites++;
thread->setIntReg(si->destRegIdx(idx), val);
}
/** Reads a floating point register of single register width. */
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
M5_ATTR_OVERRIDE
FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@ -185,8 +183,7 @@ class SimpleExecContext : public ExecContext {
/** Reads a floating point register in its binary format, instead
* of by value. */
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
M5_ATTR_OVERRIDE
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@ -194,8 +191,8 @@ class SimpleExecContext : public ExecContext {
}
/** Sets a floating point register of single width to a value. */
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
M5_ATTR_OVERRIDE
void setFloatRegOperand(const StaticInst *si, int idx,
FloatReg val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
@ -205,37 +202,36 @@ class SimpleExecContext : public ExecContext {
/** Sets the bits of a floating point register of single width
* to a binary value. */
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val) M5_ATTR_OVERRIDE
FloatRegBits val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
}
CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
}
void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
M5_ATTR_OVERRIDE
void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
numCCRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
thread->setCCReg(reg_idx, val);
}
MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
M5_ATTR_OVERRIDE
void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val) override
{
numIntRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
@ -246,7 +242,7 @@ class SimpleExecContext : public ExecContext {
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE
MiscReg readMiscReg(int misc_reg) override
{
numIntRegReads++;
return thread->readMiscReg(misc_reg);
@ -256,18 +252,18 @@ class SimpleExecContext : public ExecContext {
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE
void setMiscReg(int misc_reg, const MiscReg &val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
}
PCState pcState() const M5_ATTR_OVERRIDE
PCState pcState() const override
{
return thread->pcState();
}
void pcState(const PCState &val) M5_ATTR_OVERRIDE
void pcState(const PCState &val) override
{
thread->pcState(val);
}
@ -278,7 +274,7 @@ class SimpleExecContext : public ExecContext {
*
* @note Only valid for memory ops.
*/
void setEA(Addr EA) M5_ATTR_OVERRIDE
void setEA(Addr EA) override
{ panic("BaseSimpleCPU::setEA() not implemented\n"); }
/**
@ -286,17 +282,17 @@ class SimpleExecContext : public ExecContext {
*
* @note Only valid for memory ops.
*/
Addr getEA() const M5_ATTR_OVERRIDE
Addr getEA() const override
{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
Fault readMem(Addr addr, uint8_t *data, unsigned int size,
unsigned int flags) M5_ATTR_OVERRIDE
unsigned int flags) override
{
return cpu->readMem(addr, data, size, flags);
}
Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE
unsigned int flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}
@ -304,7 +300,7 @@ class SimpleExecContext : public ExecContext {
/**
* Sets the number of consecutive store conditional failures.
*/
void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE
void setStCondFailures(unsigned int sc_failures) override
{
thread->setStCondFailures(sc_failures);
}
@ -312,7 +308,7 @@ class SimpleExecContext : public ExecContext {
/**
* Returns the number of consecutive store conditional failures.
*/
unsigned int readStCondFailures() const M5_ATTR_OVERRIDE
unsigned int readStCondFailures() const override
{
return thread->readStCondFailures();
}
@ -320,7 +316,7 @@ class SimpleExecContext : public ExecContext {
/**
* Executes a syscall specified by the callnum.
*/
void syscall(int64_t callnum) M5_ATTR_OVERRIDE
void syscall(int64_t callnum) override
{
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.");
@ -329,7 +325,7 @@ class SimpleExecContext : public ExecContext {
}
/** Returns a pointer to the ThreadContext. */
ThreadContext *tcBase() M5_ATTR_OVERRIDE
ThreadContext *tcBase() override
{
return thread->getTC();
}
@ -338,7 +334,7 @@ class SimpleExecContext : public ExecContext {
* Somewhat Alpha-specific function that handles returning from an
* error or interrupt.
*/
Fault hwrei() M5_ATTR_OVERRIDE
Fault hwrei() override
{
return thread->hwrei();
}
@ -347,17 +343,17 @@ class SimpleExecContext : public ExecContext {
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
*/
bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE
bool simPalCheck(int palFunc) override
{
return thread->simPalCheck(palFunc);
}
bool readPredicate() M5_ATTR_OVERRIDE
bool readPredicate() override
{
return thread->readPredicate();
}
void setPredicate(bool val) M5_ATTR_OVERRIDE
void setPredicate(bool val) override
{
thread->setPredicate(val);
@ -369,41 +365,41 @@ class SimpleExecContext : public ExecContext {
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
void demapPage(Addr vaddr, uint64_t asn) override
{
thread->demapPage(vaddr, asn);
}
void armMonitor(Addr address) M5_ATTR_OVERRIDE
void armMonitor(Addr address) override
{
cpu->armMonitor(thread->threadId(), address);
}
bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
bool mwait(PacketPtr pkt) override
{
return cpu->mwait(thread->threadId(), pkt);
}
void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
void mwaitAtomic(ThreadContext *tc) override
{
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
}
AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
AddressMonitor *getAddrMonitor() override
{
return cpu->getCpuAddrMonitor(thread->threadId());
}
#if THE_ISA == MIPS_ISA
MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
M5_ATTR_OVERRIDE
override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
void setRegOtherThread(int regIdx, MiscReg val,
ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE
ThreadID tid = InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");

9
src/cpu/simple/probes/simpoint.hh
View file

@ -41,7 +41,8 @@
#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
#include "base/hashmap.hh"
#include <unordered_map>
#include "cpu/simple_thread.hh"
#include "params/SimPoint.hh"
#include "sim/probe/probe.hh"
@ -59,7 +60,7 @@
typedef std::pair<Addr, Addr> BasicBlockRange;
/** Overload hash function for BasicBlockRange type */
__hash_namespace_begin
namespace std {
template <>
struct hash<BasicBlockRange>
{
@ -68,7 +69,7 @@ struct hash<BasicBlockRange>
return hash<Addr>()(bb.first + bb.second);
}
};
__hash_namespace_end
}
class SimPoint : public ProbeListenerObject
{
@ -109,7 +110,7 @@ class SimPoint : public ProbeListenerObject
};
/** Hash table containing all previously seen basic blocks */
m5::hash_map<BasicBlockRange, BBInfo> bbMap;
std::unordered_map<BasicBlockRange, BBInfo> bbMap;
/** Currently executing basic block */
BasicBlockRange currentBBV;
/** inst count in current basic block */

4
src/cpu/simple/timing.hh
View file

@ -272,8 +272,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);

4
src/cpu/simple_thread.hh
View file

@ -154,8 +154,8 @@ class SimpleThread : public ThreadState
void copyState(ThreadContext *oldContext);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void startup();
/***************************************************************

2
src/cpu/testers/rubytest/CheckTable.cc
View file

@ -112,7 +112,7 @@ CheckTable::getCheck(const Addr address)
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
auto i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;

4
src/cpu/testers/rubytest/CheckTable.hh
View file

@ -31,9 +31,9 @@
#define __CPU_RUBYTEST_CHECKTABLE_HH__
#include <iostream>
#include <unordered_map>
#include <vector>
#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
class Check;
@ -63,7 +63,7 @@ class CheckTable
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
m5::hash_map<Addr, Check*> m_lookup_map;
std::unordered_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;

11
src/cpu/testers/traffic_gen/traffic_gen.hh
View file

@ -41,7 +41,8 @@
#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#include "base/hashmap.hh"
#include <unordered_map>
#include "base/statistics.hh"
#include "cpu/testers/traffic_gen/generators.hh"
#include "mem/mem_object.hh"
@ -135,7 +136,7 @@ class TrafficGen : public MemObject
uint32_t currState;
/** Map of generator states */
m5::hash_map<uint32_t, BaseGen*> states;
std::unordered_map<uint32_t, BaseGen*> states;
/** Master port specialisation for the traffic generator */
class TrafficGenPort : public MasterPort
@ -198,10 +199,10 @@ class TrafficGen : public MemObject
void initState();
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/** Register statistics */
void regStats();

4
src/cpu/thread_state.hh
View file

@ -63,9 +63,9 @@ struct ThreadState : public Serializable {
virtual ~ThreadState();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) override;
int cpuId() const { return baseCpu->cpuId(); }

8
src/dev/alpha/backdoor.hh
View file

@ -76,8 +76,8 @@ class AlphaBackdoor : public BasicPioDevice
protected:
struct Access : public AlphaAccess, public Serializable
{
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
union {
@ -118,8 +118,8 @@ class AlphaBackdoor : public BasicPioDevice
/**
* standard serialization routines for checkpointing
*/
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_ALPHA_BACKDOOR_HH__

4
src/dev/alpha/tsunami.hh
View file

@ -124,8 +124,8 @@ class Tsunami : public Platform
*/
virtual Addr calcPciMemAddr(Addr addr);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_TSUNAMI_HH__

4
src/dev/alpha/tsunami_cchip.hh
View file

@ -131,8 +131,8 @@ class TsunamiCChip : public BasicPioDevice
*/
void reqIPI(uint64_t ipreq);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_CCHIP_HH__

4
src/dev/alpha/tsunami_io.hh
View file

@ -138,8 +138,8 @@ class TsunamiIO : public BasicPioDevice
*/
void clearPIC(uint8_t bitvector);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Start running.

4
src/dev/alpha/tsunami_pchip.hh
View file

@ -89,8 +89,8 @@ class TsunamiPChip : public BasicPioDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_PCHIP_HH__

4
src/dev/arm/energy_ctrl.hh
View file

@ -132,8 +132,8 @@ class EnergyCtrl : public BasicPioDevice
*/
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void startup();
void init();

6
src/dev/arm/flash_device.hh
View file

@ -62,11 +62,11 @@ class FlashDevice : public AbstractNVM
~FlashDevice();
/** Checkpoint functions*/
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
void checkDrain();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
/** Defines the possible actions to the flash*/

26
src/dev/arm/generic_timer.hh
View file

@ -93,8 +93,8 @@ class SystemCounter : public Serializable
void setKernelControl(uint32_t val) { _regCntkctl = val; }
uint32_t getKernelControl() { return _regCntkctl; }
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
// Disable copying
@ -189,8 +189,8 @@ class ArchTimer : public Serializable
/// Returns the value of the counter which this timer relies on.
uint64_t value() const;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
// Disable copying
@ -202,8 +202,8 @@ class GenericTimer : public SimObject
public:
GenericTimer(GenericTimerParams *p);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public:
void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val);
@ -262,10 +262,10 @@ class GenericTimerISA : public ArmISA::BaseISADevice
GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
: parent(_parent), cpu(_cpu) {}
void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE {
void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
parent.setMiscReg(misc_reg, cpu, val);
}
ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE {
ArmISA::MiscReg readMiscReg(int misc_reg) override {
return parent.readMiscReg(misc_reg, cpu);
}
@ -279,13 +279,13 @@ class GenericTimerMem : public PioDevice
public:
GenericTimerMem(GenericTimerMemParams *p);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public: // PioDevice
AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; }
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
AddrRangeList getAddrRanges() const override { return addrRanges; }
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
protected:
uint64_t ctrlRead(Addr addr, size_t size) const;

4
src/dev/arm/gic_pl390.hh
View file

@ -300,8 +300,8 @@ class Pl390 : public BaseGic
void driveIrqEn(bool state);
/** @} */
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
protected:
/** Handle a read to the distributor poriton of the GIC

10
src/dev/arm/gpu_nomali.hh
View file

@ -55,13 +55,13 @@ class NoMaliGpu : public PioDevice
virtual ~NoMaliGpu();
public: /* Checkpointing */
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public: /* IO device interfaces */
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE;
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
AddrRangeList getAddrRanges() const override;
private:
/**

32
src/dev/arm/hdlcd.hh
View file

@ -95,18 +95,18 @@ class HDLcd: public AmbaDmaDevice
HDLcd(const HDLcdParams *p);
~HDLcd();
void regStats() M5_ATTR_OVERRIDE;
void regStats() override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void drainResume() M5_ATTR_OVERRIDE;
void drainResume() override;
public: // IO device interface
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; }
AddrRangeList getAddrRanges() const override { return addrRanges; }
protected: // Parameters
VncInput *vnc;
@ -328,16 +328,16 @@ class HDLcd: public AmbaDmaDevice
void dumpSettings();
protected:
bool nextPixel(Pixel &p) M5_ATTR_OVERRIDE { return parent.pxlNext(p); }
bool nextPixel(Pixel &p) override { return parent.pxlNext(p); }
void onVSyncBegin() M5_ATTR_OVERRIDE { return parent.pxlVSyncBegin(); }
void onVSyncEnd() M5_ATTR_OVERRIDE { return parent.pxlVSyncEnd(); }
void onVSyncBegin() override { return parent.pxlVSyncBegin(); }
void onVSyncEnd() override { return parent.pxlVSyncEnd(); }
void onUnderrun(unsigned x, unsigned y) M5_ATTR_OVERRIDE {
void onUnderrun(unsigned x, unsigned y) override {
parent.pxlUnderrun();
}
void onFrameDone() M5_ATTR_OVERRIDE { parent.pxlFrameDone(); }
void onFrameDone() override { parent.pxlFrameDone(); }
protected:
HDLcd &parent;
@ -366,12 +366,12 @@ class HDLcd: public AmbaDmaDevice
void abortFrame();
void dumpSettings();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
protected:
void onEndOfBlock() M5_ATTR_OVERRIDE;
void onIdle() M5_ATTR_OVERRIDE;
void onEndOfBlock() override;
void onIdle() override;
HDLcd &parent;
const size_t lineSize;

4
src/dev/arm/kmi.hh
View file

@ -157,8 +157,8 @@ class Pl050 : public AmbaIntDevice, public VncKeyboard, public VncMouse
virtual void mouseAt(uint16_t x, uint16_t y, uint8_t buttons);
virtual void keyPress(uint32_t key, bool down);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_ARM_PL050_HH__

10
src/dev/arm/pl011.hh
View file

@ -60,15 +60,15 @@ class Pl011 : public Uart, public AmbaDevice
public:
Pl011(const Pl011Params *p);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public: // PioDevice
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
public: // Uart
void dataAvailable() M5_ATTR_OVERRIDE;
void dataAvailable() override;
protected: // Interrupt handling

4
src/dev/arm/pl111.hh
View file

@ -371,8 +371,8 @@ class Pl111: public AmbaDmaDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Determine the address ranges that this device responds to.

4
src/dev/arm/rtc_pl031.hh
View file

@ -125,8 +125,8 @@ class PL031 : public AmbaIntDevice
*/
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};

18
src/dev/arm/rv_ctrl.hh
View file

@ -171,17 +171,17 @@ class RealViewCtrl : public BasicPioDevice
* @param pkt The memory request.
* @param data Where to put the data.
*/
Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick read(PacketPtr pkt) override;
/**
* All writes are simply ignored.
* @param pkt The memory request.
* @param data the data
*/
Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public:
void registerDevice(DeviceFunc func, uint8_t site, uint8_t pos,
@ -206,14 +206,14 @@ class RealViewOsc
RealViewOsc(RealViewOscParams *p);
virtual ~RealViewOsc() {};
void startup() M5_ATTR_OVERRIDE;
void startup() override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public: // RealViewCtrl::Device interface
uint32_t read() const M5_ATTR_OVERRIDE;
void write(uint32_t freq) M5_ATTR_OVERRIDE;
uint32_t read() const override;
void write(uint32_t freq) override;
protected:
void clockPeriod(Tick clock_period);

8
src/dev/arm/timer_cpulocal.hh
View file

@ -145,8 +145,8 @@ class CpuLocalTimer : public BasicPioDevice
/** Handle write for a single timer */
void write(PacketPtr pkt, Addr daddr);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
friend class CpuLocalTimer;
};
@ -186,8 +186,8 @@ class CpuLocalTimer : public BasicPioDevice
*/
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};

8
src/dev/arm/timer_sp804.hh
View file

@ -121,8 +121,8 @@ class Sp804 : public AmbaPioDevice
/** Handle write for a single timer */
void write(PacketPtr pkt, Addr daddr);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
/** Pointer to the GIC for causing an interrupt */
@ -160,8 +160,8 @@ class Sp804 : public AmbaPioDevice
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};

6
src/dev/arm/ufs_device.hh
View file

@ -173,10 +173,10 @@ class UFSHostDevice : public DmaDevice
UFSHostDevice(const UFSHostDeviceParams* p);
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
void checkDrain();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
/**

8
src/dev/arm/vgic.hh
View file

@ -192,8 +192,8 @@ class VGic : public PioDevice
uint8_t VMBP;
uint8_t VMPriMask;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
@ -212,8 +212,8 @@ class VGic : public PioDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
Tick readVCpu(PacketPtr pkt);

12
src/dev/copy_engine.hh
View file

@ -106,11 +106,11 @@ class CopyEngine : public PciDevice
void channelRead(PacketPtr pkt, Addr daddr, int size);
void channelWrite(PacketPtr pkt, Addr daddr, int size);
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
private:
void fetchDescriptor(Addr address);
@ -204,8 +204,8 @@ class CopyEngine : public PciDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif //__DEV_COPY_ENGINE_HH__

8
src/dev/copy_engine_defs.hh
View file

@ -125,7 +125,7 @@ struct Regs : public Serializable {
uint32_t attnStatus; // Read clears
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
void serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(chanCount);
SERIALIZE_SCALAR(xferCap);
@ -133,7 +133,7 @@ struct Regs : public Serializable {
SERIALIZE_SCALAR(attnStatus);
}
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
void unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(chanCount);
UNSERIALIZE_SCALAR(xferCap);
@ -197,7 +197,7 @@ struct ChanRegs : public Serializable {
};
CHANERR error;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
void serialize(CheckpointOut &cp) const override
{
paramOut(cp, "ctrl", ctrl._data);
paramOut(cp, "status", status._data);
@ -207,7 +207,7 @@ struct ChanRegs : public Serializable {
paramOut(cp, "error", error._data);
}
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
void unserialize(CheckpointIn &cp) override
{
paramIn(cp, "ctrl", ctrl._data);
paramIn(cp, "status", status._data);

8
src/dev/disk_image.hh
View file

@ -36,8 +36,8 @@
#define __DISK_IMAGE_HH__
#include <fstream>
#include <unordered_map>
#include "base/hashmap.hh"
#include "params/CowDiskImage.hh"
#include "params/DiskImage.hh"
#include "params/RawDiskImage.hh"
@ -111,7 +111,7 @@ class CowDiskImage : public DiskImage
struct Sector {
uint8_t data[SectorSize];
};
typedef m5::hash_map<uint64_t, Sector *> SectorTable;
typedef std::unordered_map<uint64_t, Sector *> SectorTable;
protected:
std::string filename;
@ -129,8 +129,8 @@ class CowDiskImage : public DiskImage
void save(const std::string &file) const;
void writeback();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
virtual std::streampos size() const;

8
src/dev/dma_device.hh
View file

@ -148,7 +148,7 @@ class DmaPort : public MasterPort, public Drainable
bool dmaPending() const { return pendingCount > 0; }
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
};
class DmaDevice : public PioDevice
@ -238,11 +238,11 @@ class DmaReadFifo : public Drainable, public Serializable
~DmaReadFifo();
public: // Serializable
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public: // Drainable
DrainState drain() M5_ATTR_OVERRIDE;
DrainState drain() override;
public: // FIFO access
/**

4
src/dev/etherlink.hh
View file

@ -158,8 +158,8 @@ class EtherLink : public EtherObject
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};

4
src/dev/ethertap.hh
View file

@ -115,8 +115,8 @@ class EtherTap : public EtherObject
virtual bool recvPacket(EthPacketPtr packet);
virtual void sendDone();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
class EtherTapInt : public EtherInt

4
src/dev/i2cbus.hh
View file

@ -146,8 +146,8 @@ class I2CBus : public BasicPioDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif //__DEV_I2CBUS

20
src/dev/i8254xGBe.hh
View file

@ -329,8 +329,8 @@ class IGbE : public EtherDevice
void reset();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
virtual bool hasOutstandingEvents() {
return wbEvent.scheduled() || fetchEvent.scheduled();
@ -393,8 +393,8 @@ class IGbE : public EtherDevice
virtual bool hasOutstandingEvents();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
friend class RxDescCache;
@ -504,8 +504,8 @@ class IGbE : public EtherDevice
}
EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
friend class TxDescCache;
@ -535,11 +535,11 @@ class IGbE : public EtherDevice
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
DrainState drain() M5_ATTR_OVERRIDE;
void drainResume() M5_ATTR_OVERRIDE;
DrainState drain() override;
void drainResume() override;
};

4
src/dev/i8254xGBe_defs.hh
View file

@ -759,7 +759,7 @@ struct Regs : public Serializable {
uint32_t sw_fw_sync;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
void serialize(CheckpointOut &cp) const override
{
paramOut(cp, "ctrl", ctrl._data);
paramOut(cp, "sts", sts._data);
@ -805,7 +805,7 @@ struct Regs : public Serializable {
SERIALIZE_SCALAR(sw_fw_sync);
}
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
void unserialize(CheckpointIn &cp) override
{
paramIn(cp, "ctrl", ctrl._data);
paramIn(cp, "sts", sts._data);

4
src/dev/ide_ctrl.hh
View file

@ -154,7 +154,7 @@ class IdeController : public PciDevice
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __IDE_CTRL_HH_

4
src/dev/ide_disk.hh
View file

@ -365,8 +365,8 @@ class IdeDisk : public SimObject
inline Addr pciToDma(Addr pciAddr);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};

4
src/dev/mips/malta.hh
View file

@ -135,8 +135,8 @@ class Malta : public Platform
M5_DUMMY_RETURN
}
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_MALTA_HH__

4
src/dev/mips/malta_cchip.hh
View file

@ -133,8 +133,8 @@ class MaltaCChip : public BasicPioDevice
*/
void reqIPI(uint64_t ipreq);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __MALTA_CCHIP_HH__

4
src/dev/mips/malta_io.hh
View file

@ -130,8 +130,8 @@ class MaltaIO : public BasicPioDevice
/** Clear an Interrupt to the CPU */
void clearIntr(uint8_t interrupt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Start running.

4
src/dev/mips/malta_pchip.hh
View file

@ -88,8 +88,8 @@ class MaltaPChip : public BasicPioDevice
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __TSUNAMI_PCHIP_HH__

12
src/dev/multi_etherlink.hh
View file

@ -222,14 +222,14 @@ class MultiEtherLink : public EtherObject
}
virtual EtherInt *getEthPort(const std::string &if_name,
int idx) M5_ATTR_OVERRIDE;
int idx) override;
void memWriteback() M5_ATTR_OVERRIDE;
void init() M5_ATTR_OVERRIDE;
void startup() M5_ATTR_OVERRIDE;
void memWriteback() override;
void init() override;
void startup() override;
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_MULTIETHERLINK_HH__

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