cpu: add support for outputing a protobuf formatted CPU trace
Doesn't support x86 due to static instruction representation. --HG-- rename : src/cpu/CPUTracers.py => src/cpu/InstPBTrace.py
This commit is contained in:
Ali Saidi
parent
268d9e59c5
commit
4eff4fa12e
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@ -0,0 +1,37 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from m5.params import *
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from InstTracer import InstTracer
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class InstPBTrace(InstTracer):
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type = 'InstPBTrace'
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cxx_class = 'Trace::InstPBTrace'
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cxx_header = 'cpu/inst_pb_trace.hh'
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file_name = Param.String("Instruction trace output file")
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@ -35,6 +35,11 @@ if env['TARGET_ISA'] == 'null':
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Source('intr_control_noisa.cc')
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Return()
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# Only build the protocol buffer instructions tracer if we have protobuf support
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if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
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SimObject('InstPBTrace.py')
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Source('inst_pb_trace.cc')
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SimObject('CheckerCPU.py')
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SimObject('BaseCPU.py')
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@ -0,0 +1,178 @@
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/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
|
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
|
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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||||
* modified or unmodified, in source code or in binary form.
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||||
*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "cpu/inst_pb_trace.hh"
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#include "base/callback.hh"
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#include "base/output.hh"
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#include "config/the_isa.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "debug/ExecEnable.hh"
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#include "params/InstPBTrace.hh"
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#include "proto/inst.pb.h"
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#include "sim/core.hh"
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namespace Trace {
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ProtoOutputStream *InstPBTrace::traceStream;
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void
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InstPBTraceRecord::dump()
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{
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// We're trying to build an instruction trace so we just want macro-ops and
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// instructions that aren't macro-oped
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if ((macroStaticInst && staticInst->isFirstMicroop()) ||
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!staticInst->isMicroop()) {
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tracer.traceInst(thread, staticInst, pc);
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}
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// If this instruction accessed memory lets record it
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if (getMemValid())
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tracer.traceMem(staticInst, getAddr(), getSize(), getFlags());
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}
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InstPBTrace::InstPBTrace(const InstPBTraceParams *p)
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: InstTracer(p), curMsg(nullptr)
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{
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// Create our output file
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createTraceFile(p->file_name);
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}
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void
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InstPBTrace::createTraceFile(std::string filename)
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{
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// Since there is only one output file for all tracers check if it exists
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if (traceStream)
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return;
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traceStream = new ProtoOutputStream(simout.resolve(filename));
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// Output the header
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ProtoMessage::InstHeader header_msg;
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header_msg.set_obj_id("gem5 generated instruction trace");
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header_msg.set_ver(0);
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header_msg.set_tick_freq(SimClock::Frequency);
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header_msg.set_has_mem(true);
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traceStream->write(header_msg);
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// get a callback when we exit so we can close the file
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Callback *cb = new MakeCallback<InstPBTrace,
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&InstPBTrace::closeStreams>(this);
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registerExitCallback(cb);
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}
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void
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InstPBTrace::closeStreams()
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{
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if (curMsg) {
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traceStream->write(*curMsg);
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delete curMsg;
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curMsg = NULL;
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}
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if (!traceStream)
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return;
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delete traceStream;
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traceStream = NULL;
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}
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InstPBTrace::~InstPBTrace()
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{
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closeStreams();
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}
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InstPBTraceRecord*
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InstPBTrace::getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr si,
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TheISA::PCState pc, const StaticInstPtr mi)
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{
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// Only record the trace if Exec debugging in enabled
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if (!Trace::enabled || !Debug::ExecEnable)
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return NULL;
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return new InstPBTraceRecord(*this, when, tc, si, pc, mi);
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}
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void
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InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc)
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{
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if (curMsg) {
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/// @todo if we are running multi-threaded I assume we'd need a lock here
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traceStream->write(*curMsg);
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delete curMsg;
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curMsg = NULL;
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}
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// Create a new instruction message and fill out the fields
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curMsg = new ProtoMessage::Inst;
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curMsg->set_pc(pc.pc());
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curMsg->set_inst(static_cast<uint32_t>(bits(si->machInst, 31, 0)));
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curMsg->set_cpuid(tc->cpuId());
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curMsg->set_tick(curTick());
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curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
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curMsg->set_inst_flags(bits(si->machInst, 7, 0));
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}
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void
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InstPBTrace::traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f)
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{
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panic_if(!curMsg, "Memory access w/o msg?!");
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// We do a poor job identifying macro-ops that are load/stores
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curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
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ProtoMessage::Inst::MemAccess *mem_msg = curMsg->add_mem_access();
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mem_msg->set_addr(a);
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mem_msg->set_size(s);
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mem_msg->set_mem_flags(f);
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}
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} // namespace Trace
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Trace::InstPBTrace*
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InstPBTraceParams::create()
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{
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return new Trace::InstPBTrace(this);
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}
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@ -0,0 +1,135 @@
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/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __CPU_INST_PB_TRACE_HH__
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#define __CPU_INST_PB_TRACE_HH__
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#include "arch/types.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "cpu/static_inst_fwd.hh"
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#include "params/InstPBTrace.hh"
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#include "proto/protoio.hh"
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#include "sim/insttracer.hh"
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class ThreadContext;
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namespace ProtoMessage {
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class Inst;
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}
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namespace Trace {
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/**
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* This in an instruction tracer that records the flow of instructions through
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* multiple cpus and systems to a protobuf file specified by proto/inst.proto
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* for further analysis.
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*/
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class InstPBTraceRecord : public InstRecord
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{
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public:
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InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc,
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const StaticInstPtr si, TheISA::PCState pc,
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const StaticInstPtr mi = NULL)
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: InstRecord(when, tc, si, pc, mi), tracer(_tracer)
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{}
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/** called by the cpu when the instruction commits.
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* This implementation of dump calls InstPBTrace to output the contents to a
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* protobuf file
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*/
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void dump() M5_ATTR_OVERRIDE;
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protected:
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InstPBTrace& tracer;
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};
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class InstPBTrace : InstTracer
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{
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public:
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InstPBTrace(const InstPBTraceParams *p);
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virtual ~InstPBTrace();
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InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
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StaticInstPtr si, TheISA::PCState pc, const
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StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE;
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protected:
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/** One output stream for the entire simulation.
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* We encode the CPU & system ID so all we need is a single file
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*/
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static ProtoOutputStream *traceStream;
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/** This is the message were working on writing. The majority of the message
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* exists however the memory accesses will be delayed.
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*/
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ProtoMessage::Inst *curMsg;
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/** Create the output file and write the header into it
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* @param filename the file to create (if ends with .gz it will be
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* compressed)
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*/
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void createTraceFile(std::string filename);
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/** If there is a pending message still write it out and then close the file
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*/
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void closeStreams();
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/** Write an instruction to the trace file
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* @param tc thread context for the cpu ID
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* @param si for the machInst and opClass
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* @param pc for the PC Addr
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*/
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void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
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/** Write a memory request to the trace file as part of the cur instruction
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* @param si for the machInst and opClass
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* @param a address of the request
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* @param s size of the request
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* @param f flags for the request
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*/
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void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
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friend class InstPBTraceRecord;
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};
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} // namespace Trace
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#endif // __CPU_INST_PB_TRACE_HH__
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@ -42,4 +42,5 @@ Import('*')
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# Only build if we have protobuf support
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if env['HAVE_PROTOBUF']:
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ProtoBuf('packet.proto')
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ProtoBuf('inst.proto')
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Source('protoio.cc')
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@ -0,0 +1,107 @@
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// Copyright (c) 2014 ARM Limited
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// All rights reserved
|
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//
|
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// The license below extends only to copyright in the software and shall
|
||||
// not be construed as granting a license to any other intellectual
|
||||
// property including but not limited to intellectual property relating
|
||||
// to a hardware implementation of the functionality of the software
|
||||
// licensed hereunder. You may use the software subject to the license
|
||||
// terms below provided that you ensure that this notice is replicated
|
||||
// unmodified and in its entirety in all distributions of the software,
|
||||
// modified or unmodified, in source code or in binary form.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are
|
||||
// met: redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer;
|
||||
// redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution;
|
||||
// neither the name of the copyright holders nor the names of its
|
||||
// contributors may be used to endorse or promote products derived from
|
||||
// this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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//
|
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// Authors: Ali Saidi
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// Put all the generated messages in a namespace
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package ProtoMessage;
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// Packet header with the identifier describing what object captured
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// the trace, the version of this file format, and the tick frequency
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// for all the packet time stamps.
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message InstHeader {
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required string obj_id = 1;
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required uint32 ver = 2 [default = 0];
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required uint64 tick_freq = 3;
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required bool has_mem = 4;
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}
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message Inst {
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required uint64 pc = 1;
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required fixed32 inst = 2;
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optional uint32 nodeid = 3;
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optional uint32 cpuid = 4;
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optional fixed64 tick = 5;
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enum InstType {
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None = 0;
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IntAlu = 1;
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IntMul = 2;
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IntDiv = 3;
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FloatAdd = 4;
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FloatCmp = 5;
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FloatCvt = 6;
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FloatMult = 7;
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FloatDiv = 8;
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FloatSqrt = 9;
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SIMDIntAdd = 10;
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SIMDIntAddAcc = 11;
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SIMDIntAlu = 12;
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SIMDIntCmp = 13;
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SIMDIntCvt = 14;
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SIMDMisc = 15;
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SIMDIntMult = 16;
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SIMDIntMultAcc = 17;
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SIMDIntShift = 18;
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SIMDIntShiftAcc = 19;
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SIMDSqrt = 20;
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SIMDFloatAdd = 21;
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SIMDFloatAlu = 22;
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SIMDFloatCmp = 23;
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SIMDFloatCvt = 24;
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SIMDFloatDiv = 25;
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SIMDFloatMisc = 26;
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SIMDFloatMult = 27;
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SIMDFloatMultAdd = 28;
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SIMDFloatSqrt = 29;
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MemRead = 30;
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MemWrite = 31;
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IprAccess = 32;
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InstPrefetch = 33;
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}
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optional InstType type = 6; // add, mul, fp add, load, store, simd add, …
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optional uint32 inst_flags = 7; // execution mode information
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// If the operation does one or more memory accesses
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message MemAccess {
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required uint64 addr = 1;
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required uint32 size = 2;
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optional uint32 mem_flags = 3;
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}
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||||
repeated MemAccess mem_access = 8;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
#!/usr/bin/env python
|
||||
|
||||
# Copyright (c) 2013-2014 ARM Limited
|
||||
# All rights reserved
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
# Andreas Hansson
|
||||
|
||||
# This script is used to dump protobuf instruction traces to ASCII
|
||||
# format. It assumes that protoc has been executed and already
|
||||
# generated the Python package for the inst messages. This can
|
||||
# be done manually using:
|
||||
# protoc --python_out=. inst.proto
|
||||
# The ASCII trace format uses one line per request.
|
||||
|
||||
import protolib
|
||||
import sys
|
||||
|
||||
# Import the packet proto definitions
|
||||
try:
|
||||
import inst_pb2
|
||||
except:
|
||||
print "Did not find protobuf inst definitions, attempting to generate"
|
||||
from subprocess import call
|
||||
error = call(['protoc', '--python_out=util', '--proto_path=src/proto',
|
||||
'src/proto/inst.proto'])
|
||||
if not error:
|
||||
print "Generated inst proto definitions"
|
||||
|
||||
try:
|
||||
import google.protobuf
|
||||
except:
|
||||
print "Please install Python protobuf module"
|
||||
exit(-1)
|
||||
|
||||
import inst_pb2
|
||||
else:
|
||||
print "Failed to import inst proto definitions"
|
||||
exit(-1)
|
||||
|
||||
def main():
|
||||
if len(sys.argv) != 3:
|
||||
print "Usage: ", sys.argv[0], " <protobuf input> <ASCII output>"
|
||||
exit(-1)
|
||||
|
||||
# Open the file in read mode
|
||||
proto_in = protolib.openFileRd(sys.argv[1])
|
||||
|
||||
try:
|
||||
ascii_out = open(sys.argv[2], 'w')
|
||||
except IOError:
|
||||
print "Failed to open ", sys.argv[2], " for writing"
|
||||
exit(-1)
|
||||
|
||||
# Read the magic number in 4-byte Little Endian
|
||||
magic_number = proto_in.read(4)
|
||||
|
||||
if magic_number != "gem5":
|
||||
print "Unrecognized file", sys.argv[1]
|
||||
exit(-1)
|
||||
|
||||
print "Parsing instruction header"
|
||||
|
||||
# Add the packet header
|
||||
header = inst_pb2.InstHeader()
|
||||
protolib.decodeMessage(proto_in, header)
|
||||
|
||||
print "Object id:", header.obj_id
|
||||
print "Tick frequency:", header.tick_freq
|
||||
print "Memory addresses included:", header.has_mem
|
||||
|
||||
if header.ver != 0:
|
||||
print "Warning: file version newer than decoder:", header.ver
|
||||
print "This decoder may not understand how to decode this file"
|
||||
|
||||
|
||||
print "Parsing instructions"
|
||||
|
||||
num_insts = 0
|
||||
inst = inst_pb2.Inst()
|
||||
|
||||
# Decode the inst messages until we hit the end of the file
|
||||
optional_fields = ('tick', 'type', 'inst_flags', 'addr', 'size', 'mem_flags')
|
||||
while protolib.decodeMessage(proto_in, inst):
|
||||
# If we have a tick use it, otherwise count instructions
|
||||
if inst.HasField('tick'):
|
||||
tick = inst.tick
|
||||
else:
|
||||
tick = num_insts
|
||||
|
||||
if inst.HasField('nodeid'):
|
||||
node_id = inst.nodeid
|
||||
else:
|
||||
node_id = 0;
|
||||
if inst.HasField('cpuid'):
|
||||
cpu_id = inst.cpuid
|
||||
else:
|
||||
cpu_id = 0;
|
||||
|
||||
ascii_out.write('%-20d: (%03d/%03d) %#010x @ %#016x ' % (tick, node_id, cpu_id,
|
||||
inst.inst, inst.pc))
|
||||
|
||||
if inst.HasField('type'):
|
||||
ascii_out.write(' : %10s' % inst_pb2._INST_INSTTYPE.values_by_number[inst.type].name)
|
||||
|
||||
for mem_acc in inst.mem_access:
|
||||
ascii_out.write(" %#x-%#x;" % (mem_acc.addr, mem_acc.addr + mem_acc.size))
|
||||
|
||||
ascii_out.write('\n')
|
||||
num_insts += 1
|
||||
|
||||
print "Parsed instructions:", num_insts
|
||||
|
||||
# We're done
|
||||
ascii_out.close()
|
||||
proto_in.close()
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue