mem: hmc: adds controller
This patch models a simple HMC Controller. It simply schedules the incoming packets to HMC Serial Links using a round robin mechanism. This patch should be applied in series with other patches modeling a complete HMC device. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Erfan Azarkhish
parent
100cbc9cf6
commit
1530e1a690
73
src/mem/HMCController.py
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73
src/mem/HMCController.py
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Erfan Azarkhish
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from m5.params import *
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from XBar import *
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# References:
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# [1] http://www.open-silicon.com/open-silicon-ips/hmc/
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# [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link
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# Power Management and Two-Level Prefetching," TVLSI 2015
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# The HMCController class highlights the fact that a component is required
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# between host and HMC to convert the host protocol (AXI for example) to the
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# serial links protocol. Moreover, this component should have large internal
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# queueing to hide the access latency of the HMC.
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# Plus, this controller can implement more advanced global scheduling policies
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# and can reorder and steer transactions if required. A good example of such
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# component is available in [1].
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# Also in [2] there is a similar component which is connected to all serial
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# links, and it schedules the requests to the ones which are not busy.
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# These two references clarify two things:
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# 1. The serial links support the same address range and packets can travel
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# over any of them.
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# 2. One host can be connected to more than 1 serial link simply to achieve
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# higher bandwidth, and not for any other reason.
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# In this model, we have used a round-robin counter, because it is the
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# simplest way to schedule packets over the non-busy serial links. However,
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# more advanced scheduling algorithms are possible and even host can dedicate
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# each serial link to a portion of the address space and interleave packets
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# over them. Yet in this model, we have not made any such assumptions on the
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# address space.
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class HMCController(NoncoherentXBar):
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type = 'HMCController'
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cxx_header = "mem/hmc_controller.hh"
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@ -42,6 +42,7 @@ SimObject('ExternalSlave.py')
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SimObject('MemObject.py')
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SimObject('SimpleMemory.py')
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SimObject('XBar.py')
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SimObject('HMCController.py')
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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@ -64,6 +65,7 @@ Source('snoop_filter.cc')
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Source('stack_dist_calc.cc')
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Source('tport.cc')
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Source('xbar.cc')
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Source('hmc_controller.cc')
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if env['TARGET_ISA'] != 'null':
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Source('fs_translating_port_proxy.cc')
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@ -101,6 +103,7 @@ DebugFlag('MemoryAccess')
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DebugFlag('PacketQueue')
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DebugFlag('StackDist')
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DebugFlag("DRAMSim2")
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DebugFlag('HMCController')
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DebugFlag("MemChecker")
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DebugFlag("MemCheckerMonitor")
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120
src/mem/hmc_controller.cc
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120
src/mem/hmc_controller.cc
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#include "base/random.hh"
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#include "debug/HMCController.hh"
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#include "mem/hmc_controller.hh"
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HMCController::HMCController(const HMCControllerParams* p) :
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NoncoherentXBar(p),
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n_master_ports(p->port_master_connection_count),
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rr_counter(0)
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{
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assert(p->port_slave_connection_count == 1);
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}
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HMCController*
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HMCControllerParams::create()
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{
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return new HMCController(this);
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}
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// Since this module is a load distributor, all its master ports have the same
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// range so we should keep only one of the ranges and ignore the others
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void HMCController::recvRangeChange(PortID master_port_id)
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{
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if (master_port_id == 0)
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{
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gotAllAddrRanges = true;
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BaseXBar::recvRangeChange(master_port_id);
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}
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else
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gotAddrRanges[master_port_id] = true;
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}
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int HMCController::rotate_counter()
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{
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int current_value = rr_counter;
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rr_counter++;
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if (rr_counter == n_master_ports)
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rr_counter = 0;
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return current_value;
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}
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bool HMCController::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
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{
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// determine the source port based on the id
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SlavePort *src_port = slavePorts[slave_port_id];
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// we should never see express snoops on a non-coherent component
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assert(!pkt->isExpressSnoop());
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// For now, this is a simple round robin counter, for distribution the
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// load among the serial links
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PortID master_port_id = rotate_counter();
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// test if the layer should be considered occupied for the current
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// port
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if (!reqLayers[master_port_id]->tryTiming(src_port)) {
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x BUSY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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return false;
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}
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// store size and command as they might be modified when
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// forwarding the packet
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unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
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unsigned int pkt_cmd = pkt->cmdToIndex();
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// store the old header delay so we can restore it if needed
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Tick old_header_delay = pkt->headerDelay;
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// a request sees the frontend and forward latency
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Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
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// set the packet header and payload delay
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calcPacketTiming(pkt, xbar_delay);
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// determine how long to be layer is busy
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Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
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// before forwarding the packet (and possibly altering it),
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// remember if we are expecting a response
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const bool expect_response = pkt->needsResponse() &&
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!pkt->memInhibitAsserted();
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// since it is a normal request, attempt to send the packet
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bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
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if (!success) {
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// inhibited packets should never be forced to retry
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assert(!pkt->memInhibitAsserted());
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DPRINTF(HMCController, "recvTimingReq: src %s %s 0x%x RETRY\n",
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src_port->name(), pkt->cmdString(), pkt->getAddr());
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// restore the header delay as it is additive
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pkt->headerDelay = old_header_delay;
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// occupy until the header is sent
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reqLayers[master_port_id]->failedTiming(src_port,
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clockEdge(Cycles(1)));
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return false;
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}
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// remember where to route the response to
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if (expect_response) {
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assert(routeTo.find(pkt->req) == routeTo.end());
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routeTo[pkt->req] = slave_port_id;
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}
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reqLayers[master_port_id]->succeededTiming(packetFinishTime);
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// stats updates
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pktCount[slave_port_id][master_port_id]++;
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pktSize[slave_port_id][master_port_id] += pkt_size;
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transDist[pkt_cmd]++;
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return true;
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}
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103
src/mem/hmc_controller.hh
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103
src/mem/hmc_controller.hh
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@ -0,0 +1,103 @@
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/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2015 The University of Bologna
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
|
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erfan Azarkhish
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*/
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/**
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* @file
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* HMCController declaration
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*/
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#ifndef __HMC_CONTROLLER__
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#define __HMC_CONTROLLER__
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#include "mem/noncoherent_xbar.hh"
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#include "mem/port.hh"
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#include "params/HMCController.hh"
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/**
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* HMC Controller, in general, is responsible for translating the host
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* protocol (AXI for example) to serial links protocol. Plus, it should have
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* large internal buffers to hide the access latency of the cube. It is also
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* inferred from the standard [1] and the literature [2] that serial links
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* share the same address range and packets can travel over any of them, so a
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* load distribution mechanism is required.
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* This model simply queues the incoming transactions (using a Bridge) and
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* schedules them to the serial links using a simple round robin mechanism to
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* balance the load among them. More advanced global scheduling policies and
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* reordering and steering of transactions can be added to this model if
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* required [3].
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* [1] http://www.hybridmemorycube.org/specification-download/
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* [2] Low-Power Hybrid Memory Cubes With Link Power Manageme and Two-Level
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* Prefetching (J. Ahn et. al)
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* [3] The Open-Silicon HMC Controller IP
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* http://www.open-silicon.com/open-silicon-ips/hmc/
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*/
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class HMCController : public NoncoherentXBar
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{
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public:
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HMCController(const HMCControllerParams *p);
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private:
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// Receive range change only on one of the ports (because they all have
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// the same range)
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virtual void recvRangeChange(PortID master_port_id);
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// Receive a request and distribute it among slave ports
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// Simply forwards the packet to the next serial link based on a
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// Round-robin counter
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virtual bool recvTimingReq(PacketPtr pkt, PortID slave_port_id);
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int n_master_ports;
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// The round-robin counter
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int rr_counter;
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/**
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* Function for rotating the round robin counter
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* @return the next value of the counter
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*/
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int rotate_counter();
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};
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#endif //__HMC_CONTROLLER__
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