mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It highly reuses the existing components in gem5's general memory system with some small modifications. This changeset requires additional patches to model a complete HMC device. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Erfan Azarkhish
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100cbc9cf6
238
configs/common/HMC.py
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238
configs/common/HMC.py
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Erfan Azarkhish
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# A Simplified model of a complete HMC device. Based on:
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# [1] http://www.hybridmemorycube.org/specification-download/
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# [2] High performance AXI-4.0 based interconnect for extensible smart memory
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# cubes(E. Azarkhish et. al)
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# [3] Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level
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# Prefetching (J. Ahn et. al)
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# [4] Memory-centric system interconnect design with Hybrid Memory Cubes
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# (G. Kim et. al)
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# [5] Near Data Processing, Are we there yet? (M. Gokhale)
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# http://www.cs.utah.edu/wondp/gokhale.pdf
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#
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# This script builds a complete HMC device composed of vault controllers,
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# serial links, the main internal crossbar, and an external hmc controller.
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#
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# - VAULT CONTROLLERS:
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# Instances of the HMC_2500_x32 class with their functionality specified in
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# dram_ctrl.cc
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#
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# - THE MAIN XBAR:
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# This component is simply an instance of the NoncoherentXBar class, and its
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# parameters are tuned to [2].
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#
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# - SERIAL LINKS:
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# SerialLink is a simple variation of the Bridge class, with the ability to
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# account for the latency of packet serialization. We assume that the
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# serializer component at the transmitter side does not need to receive the
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# whole packet to start the serialization. But the deserializer waits for
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# the complete packet to check its integrity first.
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# * Bandwidth of the serial links is not modeled in the SerialLink component
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# itself. Instead bandwidth/port of the HMCController has been adjusted to
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# reflect the bandwidth delivered by 1 serial link.
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#
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# - HMC CONTROLLER:
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# Contains a large buffer (modeled with Bridge) to hide the access latency
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# of the memory cube. Plus it simply forwards the packets to the serial
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# links in a round-robin fashion to balance load among them.
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# * It is inferred from the standard [1] and the literature [3] that serial
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# links share the same address range and packets can travel over any of
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# them so a load distribution mechanism is required among them.
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import optparse
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import m5
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from m5.objects import *
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# A single Hybrid Memory Cube (HMC)
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class HMCSystem(SimOject):
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#*****************************CROSSBAR PARAMETERS*************************
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# Flit size of the main interconnect [1]
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xbar_width = Param.Unsigned( 32, "Data width of the main XBar (Bytes)")
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# Clock frequency of the main interconnect [1]
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# This crossbar, is placed on the logic-based of the HMC and it has its
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# own voltage and clock domains, different from the DRAM dies or from the
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# host.
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xbar_frequency = Param.Frequency('1GHz', "Clock Frequency of the main "
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"XBar")
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# Arbitration latency of the HMC XBar [1]
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xbar_frontend_latency = Param.Cycles(1, "Arbitration latency of the XBar")
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# Latency to forward a packet via the interconnect [1](two levels of FIFOs
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# at the input and output of the inteconnect)
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xbar_forward_latency = Param.Cycles(2, "Forward latency of the XBar")
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# Latency to forward a response via the interconnect [1](two levels of
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# FIFOs at the input and output of the inteconnect)
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xbar_response_latency = Param.Cycles(2, "Response latency of the XBar")
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#*****************************SERIAL LINK PARAMETERS**********************
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# Number of serial links [1]
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num_serial_links = Param.Unsigned(4, "Number of serial links")
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# Number of packets (not flits) to store at the request side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_req = Param.Unsigned( 16, "Number of packets to buffer "
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"at the request side of the serial link")
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# Number of packets (not flits) to store at the response side of the serial
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# link. This number should be adjusted to achive required bandwidth
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link_buffer_size_rsp = Param.Unsigned( 16, "Number of packets to buffer "
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"at the response side of the serial link")
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# Latency of the serial link composed by SER/DES latency (1.6ns [4]) plus
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# the PCB trace latency (3ns Estimated based on [5])
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link_latency = Param.Latency('4.6ns', "Latency of the serial links")
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# Header overhead of the serial links: Header size is 128bits in HMC [1],
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# and we have 16 lanes, so the overhead is 8 cycles
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link_overhead = Param.Cycles(8, "The number of cycles required to"
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" transmit the packet header over the serial link")
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# Clock frequency of the serial links [1]
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link_frequency = Param.Frequency('10GHz', "Clock Frequency of the serial"
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"links")
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# Number of parallel lanes in each serial link [1]
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num_lanes_per_link = Param.Unsigned( 16, "Number of lanes per each link")
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# Number of serial links [1]
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num_serial_links = Param.Unsigned( 4, "Number of serial links")
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#*****************************HMC CONTROLLER PARAMETERS*******************
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# Number of packets (not flits) to store at the HMC controller. This
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# number should be high enough to be able to hide the high latency of HMC
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ctrl_buffer_size_req = Param.Unsigned( 256, "Number of packets to buffer "
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"at the HMC controller (request side)")
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# Number of packets (not flits) to store at the response side of the HMC
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# controller.
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ctrl_buffer_size_rsp = Param.Unsigned( 256, "Number of packets to buffer "
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"at the HMC controller (response side)")
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# Latency of the HMC controller to process the packets
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# (ClockDomain = Host clock domain)
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ctrl_latency = Param.Cycles(4, "The number of cycles required for the "
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" controller to process the packet")
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# Wiring latency from the SoC crossbar to the HMC controller
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ctrl_static_latency = Param.Latency('500ps', "Static latency of the HMC"
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"controller")
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#*****************************PERFORMANCE MONITORING**********************
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# The main monitor behind the HMC Controller
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enable_global_monitor = Param.Bool(True, "The main monitor behind the "
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"HMC Controller")
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# The link performance monitors
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enable_link_monitor = Param.Bool(True, "The link monitors" )
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# Create an HMC device and attach it to the current system
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def config_hmc(options, system):
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system.hmc=HMCSystem()
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system.buffer = Bridge(ranges=system.mem_ranges,
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req_size=system.hmc.ctrl_buffer_size_req,
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resp_size=system.hmc.ctrl_buffer_size_rsp,
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delay=system.hmc.ctrl_static_latency)
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try:
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system.hmc.enable_global_monitor = options.enable_global_monitor
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except:
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pass;
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try:
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system.hmc.enable_link_monitor = options.enable_link_monitor
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except:
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pass;
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system.membus.master = system.buffer.slave
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# The HMC controller (Clock domain is the same as the host)
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system.hmccontroller = HMCController(width=(system.hmc.num_lanes_per_link.
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value * system.hmc.num_serial_links/8),
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frontend_latency=system.hmc.ctrl_latency,
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forward_latency=system.hmc.link_overhead,
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response_latency=system.hmc.link_overhead)
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system.hmccontroller.clk_domain = SrcClockDomain(clock=system.hmc.
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link_frequency, voltage_domain = VoltageDomain(voltage = '1V'))
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# Serial Links
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system.hmc.seriallink =[ SerialLink(ranges = system.mem_ranges,
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req_size=system.hmc.link_buffer_size_req,
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resp_size=system.hmc.link_buffer_size_rsp,
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num_lanes=system.hmc.num_lanes_per_link,
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delay=system.hmc.link_latency)
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for i in xrange(system.hmc.num_serial_links)]
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if system.hmc.enable_link_monitor:
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system.hmc.lmonitor = [ CommMonitor()
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for i in xrange(system.hmc.num_serial_links)]
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# The HMC Crossbar located in its logic-base (LoB)
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system.hmc.xbar = NoncoherentXBar(width = system.hmc.xbar_width,
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frontend_latency=system.hmc.xbar_frontend_latency,
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forward_latency=system.hmc.xbar_forward_latency,
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response_latency=system.hmc.xbar_response_latency )
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system.hmc.xbar.clk_domain = SrcClockDomain(clock =
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system.hmc.xbar_frequency, voltage_domain =
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VoltageDomain(voltage = '1V'))
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if system.hmc.enable_global_monitor:
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system.gmonitor = CommMonitor()
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system.buffer.master = system.gmonitor.slave
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system.gmonitor.master = system.hmccontroller.slave
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else:
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system.hmccontroller.slave = system.buffer.master
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for i in xrange(system.hmc.num_serial_links):
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system.hmccontroller.master = system.hmc.seriallink[i].slave
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system.hmc.seriallink[i].clk_domain = system.hmccontroller.clk_domain;
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if system.hmc.enable_link_monitor:
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system.hmc.seriallink[i].master = system.hmc.lmonitor[i].slave
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system.hmc.lmonitor[i].master = system.hmc.xbar.slave
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else:
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system.hmc.seriallink[i].master = system.hmc.xbar.slave
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@ -39,6 +39,7 @@
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import m5.objects
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import inspect
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import sys
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import HMC
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from textwrap import TextWrapper
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# Dictionary of mapping names of real memory controller models to
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@ -151,6 +152,14 @@ def config_mem(options, system):
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them.
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"""
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if ( options.mem_type == "HMC_2500_x32"):
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HMC.config_hmc(options, system)
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subsystem = system.hmc
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xbar = system.hmc.xbar
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else:
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subsystem = system
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xbar = system.membus
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if options.tlm_memory:
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system.external_memory = m5.objects.ExternalSlave(
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port_type="tlm",
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@ -161,11 +170,11 @@ def config_mem(options, system):
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return
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if options.external_memory_system:
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system.external_memory = m5.objects.ExternalSlave(
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subsystem.external_memory = m5.objects.ExternalSlave(
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port_type=options.external_memory_system,
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port_data="init_mem0", port=system.membus.master,
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port_data="init_mem0", port=xbar.master,
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addr_ranges=system.mem_ranges)
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system.kernel_addr_check = False
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subsystem.kernel_addr_check = False
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return
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nbr_mem_ctrls = options.mem_channels
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@ -199,8 +208,8 @@ def config_mem(options, system):
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mem_ctrls.append(mem_ctrl)
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system.mem_ctrls = mem_ctrls
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subsystem.mem_ctrls = mem_ctrls
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# Connect the controllers to the membus
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for i in xrange(len(system.mem_ctrls)):
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system.mem_ctrls[i].port = system.membus.master
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for i in xrange(len(subsystem.mem_ctrls)):
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subsystem.mem_ctrls[i].port = xbar.master
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@ -215,6 +215,7 @@ def build_test_system(np):
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test_sys.cpu[i].createThreads()
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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return test_sys
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