gem5/src
Radhika Jagtap 3080bbcc36 cpu: Create record type enum for elastic traces
This patch replaces the booleans that specified the elastic trace record
type with an enum type. The source of change is the proto message for
elastic trace where the enum is introduced. The struct definitions in the
elastic trace probe listener as well as the Trace CPU replace the boleans
with the proto message enum.

The patch does not impact functionality, but traces are not compatible with
previous version. This is preparation for adding new types of records in
subsequent patches.
2015-12-07 16:42:16 -06:00
..
arch arm, config: Automatically discover available platforms 2015-12-04 00:19:05 +00:00
base sim: Add support for generating back traces on errors 2015-12-04 00:12:58 +00:00
cpu cpu: Create record type enum for elastic traces 2015-12-07 16:42:16 -06:00
dev dev: Rewrite PCI host functionality 2015-12-05 00:11:24 +00:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem mem: Add instruction sequence number to request 2015-12-07 16:42:15 -06:00
proto cpu: Create record type enum for elastic traces 2015-12-07 16:42:16 -06:00
python config: Fix broken SimObject listing 2015-12-01 13:01:05 +00:00
sim sim: Get rid of the non-const serialize() method 2015-12-04 09:48:48 +00:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00