gem5/src
Andreas Sandberg f7055e9215 dev, arm: Rewrite the HDLCD controller
Rewrite the HDLCD controller to use the new DMA engine and pixel
pump. This fixes several bugs in the current implementation:

   * Broken/missing interrupt support (VSync, underrun, DMA end)
   * Fragile resolution changes (changing resolutions used
     to cause assertion errors).
   * Support for resolutions with a width that isn't divisible by 32.
   * The pixel clock can now be set dynamically.

This breaks checkpoint compatibility. Checkpoints can be upgraded with
the checkpoint conversion script. However, upgraded checkpoints won't
contain the state of the current frame. That means that HDLCD
controllers restoring from a converted checkpoint immediately start
drawing a new frame (i.e, expect timing differences).
2015-09-11 15:55:46 +01:00
..
arch arm, mem: Remove unused CLEAR_LL request flag 2015-08-21 07:03:25 -04:00
base base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
cpu ruby: eliminate type uint64 and int64 2015-08-29 10:19:23 -05:00
dev dev, arm: Rewrite the HDLCD controller 2015-09-11 15:55:46 +01:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern style: change Process function calls to use camelCase 2015-07-24 12:25:23 -07:00
mem ruby: slicc: remove nextLineHack from Type.py 2015-09-08 19:32:04 -05:00
proto cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
python ruby: Expose MessageBuffers as SimObjects 2015-08-14 00:19:44 -05:00
sim sim: Fix time unit in abort message 2015-09-04 13:13:55 -04:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00