arm, mem: Remove unused CLEAR_LL request flag

Cleaning up dead code. The CLREX stores zero directly to
MISCREG_LOCKFLAG and so the request flag is no longer needed. The
corresponding functionality in the cache tags is also removed.
This commit is contained in:
Andreas Hansson 2015-08-21 07:03:25 -04:00
parent bda79817c8
commit 6eb434c8a2
8 changed files with 0 additions and 50 deletions

View file

@ -977,16 +977,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
"flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2,
scr, sctlr, flags, tranType);
// If this is a clrex instruction, provide a PA of 0 with no fault
// This will force the monitor to set the tracked address to 0
// a bit of a hack but this effectively clrears this processors monitor
if (flags & Request::CLEAR_LL){
// @todo: check implications of security extensions
req->setPaddr(0);
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
req->setFlags(Request::CLEAR_LL);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||
((!req->isInstFetch()) && (!sctlr.c))){
req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);

View file

@ -288,9 +288,6 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
pkt->req->isInstFetch() ? " (ifetch)" : "",
pkt->getAddr());
if (pkt->req->isClearLL())
tags->clearLocks();
// flush and invalidate any existing block
CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
if (old_blk && old_blk->isValid()) {

View file

@ -170,12 +170,6 @@ class BaseTags : public ClockedObject
*/
virtual void computeStats() {}
/**
*iterated through all blocks and clear all locks
*Needed to clear all lock tracking at once
*/
virtual void clearLocks() {}
/**
* Print all tags used
*/

View file

@ -135,14 +135,6 @@ BaseSetAssoc::findBlockBySetAndWay(int set, int way) const
return sets[set].blks[way];
}
void
BaseSetAssoc::clearLocks()
{
for (int i = 0; i < numBlocks; i++){
blks[i].clearLoadLocks();
}
}
std::string
BaseSetAssoc::print() const {
std::string cache_state;

View file

@ -380,12 +380,6 @@ public:
return ((tag << tagShift) | ((Addr)set << setShift));
}
/**
*iterated through all blocks and clear all locks
*Needed to clear all lock tracking at once
*/
virtual void clearLocks();
/**
* Called at end of simulation to complete average block reference stats.
*/

View file

@ -317,14 +317,6 @@ FALRU::check()
return true;
}
void
FALRU::clearLocks()
{
for (int i = 0; i < numBlocks; i++){
blks[i].clearLoadLocks();
}
}
FALRU *
FALRUParams::create()
{

View file

@ -305,12 +305,6 @@ public:
return (tag);
}
/**
*iterated through all blocks and clear all locks
*Needed to clear all lock tracking at once
*/
virtual void clearLocks();
/**
* @todo Implement as in lru. Currently not used
*/

View file

@ -123,8 +123,6 @@ class Request
STRICT_ORDER = 0x00000800,
/** This request is to a memory mapped register. */
MMAPPED_IPR = 0x00002000,
/** This request is a clear exclusive. */
CLEAR_LL = 0x00004000,
/** This request is made in privileged mode. */
PRIVILEGED = 0x00008000,
@ -655,7 +653,6 @@ class Request
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
bool isSecure() const { return _flags.isSet(SECURE); }
bool isPTWalk() const { return _flags.isSet(PT_WALK); }
};