cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT capable cpus are woken.
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a5c4eb3de9
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9e07a7504c
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@ -82,7 +82,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
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xc->setMiscReg(MISCREG_LOCKFLAG, false);
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// Implement ARMv8 WFE/SEV semantics
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xc->setMiscReg(MISCREG_SEV_MAILBOX, true);
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xc->getCpuPtr()->wakeup();
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xc->getCpuPtr()->wakeup(xc->threadId());
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}
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}
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@ -47,7 +47,7 @@ class BaseCPU
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public:
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static int numSimulatedInsts() { return 0; }
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static int numSimulatedOps() { return 0; }
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static void wakeup() { ; }
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static void wakeup(ThreadID tid) { ; }
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};
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#endif // __ARCH_NULL_CPU_DUMMY_HH__
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@ -290,7 +290,7 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
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}
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}
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if (FullSystem)
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cpu->wakeup();
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cpu->wakeup(0);
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}
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@ -220,14 +220,14 @@ class BaseCPU : public MemObject
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return interrupts[tid];
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}
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virtual void wakeup() = 0;
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virtual void wakeup(ThreadID tid) = 0;
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void
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postInterrupt(ThreadID tid, int int_num, int index)
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{
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interrupts[tid]->post(int_num, index);
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if (FullSystem)
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wakeup();
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wakeup(tid);
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}
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void
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@ -380,7 +380,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
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Fault hwrei() { return thread->hwrei(); }
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bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
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void wakeup() { }
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void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
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// Assume that the normal CPU's call to syscall was successful.
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// The checker's state would have already been updated by the syscall.
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void syscall(int64_t callnum) { }
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@ -408,7 +408,7 @@ BaseKvmCPU::verifyMemoryMode() const
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}
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void
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BaseKvmCPU::wakeup()
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BaseKvmCPU::wakeup(ThreadID tid)
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{
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DPRINTF(Kvm, "wakeup()\n");
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// This method might have been called from another
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@ -100,7 +100,7 @@ class BaseKvmCPU : public BaseCPU
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MasterPort &getDataPort() { return dataPort; }
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MasterPort &getInstPort() { return instPort; }
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void wakeup();
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void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE;
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void activateContext(ThreadID thread_num);
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void suspendContext(ThreadID thread_num);
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void deallocateContext(ThreadID thread_num);
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@ -167,14 +167,12 @@ MinorCPU::dbg_vtophys(Addr addr)
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}
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void
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MinorCPU::wakeup()
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MinorCPU::wakeup(ThreadID tid)
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{
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DPRINTF(Drain, "MinorCPU wakeup\n");
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DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid);
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for (auto i = threads.begin(); i != threads.end(); i ++) {
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if ((*i)->status() == ThreadContext::Suspended)
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(*i)->activate();
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}
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if (threads[tid]->status() == ThreadContext::Suspended)
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threads[tid]->activate();
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DPRINTF(Drain,"Suspended Processor awoke\n");
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}
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@ -241,7 +239,8 @@ MinorCPU::drainResume()
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"'timing' mode.\n");
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}
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wakeup();
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for (ThreadID tid = 0; tid < numThreads; tid++)
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wakeup(tid);
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pipeline->drainResume();
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}
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@ -128,7 +128,7 @@ class MinorCPU : public BaseCPU
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/** Starting, waking and initialisation */
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void init();
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void startup();
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void wakeup();
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void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
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Addr dbg_vtophys(Addr addr);
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@ -120,7 +120,7 @@ FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
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{
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup();
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cpu->wakeup(tid);
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}
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}
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lsq->recvTimingSnoopReq(pkt);
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@ -1633,15 +1633,15 @@ FullO3CPU<Impl>::wakeCPU()
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template <class Impl>
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void
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FullO3CPU<Impl>::wakeup()
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FullO3CPU<Impl>::wakeup(ThreadID tid)
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{
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if (this->thread[0]->status() != ThreadContext::Suspended)
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if (this->thread[tid]->status() != ThreadContext::Suspended)
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return;
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this->wakeCPU();
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DPRINTF(Quiesce, "Suspended Processor woken\n");
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this->threadContexts[0]->activate();
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this->threadContexts[tid]->activate();
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}
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template <class Impl>
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@ -640,7 +640,7 @@ class FullO3CPU : public BaseO3CPU
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/** Wakes the CPU, rescheduling the CPU if it's not already active. */
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void wakeCPU();
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virtual void wakeup();
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virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
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/** Gets a free thread id. Use if thread ids change across system. */
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ThreadID getFreeTid();
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@ -140,7 +140,7 @@ AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (tid != sender) {
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if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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wakeup();
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wakeup(tid);
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}
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TheISA::handleLockedSnoop(threadInfo[tid]->thread,
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@ -287,7 +287,7 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup();
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cpu->wakeup(tid);
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}
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}
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@ -313,7 +313,7 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
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AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup();
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cpu->wakeup(tid);
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}
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}
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@ -416,14 +416,13 @@ BaseSimpleCPU::dbg_vtophys(Addr addr)
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}
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void
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BaseSimpleCPU::wakeup()
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BaseSimpleCPU::wakeup(ThreadID tid)
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{
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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getCpuAddrMonitor(tid)->gotWakeup = true;
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if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
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DPRINTF(Quiesce,"Suspended Processor awoke\n");
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threadInfo[tid]->thread->activate();
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}
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getCpuAddrMonitor(tid)->gotWakeup = true;
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if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
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DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
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threadInfo[tid]->thread->activate();
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}
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}
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@ -93,7 +93,7 @@ class BaseSimpleCPU : public BaseCPU
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public:
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BaseSimpleCPU(BaseSimpleCPUParams *params);
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virtual ~BaseSimpleCPU();
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void wakeup();
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void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
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virtual void init();
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public:
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Trace::InstRecord *traceData;
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@ -545,7 +545,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (tid != sender) {
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if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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wakeup();
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wakeup(tid);
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}
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TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
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dcachePort.cacheBlockMask);
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@ -865,7 +865,7 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
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{
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup();
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cpu->wakeup(tid);
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}
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}
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@ -879,7 +879,7 @@ TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
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{
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for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
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if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
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cpu->wakeup();
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cpu->wakeup(tid);
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}
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}
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}
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@ -274,7 +274,8 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
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// architecture specifies that an event is
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// automatically generated when clearing the exclusive
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// monitor to wake up the processor in WFE.
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system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup();
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ThreadContext* ctx = system()->getThreadContext(i->contextId);
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ctx->getCpuPtr()->wakeup(ctx->threadId());
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i = lockedAddrList.erase(i);
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} else {
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i++;
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