9e07a7504c
Changes wakeup functionality so that only specific threads on SMT capable cpus are woken.
162 lines
4.8 KiB
C++
162 lines
4.8 KiB
C++
/*
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* Copyright (c) 2011-2012,2015 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Dave Greene
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* Nathan Binkert
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*/
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#ifndef __CPU_SIMPLE_BASE_HH__
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#define __CPU_SIMPLE_BASE_HH__
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#include "base/statistics.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/eventq.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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// forward declarations
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class Checkpoint;
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class Process;
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class Processor;
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class ThreadContext;
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namespace TheISA
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{
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class DTB;
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class ITB;
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}
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namespace Trace {
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class InstRecord;
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}
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struct BaseSimpleCPUParams;
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class BPredUnit;
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class SimpleExecContext;
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class BaseSimpleCPU : public BaseCPU
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{
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protected:
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ThreadID curThread;
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BPredUnit *branchPred;
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void checkPcEventQueue();
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void swapActiveThread();
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public:
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BaseSimpleCPU(BaseSimpleCPUParams *params);
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virtual ~BaseSimpleCPU();
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void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
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virtual void init();
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public:
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Trace::InstRecord *traceData;
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CheckerCPU *checker;
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std::vector<SimpleExecContext*> threadInfo;
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std::list<ThreadID> activeThreads;
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/** Current instruction */
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TheISA::MachInst inst;
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StaticInstPtr curStaticInst;
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StaticInstPtr curMacroStaticInst;
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protected:
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enum Status {
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Idle,
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Running,
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Faulting,
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ITBWaitResponse,
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IcacheRetry,
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IcacheWaitResponse,
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IcacheWaitSwitch,
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DTBWaitResponse,
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DcacheRetry,
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DcacheWaitResponse,
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DcacheWaitSwitch,
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};
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Status _status;
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public:
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Addr dbg_vtophys(Addr addr);
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void checkForInterrupts();
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void setupFetchRequest(Request *req);
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void preExecute();
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void postExecute();
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void advancePC(const Fault &fault);
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virtual void haltContext(ThreadID thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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virtual void startup();
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virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
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unsigned flags) = 0;
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virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
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unsigned flags, uint64_t* res) = 0;
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void countInst();
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virtual Counter totalInsts() const;
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virtual Counter totalOps() const;
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void serializeThread(CheckpointOut &cp,
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ThreadID tid) const M5_ATTR_OVERRIDE;
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void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
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};
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#endif // __CPU_SIMPLE_BASE_HH__
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