gem5/src
Michael LeBeane b181cea364 ruby: make DMASequencer inherit from RubyPort
This patch essentially rolls back 10518:30e3715c9405 to make RubyPort the
parent class of DMASequencer.  It removes redundant code and restores some
features which were lost when directly inheriting from MemObject.  For
example,
DMASequencer can now communicate to other devices using PIO, which is useful
for memmory-mapped communication between multiple DMADevices.
2016-02-14 20:28:48 -05:00
..
arch syscall_emul: Implement clock_getres() system call 2016-02-13 12:33:07 -05:00
base style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
cpu mem: Deduce if cache should forward snoops 2016-02-10 04:08:24 -05:00
dev style: eliminate explicit boolean comparisons 2016-02-06 17:21:20 -08:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
gpu-compute gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
kern misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem ruby: make DMASequencer inherit from RubyPort 2016-02-14 20:28:48 -05:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python configs: add command-line option to stop debug output 2016-02-13 12:36:43 -05:00
sim syscall_emul: Implement clock_getres() system call 2016-02-13 12:33:07 -05:00
unittest style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript scons: always generate sim/tags.cc 2016-02-08 13:39:45 -06:00