gem5/src
Andreas Hansson f5c4a45889 mem: Explicitly check MSHR snoops for cases not dealt with
Add a sanity check to make it explicit that we currently do not allow
an I/O coherent agent to directly issue writes into the coherent part
of the memory system (it has to go via a cache, and get transformed
into a read ex, upgrade or invalidation).
2015-12-28 11:14:18 -05:00
..
arch arm: remote GDB: rationalize structure of register offsets 2015-12-18 15:12:07 -06:00
base arm: remote GDB: rationalize structure of register offsets 2015-12-18 15:12:07 -06:00
cpu cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
dev dev: Add missing SConscript in src/dev/i2c 2015-12-10 18:46:02 +00:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem mem: Explicitly check MSHR snoops for cases not dealt with 2015-12-28 11:14:18 -05:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python dev: Move network devices to src/dev/net/ 2015-12-10 10:35:18 +00:00
sim sim: Use the old work item behavior by default 2015-12-18 10:14:17 +00:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00